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Mos transistor

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It's simple to understand mos concepts.

It's simple to understand mos concepts.

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  • 1. 11Slides adapted from:N. Weste, D. Harris, CMOS VLSI Design,© Addison-Wesley, 3/e, 2004MOS TransistorTheory2OutlineThe Big PictureMOS StructureIdeal I-V CharcteristicsMOS Capacitance ModelsNon ideal I-V EffectsPass transistor circuitsTristate InverterSwitch level RC Delay Models
  • 2. 23The Big PictureSo far, we have treated transistors as ideal switchesAn ON transistor passes a finite amount of currentDepends on terminal voltagesDerive current-voltage (I-V) relationshipsTransistor gate, source, drain all have capacitanceI = C (∆V/∆t) ∆t = (C/I) ∆VCapacitance and current determine speed4MOS Transistor Symbol
  • 3. 35MOS StructureGate and body formMOS capacitorOperating modesAccumulationDepletionInversion6nMOS Transistor Terminal VoltagesMode of operation depends on Vg, Vd, VsVgs = Vg – VsVgd = Vg – VdVds = Vd – Vs = Vgs - VgdSource and drain are symmetric diffusion terminalsBy convention, source is terminal at lower voltageHence Vds ≥ 0nMOS body is grounded. First assume source is 0 too.Three regions of operationCutoffLinearSaturationVgVsVdVgdVgsVds+-+-+-
  • 4. 47nMOS in cutoff operation modeNo channelIds = 08nMOS in linear operation modeChannel formsCurrent flows from D to Se- from S to DIds increases with VdsSimilar to linearresistor
  • 5. 59nMOS in Saturation operation modeChannel pinches offIds independent of VdsWe say current saturatesSimilar to current source10pMOS Transistor
  • 6. 611I-V Characteristics (nMOS)In Linear region, Ids depends onHow much charge is in the channel?How fast is the charge moving?12Channel ChargeMOS structure looks like parallelplate capacitor while operating ininversion:Gate – oxide – channelQchannel = CVC = Cg = εoxWL/tox = coxWLV = Vgc – Vt = (Vgs – Vds/2) – Vtcox = εox / tox
  • 7. 713Carrier velocityCharge is carried by e-Carrier velocity v proportional to lateralE-field between source and drainv = µE µ called mobilityE = Vds/LTime for carrier to cross channel:t = L / v14nMOS Linear I-VNow we knowHow much charge Qchannel is in the channelHow much time t each carrier takes to crosschannelox 22dsdsgs t dsdsgs t dsQItW VC V V VLVV V Vµβ= = − −   = − −  ox=WCLβ µ=
  • 8. 815nMOS Saturation I-VIf Vgd < Vt, channel pinches off near drainWhen Vds > Vdsat = Vgs – VtNow drain voltage no longer increases current( )222dsatds gs t dsatgs tVI V V VV Vββ = − −  = −16nMOS I-V Summary( )2cutofflinearsaturatio022ngs tdsds gs t ds ds dsatgs t ds dsatV VVI V V V V VV V V Vββ <  = − − <  − >first order transistor models
  • 9. 917I-V characteristics of nMOS Transistor18Example0.6 µm process from AMI Semiconductortox = 100 Åm = 350 cm2/V*sVt = 0.7 VPlot Ids vs. VdsVgs = 0, 1, 2, 3, 4, 5Use W/L = 4/2 λ( )14283.9 8.85 10350 120 /100 10oxW W WC A VL L Lβ µ µ−− • ⋅  = = =  ⋅   0 1 2 3 4 500.511.522.5VdsIds(mA)Vgs= 5Vgs= 4Vgs= 3Vgs= 2Vgs= 1
  • 10. 1019pMOS I-V CharacteriticsAll dopings and voltages are inverted for pMOSMobility µp is determined by holesTypically 2-3x lower than that of electrons µn120 cm2/V*s in AMI 0.6 mm processThus pMOS must be wider to provide samecurrentIn this class, assume µn / µp = 220pMOS I-V Summary( )2cutofflinearsaturatio022ngs tdsds gs t ds ds dsatgs t ds dsatV VVI V V V V VV V V Vββ <  = − − <  − >first order transistor models
  • 11. 1121I-V characteristics of pMOS Transistor22Capacitances of a MOS TransistorAny two conductors separated by an insulatorhave capacitanceGate to channel capacitor is very importantCreates channel charge necessary foroperation (intrinsic capacitance)Source and drain have capacitance to body(parasitic capacitance)Across reverse-biased diodesCalled diffusion capacitance because it isassociated with source/drain diffusion
  • 12. 1223Gate CapacitanceWhen the transistor is off, the channel is notinvertedCg = Cgb = εoxWL/tox = CoxWLLet’s call CoxWL = C0When the transistor is on, the channel extendsfrom the source to the drain (if the transistor isunsaturated, or to the pinchoff point otherwise)Cg = Cgb + Cgs + Cgd24Gate CapacitanceIn reality the gate overlaps source anddrain. Thus, the gate capacitance shouldinclude not only the intrinsic capacitancebut also parasitic overlap capacitances:Cgs(overlap) = Cox W LDCgs(overlap) = Cox W LD
  • 13. 1325Detailed Gate Capacitance2/3 C0+ CoxWLDC0/2 + CoxWLDCoxWLDCgs (total)CoxWLDC0/2 + CoxWLDCoxWLDCgd (total)00C0Cgb (total)SaturationLinearCutoffCapacitanceSource: M-S Kang, Y. Leblebici,CMOS Digital ICs, 3/e,2003, McGraw-Hill26Diffusion CapacitanceCsb, CdbUndesired capacitance (parasitic)Due to the reverse biased p-njunctions between source diffusionand body and drain diffusion and bodyCapacitance depends on area andperimeterUse small diffusion nodesComparable to Cg forcontacted diffusion½ Cg for uncontactedVaries with process
  • 14. 1427Lumped representation of theMOSFET capacitances28Non-ideal I-V effectsThe saturation current increases less than quadratically withincreasing VgsVelocity saturationMobility degradationChannel length modulationBody EffectLeakage currentsSub-threshold conductionJunction leakageTunnelingTemperature DependenceGeometry Dependence
  • 15. 1529Velocity saturation andmobility degradationAt strong lateral fieldsresulting from high Vds,drift velocity rolls off dueto carrier scattering andeventually saturatesStrong vertical fieldsresulting from large Vgscause the carriers toscatter against thesurface and also reducethe carrier mobility. Thiseffect is called mobilitydegradation30Channel length modulationThe reverse biased p-n junctionbetween the drain and the bodyforms a depletion region with lengthL’ that increases with Vdb. Thedepletion region effectively shortenthe channel length to: Leff = L – L’Assuming the source voltage isclose to the body votage Vdb ~ Vsb.Hence, increasing Vds decrease theeffective channel length.Shorter channel length results inhigher current
  • 16. 1631Body EffectThe potential difference between source andbody Vsb affects (increases) the thresholdvoltageThreshold voltage depends on:VsbProcessDopingTemperature32Subthreshold ConductionThe ideal transistor I-V model assumes current only flowsfrom source to drain when Vgs > Vt.In real transistors, current doesn’t abruptly cut off belowthreshold, but rather drop off exponentiallyThis leakage current when the transistor is nominally OFFdepends on:process (εox, tox)doping levels (NA, or ND)device geometry (W, L)temperature (T)( Subthreshold voltage (Vt) )
  • 17. 1733Junction LeakageThe p-n junctions between diffusion and the substrate orwell for diodes.The well-to-substrate is another diodeSubstrate and well are tied to GND and VDD to ensurethese diodes remain reverse biasedBut, reverse biased diodes still conduct a small amount ofcurrent that depends on:Doping levelsArea and perimeter of the diffusion regionThe diode voltage34TunnelingThere is a finite probability thatcarriers will tunnel though thegate oxide. This result in gateleakage current flowing intothe gateThe probability drops offexponentially with toxFor oxides thinner than15-20 Å, tunneling becomes afactor
  • 18. 1835Temperature dependenceTransistor characteristics areinfluenced by temperatureµ decreases with TVt decreases linearly with TIleakage increases with TON current decreases with TOFF current increases with TThus, circuit performances areworst at high temperature36Geometry DependenceLayout designers draw transistors with Wdrawn, LdrawnActual dimensions may differ from some factor XW and XLThe source and drain tend to diffuse laterally under thegate by LD, producing a shorter effective channelSimilarly, diffusion of the bulk by WD decreases theeffective channel widthIn process below 0.25 µm the effective length of thetransistor also depends significantly on the orientation ofthe transistor
  • 19. 1937Impact of non-ideal I-V effectsThreshold is a significant fraction of the supply voltageLeakage is increased causing gates toconsume power when idlelimits the amount of time that data is retainedLeakage increases with temperatureVelocity saturation and mobility degradationresult in less current than expected at high voltageNo point in trying to use high VDD to achieve fasttransistorsTransistors in series partition the voltage across eachtransistor thus experience less velocity saturationTend to be a little faster than a single transistorTwo nMOS in series deliver more than half thecurrent of a single nMOS transistor of the samewidthMatching: same dimension and orientation38Pass TransistorsnMOS pass transistors pull no higher than VDD-VtnCalled a degraded “1”Approach degraded value slowly (low Ids)pMOS pass transistors pull no lower than |Vtp|Called a degraded “0”Approach degraded value slowly (low Ids)
  • 20. 2039Pass transistor Circuits40Transmission gate ON resistance
  • 21. 2141Tri-state InverterIf the output is tri-stated but A toggles,charge from the internal nodes (= caps)may disturb the floating output node42Effective resistance of a transistorFirst-order transistor models have limited valueNot accurate enough for modern transistorsToo complicated for hand analysisSimplification: treat transistor as resistorReplace Ids(Vds, Vgs) with effective resistance RIds = Vds/RR averaged across switching range of digital gateToo inaccurate to predict current at any given timeBut good enough to predict RC delay (propagation delay of alogic gate)
  • 22. 2243RC ValuesCapacitanceC = Cg = Cs = Cd = 2 fF/µm of gate widthValues similar across many processesResistanceR ≈ 6 KΩ*µm in 0.6um processImproves with shorter channel lengthsUnit transistorsMay refer to minimum contacted device (4/2 λ)or maybe 1 µm wide deviceDoesn’t matter as long as you are consistent44RC Delay ModelsUse equivalent circuits for MOS transistorsideal switch + capacitance and ON resistanceunit nMOS has resistance R, capacitance Cunit pMOS has resistance 2R, capacitance CCapacitance proportional to widthResistance inversely proportional to width
  • 23. 2345Switch level RC models46Inverter Delay EstimateEstimate the delay of a fanout-of-1 inverterdelay = 6RC
  • 24. 2447Resistance of a unit transmission gateThe effective resistance of a transmission gate is theparallel of the resistance of the two transistorApproximately R in both directionsTransmission gates are commonly built using equal-sizedtransistorsBoosting the size of the pMOS only slightly improve theeffective resistance while significantly increasing thecapacitance48SummaryModels are only approximations to reality, not reality itselfModels cannot be perfectly accurateLittle value in using excessively complicated models, particularlyfor hand calculationsTo first order current is proportional to W/LBut, in modern transistors Leff is shorter than LdrawnDoubling the Ldrawn reduces current more than a factor of twoTwo series transistors in a modern process deliver more than halfthe current of a single transistorUse Transmission gates in place of pass transistorsTransistor speed depends on the ratio of current to capacitanceSources of capacitance (voltage dependents)Gate capacitanceDiffusion capacitance

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