“ Advanced 32 Bit Embedded system design” Focus on ARM & Power PC Necessity of 32-bit Microcontroller - By V.Mohana
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Mixed Microcontroller Soup
Embedded Microcontroller <ul><li>Microcontroller </li></ul><ul><ul><li>An application-specific processor </li></ul></ul><u...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
High-end microcontroller applications <ul><li>Consumer Electronics </li></ul><ul><li>Printer. </li></ul><ul><li>Cell phone...
High-end microcontroller applications
BMW 850i
BMW 850i, cont’d.  brake sensor brake sensor brake sensor brake sensor ABS hydraulic pump
HP Design Jet drafting plotter i960KA adrs latch bus if 1 MB ROM 2 MB DRAM proc. support ASIC || if RS- 422 pen ctrl ASIC ...
Apple Newton ARM 610 ROM RAM Runt ASIC LCD speaker serial I/F A/D tablet PCMCIA infrared
Set-top box in system set-top box IR digital TV input back channel
Philips fiber-to-curb box hardware Network interface MPEG demux MPEG audio MPEG video NTSC CD-I graphics PCMCIA DRAM I/O k...
Fiber-to-curb box software default apps custom apps OS-9 kernel I/O manager device drivers boot/monitor software MPEG2 dem...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Von Neumann architecture <ul><li>Memory holds data, instructions. </li></ul><ul><li>Central processing unit (CPU) fetches ...
CPU + memory memory CPU PC address data IR ADD r5,r1,r3 200 200 ADD r5,r1,r3
Harvard architecture CPU PC data memory program memory address data address data
von Neumann vs. Harvard <ul><li>Harvard can’t use self-modifying code. </li></ul><ul><li>Harvard allows two simultaneous m...
Load and Store architecture <ul><li>CISC Approach </li></ul><ul><ul><li>The primary goal of CISC architecture is to comple...
Load and Store architecture <ul><li>RISC Approach </li></ul><ul><ul><li>RISC processors only use simple instructions that ...
RISC Vs CISC approach <ul><li>CISC Approach </li></ul><ul><ul><li>MULT 2:3, 5:2 </li></ul></ul><ul><li>RISC Approach </li>...
RISC Vs CISC Low cycles per second, large code sizes  Small code sizes, high cycles per second  Register to register: &quo...
The Performance Equation   <ul><li>The CISC approach attempts to minimize the number of instructions per program, sacrific...
Pipelining <ul><li>Execute several instructions simultaneously but at different stages. </li></ul><ul><li>Simple three-sta...
Pipeline complications <ul><li>May not always be able to predict the next instruction: </li></ul><ul><ul><li>Conditional b...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Why 32 Bit Microcontroller? <ul><li>Performance </li></ul><ul><li>OS support </li></ul><ul><li>Sophisticated Peripherals s...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Popular 32- bit CPU cores <ul><li>ARM ( A corn  R ISC  M achine ) </li></ul><ul><li>MIPS ( M icroprocessor without  I nter...
Popular 32 bit microcontroller manufacturers <ul><li>Atmel </li></ul><ul><li>Cypress Semiconductor </li></ul><ul><li>Frees...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Selecting a Microcontroller <ul><li>Choose the right one for your  application </li></ul><ul><li>Software support & develo...
Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Comp...
Unique Architecture features. <ul><li>RISC Architecture </li></ul><ul><li>Pipeline </li></ul><ul><li>High speed bus archit...
ARM <ul><li>ARM Holdings, plc. is a fabless company which defines and licenses the ARM architecture </li></ul><ul><ul><li>...
ARM <ul><ul><li>32-bit architecture, typ.  Harvard  - style </li></ul></ul><ul><ul><li>Popular arch. variants include  ARM...
Intel Strong ARM architecture
Strong-ARM Audiovox Thera PDA-2032
MIPS <ul><li>Origins </li></ul><ul><ul><li>Defined by John Hennessey c. 1980 </li></ul></ul><ul><ul><li>Turned into a comp...
MIPS <ul><li>Originally targeted for workstation/supercomputer CPU </li></ul><ul><li>Migrated to embedded applications, no...
NEC VR4120
VR4120  Block diagram
Hitachi SH <ul><li>Hitachi SH is one of many products made by Hitachi </li></ul><ul><li>“Super-H” RISC engine </li></ul><u...
Hitachi SH <ul><li>SH-1 is 20 MHz, highly integrated peripheral set, MAC, cost sensitive apps </li></ul><ul><li>SH-2 is 66...
Super H
Power PC <ul><li>PowerPC  is a RISC architecture created by the 1991  A pple– I BM– M otorola alliance, known as  AIM </li...
MPC5554 Overview
Special Features of ARM (Eg: ARM7TDMI)  <ul><li>Reduced Instruction Set Computer (RISC) </li></ul><ul><ul><li>Simple instr...
ARM state and Thumb state <ul><li>ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit ...
8-bit & 16-bit code size vs Thumb <ul><li>NXP LPC2000 (Thumb Mode) 26796 bytes </li></ul><ul><li>Renesas H8 37921 bytes </...
Special features of PowerPC (e200z6) <ul><li>PowerPC e200  is a family of  32-bit Power Architecture   microprocessor  cor...
Freescale’s e200z6 Core  <ul><li>High-performance 132 MHz 32-bit Book E-compliant core built on Power Architecture technol...
References <ul><li>Computers as Components </li></ul><ul><ul><ul><li>- By Wayne Wolf </li></ul></ul></ul>
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Necessity of 32-Bit Controllers

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Introduction to 32 Bit Microcontrollers and its application

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Necessity of 32-Bit Controllers

  1. 1. “ Advanced 32 Bit Embedded system design” Focus on ARM & Power PC Necessity of 32-bit Microcontroller - By V.Mohana
  2. 2. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  3. 3. Mixed Microcontroller Soup
  4. 4. Embedded Microcontroller <ul><li>Microcontroller </li></ul><ul><ul><li>An application-specific processor </li></ul></ul><ul><ul><li>PIC vs. StrongArm: it all depends on your application </li></ul></ul><ul><li>Typically, microcontrollers... </li></ul><ul><ul><li>Are low cost, lightweight processors </li></ul></ul><ul><ul><li>Require few support components for better system integration </li></ul></ul><ul><ul><li>Come with integrated peripherals </li></ul></ul>
  5. 5. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  6. 6. High-end microcontroller applications <ul><li>Consumer Electronics </li></ul><ul><li>Printer. </li></ul><ul><li>Cell phone. </li></ul><ul><li>Automobile: engine, brakes, dash, Safety etc. </li></ul><ul><li>Television. </li></ul><ul><li>Household appliances. </li></ul><ul><li>Medical Electronics eg :-Telemetric </li></ul>
  7. 7. High-end microcontroller applications
  8. 8. BMW 850i
  9. 9. BMW 850i, cont’d. brake sensor brake sensor brake sensor brake sensor ABS hydraulic pump
  10. 10. HP Design Jet drafting plotter i960KA adrs latch bus if 1 MB ROM 2 MB DRAM proc. support ASIC || if RS- 422 pen ctrl ASIC swath RAM servo proc. (8052) EEPROM DRAM ctrl front panel stepper motor carriage PC board
  11. 11. Apple Newton ARM 610 ROM RAM Runt ASIC LCD speaker serial I/F A/D tablet PCMCIA infrared
  12. 12. Set-top box in system set-top box IR digital TV input back channel
  13. 13. Philips fiber-to-curb box hardware Network interface MPEG demux MPEG audio MPEG video NTSC CD-I graphics PCMCIA DRAM I/O kbd IR card NVRAM DRAM DRAM
  14. 14. Fiber-to-curb box software default apps custom apps OS-9 kernel I/O manager device drivers boot/monitor software MPEG2 demux audio/video interfaces CD-I graphics network interface processor hardware layer OS layer application layer
  15. 15. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  16. 16. Von Neumann architecture <ul><li>Memory holds data, instructions. </li></ul><ul><li>Central processing unit (CPU) fetches instructions from memory. </li></ul><ul><ul><li>Separate CPU and memory distinguishes programmable computer. </li></ul></ul><ul><li>CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc. </li></ul>
  17. 17. CPU + memory memory CPU PC address data IR ADD r5,r1,r3 200 200 ADD r5,r1,r3
  18. 18. Harvard architecture CPU PC data memory program memory address data address data
  19. 19. von Neumann vs. Harvard <ul><li>Harvard can’t use self-modifying code. </li></ul><ul><li>Harvard allows two simultaneous memory fetches. </li></ul><ul><li>Most DSPs use Harvard architecture for streaming data: </li></ul><ul><ul><li>greater memory bandwidth; </li></ul></ul><ul><ul><li>more predictable bandwidth. </li></ul></ul>
  20. 20. Load and Store architecture <ul><li>CISC Approach </li></ul><ul><ul><li>The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible </li></ul></ul><ul><ul><li>This is achieved by building processor hardware that is capable of understanding and executing a series of operations. </li></ul></ul>
  21. 21. Load and Store architecture <ul><li>RISC Approach </li></ul><ul><ul><li>RISC processors only use simple instructions that can be executed within one clock </li></ul></ul><ul><ul><li>Separating the &quot;LOAD&quot; and &quot;STORE&quot; instructions actually reduces the amount of work that the computer must perform </li></ul></ul>
  22. 22. RISC Vs CISC approach <ul><li>CISC Approach </li></ul><ul><ul><li>MULT 2:3, 5:2 </li></ul></ul><ul><li>RISC Approach </li></ul><ul><ul><li>LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A </li></ul></ul>
  23. 23. RISC Vs CISC Low cycles per second, large code sizes Small code sizes, high cycles per second Register to register: &quot;LOAD&quot; and &quot;STORE&quot; are independent instructions Memory-to-memory: &quot;LOAD&quot; and &quot;STORE&quot; incorporated in instructions Single-clock, reduced instruction only Includes multi-clock complex instructions Emphasis on software Emphasis on hardware RISC CISC
  24. 24. The Performance Equation <ul><li>The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction </li></ul><ul><li>RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program. </li></ul>
  25. 25. Pipelining <ul><li>Execute several instructions simultaneously but at different stages. </li></ul><ul><li>Simple three-stage pipe: </li></ul>fetch decode execute memory
  26. 26. Pipeline complications <ul><li>May not always be able to predict the next instruction: </li></ul><ul><ul><li>Conditional branch. </li></ul></ul><ul><li>Causes bubble in the pipeline: </li></ul>fetch decode Execute JNZ fetch decode execute fetch decode execute
  27. 27. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  28. 28. Why 32 Bit Microcontroller? <ul><li>Performance </li></ul><ul><li>OS support </li></ul><ul><li>Sophisticated Peripherals support </li></ul><ul><li>Real time applications </li></ul><ul><li>Pipelined RISC architecture </li></ul>
  29. 29. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  30. 30. Popular 32- bit CPU cores <ul><li>ARM ( A corn R ISC M achine ) </li></ul><ul><li>MIPS ( M icroprocessor without I nterlocked P ipeline S tages ) </li></ul><ul><li>PowerPC ( Power P erformance C omputing ) </li></ul><ul><li>SH ( S uper H ) </li></ul>
  31. 31. Popular 32 bit microcontroller manufacturers <ul><li>Atmel </li></ul><ul><li>Cypress Semiconductor </li></ul><ul><li>Freescale semiconductor </li></ul><ul><li>Infineon </li></ul><ul><li>Intel </li></ul><ul><li>NXP </li></ul><ul><li>Texas Instruments. </li></ul><ul><li>NEC </li></ul><ul><li>Renesas </li></ul>
  32. 32. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  33. 33. Selecting a Microcontroller <ul><li>Choose the right one for your application </li></ul><ul><li>Software support & development environment, FAE support, and hardware availability </li></ul><ul><li>Choose one with good software development support </li></ul><ul><li>Beware of availability </li></ul>
  34. 34. Contents <ul><li>Mixed Microcontroller Soup </li></ul><ul><li>High End Microcontroller applications </li></ul><ul><li>Computer Architecture taxonomy </li></ul><ul><li>Why 32 Bit Microcontroller? </li></ul><ul><li>Popular 32- bit CPU cores </li></ul><ul><li>Selecting a microcontroller </li></ul><ul><li>Unique architecture features. </li></ul>
  35. 35. Unique Architecture features. <ul><li>RISC Architecture </li></ul><ul><li>Pipeline </li></ul><ul><li>High speed bus architecture </li></ul><ul><li>In Circuit Emulators (ICE) </li></ul><ul><li>Various power saving mode </li></ul><ul><li>Various clock domain </li></ul><ul><li>Memory Management Unit (MMU) </li></ul>
  36. 36. ARM <ul><li>ARM Holdings, plc. is a fabless company which defines and licenses the ARM architecture </li></ul><ul><ul><li>joint venture of Apple, Acorn, and VLSI </li></ul></ul><ul><li>ARM is targeted at </li></ul><ul><ul><li>Portable market : digital cellular phones, pagers and personal organizers </li></ul></ul><ul><ul><li>Embedded market: modems, hard disc drives, printers and Automotive applications </li></ul></ul><ul><ul><li>Consumer multimedia market: sound systems, games, internet access TV, set top box </li></ul></ul><ul><li>ARM tries to provide high MIPS/watt, good code density, and minimal area => minimal cost </li></ul>
  37. 37. ARM <ul><ul><li>32-bit architecture, typ. Harvard - style </li></ul></ul><ul><ul><li>Popular arch. variants include ARM7, ARM9, ARM10, Strong-Arm </li></ul></ul><ul><ul><li>Most ARM implementations include 8-16K separate I/D caches </li></ul></ul><ul><ul><li>Representative ARM: Strong-ARM </li></ul></ul><ul><ul><li>Multiply and barrel shift instructions in hardware </li></ul></ul><ul><ul><li>Processor core consumes roughly 100 mW at top speed </li></ul></ul>
  38. 38. Intel Strong ARM architecture
  39. 39. Strong-ARM Audiovox Thera PDA-2032
  40. 40. MIPS <ul><li>Origins </li></ul><ul><ul><li>Defined by John Hennessey c. 1980 </li></ul></ul><ul><ul><li>Turned into a company by John Hennessey, Skip Stritter, and John Moussouris </li></ul></ul><ul><li>Architecture spans several generations, most recent rev of ISA is MIPS IV </li></ul><ul><li>MIPS is currently a fabless company who licenses technology, cores, and IP </li></ul><ul><ul><li>Toshiba, NEC, IDT, LSI Logic, NKK, Philips, and QED (QED is also fabless) </li></ul></ul><ul><li>Range of MIPS varieties </li></ul><ul><ul><li>32 or 64-bit versions </li></ul></ul><ul><ul><li>16 MHz to 300 MHz </li></ul></ul><ul><ul><li>54 mW to 30W </li></ul></ul><ul><ul><li>0.5u to 0.25u processes, 2mm2 to 290 mm2 implementations </li></ul></ul>
  41. 41. MIPS <ul><li>Originally targeted for workstation/supercomputer CPU </li></ul><ul><li>Migrated to embedded applications, now one of the most popular embedded architectures </li></ul><ul><li>PowerPC is taking a similar track </li></ul><ul><li>typical MIPS architecture: NEC VR4120 </li></ul>
  42. 42. NEC VR4120
  43. 43. VR4120 Block diagram
  44. 44. Hitachi SH <ul><li>Hitachi SH is one of many products made by Hitachi </li></ul><ul><li>“Super-H” RISC engine </li></ul><ul><li>Scalable architecture, from SH-1 to SH-4 </li></ul><ul><li>Upward code compatible across entire family </li></ul><ul><li>Applications from motion controllers to high-end game decks and windows CE computers </li></ul><ul><li>Targeted at low-power, cost-sensitive applications but still requiring high performance </li></ul>
  45. 45. Hitachi SH <ul><li>SH-1 is 20 MHz, highly integrated peripheral set, MAC, cost sensitive apps </li></ul><ul><li>SH-2 is 66 MHz, highly integrated peripheral set, DSP version available, cache </li></ul><ul><li>SH-3 is 133 MHz, DSP version available, MMU, cache </li></ul><ul><li>SH-4 is 200 MHz, integrated FPU, 3-D vector unit, MMU, plus other peripherals, cache </li></ul>
  46. 46. Super H
  47. 47. Power PC <ul><li>PowerPC is a RISC architecture created by the 1991 A pple– I BM– M otorola alliance, known as AIM </li></ul><ul><li>Originally intended for personal computers , PowerPC CPUs have since become popular embedded and high-performance processors. </li></ul><ul><li>PowerPC is based on IBM’s POWER Architecture </li></ul><ul><li>The first RISC machine. </li></ul><ul><li>P erformance O ptimization W ith E nhanced R ISC </li></ul>
  48. 48. MPC5554 Overview
  49. 49. Special Features of ARM (Eg: ARM7TDMI) <ul><li>Reduced Instruction Set Computer (RISC) </li></ul><ul><ul><li>Simple instruction set and decode compared to CISC processors </li></ul></ul><ul><ul><li>Allows for high instruction throughput and real-time interrupt response </li></ul></ul><ul><li>3-stage pipeline </li></ul><ul><ul><li>Fetch, Decode and Execute </li></ul></ul><ul><ul><li>All parts of the processing and memory systems can operate continuously </li></ul></ul><ul><li>Von Neumann architecture </li></ul><ul><ul><li>Single path for Instructions and Data </li></ul></ul><ul><ul><li>Data Bypass buffer of MAM reduces bottlenecks </li></ul></ul>
  50. 50. ARM state and Thumb state <ul><li>ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit data and registers. </li></ul><ul><li>Set of instructions re-coded into 16 bits </li></ul><ul><ul><li>Improved code density by ~ 30% </li></ul></ul><ul><ul><li>Saving program memory space </li></ul></ul><ul><li>In Thumb state only the program code is 16-bit wide </li></ul><ul><ul><li>After fetching the 16-bit instructions from memory, they are de-compressed to 32 bit instructions before they are decoded and executed </li></ul></ul><ul><ul><li>All operations are still 32-bit operations </li></ul></ul>
  51. 51. 8-bit & 16-bit code size vs Thumb <ul><li>NXP LPC2000 (Thumb Mode) 26796 bytes </li></ul><ul><li>Renesas H8 37921 bytes </li></ul><ul><li>Renesas M16C 26743 bytes </li></ul><ul><li>TI MSP430 26424 bytes </li></ul><ul><li>Atmel AVR 26055 bytes </li></ul><ul><li>Freescale HCS12 23916 bytes </li></ul>
  52. 52. Special features of PowerPC (e200z6) <ul><li>PowerPC e200 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale </li></ul><ul><li>Targeted for Automotive and Industrial Control system </li></ul><ul><li>Especially designed for engine management. </li></ul><ul><ul><li>Multipoint fuel injection control </li></ul></ul><ul><ul><li>Direct diesel injection (DDI) </li></ul></ul><ul><ul><li>Gasoline direct injection (GDI) </li></ul></ul><ul><ul><li>Avionics </li></ul></ul><ul><ul><li>Robotics </li></ul></ul><ul><ul><li>Turbine control </li></ul></ul><ul><ul><li>Utilities/Power management </li></ul></ul><ul><ul><li>Alternative energies </li></ul></ul><ul><ul><li>Autonomous vehicles </li></ul></ul><ul><ul><li>Any model-based design using RAppID and Matlab/Simulink  </li></ul></ul>
  53. 53. Freescale’s e200z6 Core <ul><li>High-performance 132 MHz 32-bit Book E-compliant core built on Power Architecture technology </li></ul><ul><li>SPE (signal processing extension): DSP, SIMD and floating point capabilities </li></ul><ul><li>40-channel dual enhanced queued analog-to-digital converter (eQADC—up to 12-bit resolution and up to 1.25 uS </li></ul><ul><li>Three controller area network (CAN) modules with 64 buffers each </li></ul>
  54. 54. References <ul><li>Computers as Components </li></ul><ul><ul><ul><li>- By Wayne Wolf </li></ul></ul></ul>
  55. 55. Questions

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