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Necessity of 32-Bit Controllers

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Introduction to 32 Bit Microcontrollers and its application

Introduction to 32 Bit Microcontrollers and its application


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  • 1. “ Advanced 32 Bit Embedded system design” Focus on ARM & Power PC Necessity of 32-bit Microcontroller - By V.Mohana
  • 2. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 3. Mixed Microcontroller Soup
  • 4. Embedded Microcontroller
    • Microcontroller
      • An application-specific processor
      • PIC vs. StrongArm: it all depends on your application
    • Typically, microcontrollers...
      • Are low cost, lightweight processors
      • Require few support components for better system integration
      • Come with integrated peripherals
  • 5. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 6. High-end microcontroller applications
    • Consumer Electronics
    • Printer.
    • Cell phone.
    • Automobile: engine, brakes, dash, Safety etc.
    • Television.
    • Household appliances.
    • Medical Electronics eg :-Telemetric
  • 7. High-end microcontroller applications
  • 8. BMW 850i
  • 9. BMW 850i, cont’d. brake sensor brake sensor brake sensor brake sensor ABS hydraulic pump
  • 10. HP Design Jet drafting plotter i960KA adrs latch bus if 1 MB ROM 2 MB DRAM proc. support ASIC || if RS- 422 pen ctrl ASIC swath RAM servo proc. (8052) EEPROM DRAM ctrl front panel stepper motor carriage PC board
  • 11. Apple Newton ARM 610 ROM RAM Runt ASIC LCD speaker serial I/F A/D tablet PCMCIA infrared
  • 12. Set-top box in system set-top box IR digital TV input back channel
  • 13. Philips fiber-to-curb box hardware Network interface MPEG demux MPEG audio MPEG video NTSC CD-I graphics PCMCIA DRAM I/O kbd IR card NVRAM DRAM DRAM
  • 14. Fiber-to-curb box software default apps custom apps OS-9 kernel I/O manager device drivers boot/monitor software MPEG2 demux audio/video interfaces CD-I graphics network interface processor hardware layer OS layer application layer
  • 15. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 16. Von Neumann architecture
    • Memory holds data, instructions.
    • Central processing unit (CPU) fetches instructions from memory.
      • Separate CPU and memory distinguishes programmable computer.
    • CPU registers help out: program counter (PC), instruction register (IR), general-purpose registers, etc.
  • 17. CPU + memory memory CPU PC address data IR ADD r5,r1,r3 200 200 ADD r5,r1,r3
  • 18. Harvard architecture CPU PC data memory program memory address data address data
  • 19. von Neumann vs. Harvard
    • Harvard can’t use self-modifying code.
    • Harvard allows two simultaneous memory fetches.
    • Most DSPs use Harvard architecture for streaming data:
      • greater memory bandwidth;
      • more predictable bandwidth.
  • 20. Load and Store architecture
    • CISC Approach
      • The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible
      • This is achieved by building processor hardware that is capable of understanding and executing a series of operations.
  • 21. Load and Store architecture
    • RISC Approach
      • RISC processors only use simple instructions that can be executed within one clock
      • Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform
  • 22. RISC Vs CISC approach
    • CISC Approach
      • MULT 2:3, 5:2
    • RISC Approach
      • LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A
  • 23. RISC Vs CISC Low cycles per second, large code sizes Small code sizes, high cycles per second Register to register: "LOAD" and "STORE" are independent instructions Memory-to-memory: "LOAD" and "STORE" incorporated in instructions Single-clock, reduced instruction only Includes multi-clock complex instructions Emphasis on software Emphasis on hardware RISC CISC
  • 24. The Performance Equation
    • The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction
    • RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program.
  • 25. Pipelining
    • Execute several instructions simultaneously but at different stages.
    • Simple three-stage pipe:
    fetch decode execute memory
  • 26. Pipeline complications
    • May not always be able to predict the next instruction:
      • Conditional branch.
    • Causes bubble in the pipeline:
    fetch decode Execute JNZ fetch decode execute fetch decode execute
  • 27. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 28. Why 32 Bit Microcontroller?
    • Performance
    • OS support
    • Sophisticated Peripherals support
    • Real time applications
    • Pipelined RISC architecture
  • 29. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 30. Popular 32- bit CPU cores
    • ARM ( A corn R ISC M achine )
    • MIPS ( M icroprocessor without I nterlocked P ipeline S tages )
    • PowerPC ( Power P erformance C omputing )
    • SH ( S uper H )
  • 31. Popular 32 bit microcontroller manufacturers
    • Atmel
    • Cypress Semiconductor
    • Freescale semiconductor
    • Infineon
    • Intel
    • NXP
    • Texas Instruments.
    • NEC
    • Renesas
  • 32. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 33. Selecting a Microcontroller
    • Choose the right one for your application
    • Software support & development environment, FAE support, and hardware availability
    • Choose one with good software development support
    • Beware of availability
  • 34. Contents
    • Mixed Microcontroller Soup
    • High End Microcontroller applications
    • Computer Architecture taxonomy
    • Why 32 Bit Microcontroller?
    • Popular 32- bit CPU cores
    • Selecting a microcontroller
    • Unique architecture features.
  • 35. Unique Architecture features.
    • RISC Architecture
    • Pipeline
    • High speed bus architecture
    • In Circuit Emulators (ICE)
    • Various power saving mode
    • Various clock domain
    • Memory Management Unit (MMU)
  • 36. ARM
    • ARM Holdings, plc. is a fabless company which defines and licenses the ARM architecture
      • joint venture of Apple, Acorn, and VLSI
    • ARM is targeted at
      • Portable market : digital cellular phones, pagers and personal organizers
      • Embedded market: modems, hard disc drives, printers and Automotive applications
      • Consumer multimedia market: sound systems, games, internet access TV, set top box
    • ARM tries to provide high MIPS/watt, good code density, and minimal area => minimal cost
  • 37. ARM
      • 32-bit architecture, typ. Harvard - style
      • Popular arch. variants include ARM7, ARM9, ARM10, Strong-Arm
      • Most ARM implementations include 8-16K separate I/D caches
      • Representative ARM: Strong-ARM
      • Multiply and barrel shift instructions in hardware
      • Processor core consumes roughly 100 mW at top speed
  • 38. Intel Strong ARM architecture
  • 39. Strong-ARM Audiovox Thera PDA-2032
  • 40. MIPS
    • Origins
      • Defined by John Hennessey c. 1980
      • Turned into a company by John Hennessey, Skip Stritter, and John Moussouris
    • Architecture spans several generations, most recent rev of ISA is MIPS IV
    • MIPS is currently a fabless company who licenses technology, cores, and IP
      • Toshiba, NEC, IDT, LSI Logic, NKK, Philips, and QED (QED is also fabless)
    • Range of MIPS varieties
      • 32 or 64-bit versions
      • 16 MHz to 300 MHz
      • 54 mW to 30W
      • 0.5u to 0.25u processes, 2mm2 to 290 mm2 implementations
  • 41. MIPS
    • Originally targeted for workstation/supercomputer CPU
    • Migrated to embedded applications, now one of the most popular embedded architectures
    • PowerPC is taking a similar track
    • typical MIPS architecture: NEC VR4120
  • 42. NEC VR4120
  • 43. VR4120 Block diagram
  • 44. Hitachi SH
    • Hitachi SH is one of many products made by Hitachi
    • “Super-H” RISC engine
    • Scalable architecture, from SH-1 to SH-4
    • Upward code compatible across entire family
    • Applications from motion controllers to high-end game decks and windows CE computers
    • Targeted at low-power, cost-sensitive applications but still requiring high performance
  • 45. Hitachi SH
    • SH-1 is 20 MHz, highly integrated peripheral set, MAC, cost sensitive apps
    • SH-2 is 66 MHz, highly integrated peripheral set, DSP version available, cache
    • SH-3 is 133 MHz, DSP version available, MMU, cache
    • SH-4 is 200 MHz, integrated FPU, 3-D vector unit, MMU, plus other peripherals, cache
  • 46. Super H
  • 47. Power PC
    • PowerPC is a RISC architecture created by the 1991 A pple– I BM– M otorola alliance, known as AIM
    • Originally intended for personal computers , PowerPC CPUs have since become popular embedded and high-performance processors.
    • PowerPC is based on IBM’s POWER Architecture
    • The first RISC machine.
    • P erformance O ptimization W ith E nhanced R ISC
  • 48. MPC5554 Overview
  • 49. Special Features of ARM (Eg: ARM7TDMI)
    • Reduced Instruction Set Computer (RISC)
      • Simple instruction set and decode compared to CISC processors
      • Allows for high instruction throughput and real-time interrupt response
    • 3-stage pipeline
      • Fetch, Decode and Execute
      • All parts of the processing and memory systems can operate continuously
    • Von Neumann architecture
      • Single path for Instructions and Data
      • Data Bypass buffer of MAM reduces bottlenecks
  • 50. ARM state and Thumb state
    • ARM uses a 32-bit architecture with a subset of 16-bit instructions, still using 32-bit data and registers.
    • Set of instructions re-coded into 16 bits
      • Improved code density by ~ 30%
      • Saving program memory space
    • In Thumb state only the program code is 16-bit wide
      • After fetching the 16-bit instructions from memory, they are de-compressed to 32 bit instructions before they are decoded and executed
      • All operations are still 32-bit operations
  • 51. 8-bit & 16-bit code size vs Thumb
    • NXP LPC2000 (Thumb Mode) 26796 bytes
    • Renesas H8 37921 bytes
    • Renesas M16C 26743 bytes
    • TI MSP430 26424 bytes
    • Atmel AVR 26055 bytes
    • Freescale HCS12 23916 bytes
  • 52. Special features of PowerPC (e200z6)
    • PowerPC e200 is a family of 32-bit Power Architecture microprocessor cores developed by Freescale
    • Targeted for Automotive and Industrial Control system
    • Especially designed for engine management.
      • Multipoint fuel injection control
      • Direct diesel injection (DDI)
      • Gasoline direct injection (GDI)
      • Avionics
      • Robotics
      • Turbine control
      • Utilities/Power management
      • Alternative energies
      • Autonomous vehicles
      • Any model-based design using RAppID and Matlab/Simulink 
  • 53. Freescale’s e200z6 Core
    • High-performance 132 MHz 32-bit Book E-compliant core built on Power Architecture technology
    • SPE (signal processing extension): DSP, SIMD and floating point capabilities
    • 40-channel dual enhanced queued analog-to-digital converter (eQADC—up to 12-bit resolution and up to 1.25 uS
    • Three controller area network (CAN) modules with 64 buffers each
  • 54. References
    • Computers as Components
        • - By Wayne Wolf
  • 55. Questions

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