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# Intro

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Is an introduction for digital design crash course using Verilog,
Those slides are just quick refreshment for most important parts in logic circuits, Brief history about the field and steps we follow to get a chip.

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### Intro

1. 1. Digital Design Crash Course Mohamed Rayan
2. 2. Overview  General discussion.  Digital design brief history.  Electronic Design Automation.  Digital design flow.
3. 3. General Discussion
4. 4.  Difference between Sequential and Combinational Circuits?  Memory elements are devices capable of storing binary information.  The binary information stored in these elements at any given time defines the state of the sequential circuit at that time.
5. 5.  Combinational Circuits? Q = fn ( A,b,c)  E.g: Compartors, Muxes, Decoders, Adders, subtractors, multipliers,…
6. 6.  Signed binary numbers representation  Signed magnitude(1-bit for sign only).  1’s Complement(Inversion).  2’s Complement(Inversion + increment 1). +5 (0 101) +5 (0 101) +5 (0 101) -5(1 101) -5(1 010). -5(1 011)
7. 7.  Sequential logic circuits (with storage elements)  Synchronous logic circuits : 1- Its behavior can be defined from the knowledge of its signals at discrete instants of time. 2- Storage elements used here will have a change at the same time e.g registers change with clock event  Asynchronous logic circuits (Combinational circuits with feed back): 1- Its behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change. 2- storage elements commonly used in asynchronous sequential circuits are time-delay devices e.g gate propagation delay.
8. 8.  Synchronous Sequential logic circuits
9. 9. Latches and Flip-Flops  Latches (Level triggered):  SR latch (May go to Meta stable state?!!)
10. 10. Latches and Flip-Flops  Latches(Level triggered):  D-latch is the most commonly used to eliminate the undesirable condition (Occurrence of Metstability) of the indeterminate state in the SR latch is to ensure that inputs S and R are never equal to 0 at the same time.
11. 11. Latches and Flip-Flops  Flip-Flops(Edge triggered):  Using Flip-flops as a storage element makes the system more reliable and maintain system robustness. Output changes if and only if with the edge of Clock .
12. 12. Latches and Flip-Flops  Flip-Flops(Edge triggered):
13. 13.  Why we use Flip-Flops and not to use latches? 1- Latches are level triggered but Flip-Flops are edge triggered.  Latches are just timing delays in Asynchronous sequential circuit and hence they are used in a circuit to adjusts delays between different paths for the required circuit functionality taking into consideration propagation delays of every single gate that form combinational circuit , So Designing a circuit using latches is so difficult.  Flip-Flops are edge triggered so all outputs are changing at the same time with the occurrence of certain event which is the clock edge taking into consideration the frequency of this clock and this is function in longest path in the circuit , So Designing a circuit using flip-flops will be more easier.
14. 14.  Why we use Flip-Flops and not to use latches? 2- Using latches lead to un-relaible circuits .  A sequential circuit has a feedback path from the outputs of storage element to the input of the combinational circuit. Consequently, the inputs of the storage element are derived in part from the outputs of the same and other storage element. When latches are used for the storage elements, a serious difficulty arises. The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level. The new state of a latch appears at the output while the pulse is still active. This output is connected to the inputs of the latches through the combinational circuit. If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur. The result is an unpredictable situation, since the state of the latches may keep changing for as long as the clock pulse stays at the active level. Because of this unreliable operation, the output of a latch cannot be applied directly or through combinational logic to the input of the same or another latch when all the latches are triggered by a common clock source. 3- Simulation tools can’t track outputs of Asynchronous circuits i.e Latches
15. 15. Latches and Flip-Flops  Comparison between Latches and Flip-flops Parameter Latches Flip-Flops Area Less More Glitches prone More Less Output Response Doesn’t wait to an an event i.e when input changes output will change directly Output change according to an input when an an event occurs Simulation Tool Not Supported Supported Constraints Don’t have clock constraint but delays of combinational circuit must be fixed to ensure reliable operation Having clock constraint  From the previous table we conclude that Flip-Flops is more robust than latches so it is commonly used .
16. 16. Registers and Counters  Register  A register is a group of flip‐flops, each one of which shares a common clock.  Register with Parallel load and Shift register?
17. 17. Registers and Counters  Counter  is essentially a register that goes through a predetermined sequence of binary states. The gates is combinational logic used with register to do this sequence. are a special type of register .
18. 18. Synchronous and Asynchronous Reset  Reset  Is to force the system to a known state.  Is required to initialize a hardware design.  Simply changes the state of device/design to a user/designer defined state.  There are two types of reset : (Synchronous and Asynchronous reset) We can’t expect any Sequential Circuit without reset.
19. 19. Synchronous and Asynchronous Reset Synchronous Reset Reset is sampled with respect to clock Asynchronous Reset Reset is sampled with no respect to clock Synchronous reset requires more gates to Asynchronous reset requires less gates to implement (see the example below) implement (see the example below) Synchronous reset requires clock to be active always Asynchronous reset does not require clock to be always active Synchronous reset does not have metastability problems. Asynchronous reset suffer from metastability problems. Synchronous reset is slow Asynchronous reset is fast
20. 20. Brief History
21. 21. Brief History  Digital circuit design has evolved rapidly over the last 25 years .  Human always Seeks for Comfort and luxury and try to develop in everything to reach for these  .  This leads to exponential progress in Specs and Requirements of digital systems lead increasing in area, spead and complexity of designs. E.g: Digital cameras, high-definition TV, wireless phone, smart home, smart cars…
22. 22. Brief History
23. 23. Brief History  Digital ICs are often categorized according to the complexity of their circuits, as measured by the number of logic gates in a single package. SSI (small scale of integration) The number of gates is usually fewer than 10 and is limited by the number of pins available in the IC.
24. 24. Brief History MSI (medium scale of integration) have a complexity of approximately 10 to 1,000 gates in a single package.
25. 25. Brief History LSI (Large scale of Integration) devices contain thousands of gates in a single package. They include digital systems such as processors and memory chips.
26. 26. Brief History VLSI (Very Large scale of Integration) devices now contain millions of gates within a single package. Examples are large memory arrays and complex microcomputer chips.
27. 27. Electronic Design Automation (EDA)
28. 28. Electronic Design Automation As we said that we may have single chip having hundred thousands of gates, so design processes started getting very complicated, Automated Process is a must. Traditional schematic-based design has no longer enough towards these design complexities. EDA covers all phases of the design of integrated Circuits using computer‐aided design (CAD) tools, which consist of software programs that support computer‐based representations of circuits and aid in the development of digital hardware by automating the design process.
29. 29. Electronic Design Automation • Importance of HDLs (Hardware Description/Modeling)  Designs can be described at a very abstract level by use of HDLs .  To any abstracted level we can design? Ans: (according too the ability of the tool).  Difference between Writing code for modeling H/W and S/W e.g C++ ?  Designers can write their RTL description without choosing a specific fabrication technology.  Logic synthesis tools can automatically convert the design to any fabrication technology.  If a new technology emerges, designers do not need to redesign their circuit.
30. 30. Electronic Design Automation • Logic Synthesis (Hardware Compiler but not flexible as C/C++ Compiler )
31. 31. Digital Design Flow
32. 32. Digital Design Flow Design Specs Behavioral Description RTL Description (HDL) Functional Verification and Testing e.g algorithm needs to be implemented Description for Functionality of the design and the interface of it with the whole system (inputs and outputs) Design The RTL and Write the verilog code that implement this design according Specs and Interface Compile Verilog files and make testbench to verify your design and start verification Usually 50 – 60% of cycle time Logic Synthesis (S/W) Place and Route Physical Layout Fabrication Place the gates in the chip and make possible and suitable routing between them
33. 33. thanks