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10.digital design - reset circuits
 

10.digital design - reset circuits

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    10.digital design - reset circuits 10.digital design - reset circuits Presentation Transcript

    • Digital design Reset circuits
    • Table of contents     Reset. Asynchronous reset. Synchronous reset. Asynchronous assertion synchronous deassertion.  Mixing flop types.  Internally generated resets.  Multiple clock domains.
    • Reset  Objective: to force our design into a known state.  Example: many data path systems Many data path system - so we must reset each path to begin from a certain state .
    • Reset(Cont.)  Example: We may use reset on power up to state machines which take advantage of ‘’don’t care“ logic reduction. 101 111 101 000 000 100 110 110 001 What may happen if we haven't reset? Input voltage Reset 011 010 100 001 011 010 But , how to design “reset on power up”? 111
    • Asynchronous reset  A fully asynchronous reset is one that both asserts and de-asserts a flip-flop asynchronously.  Asynchronous reset refers to the situation where the reset net is tied to the asynchronous reset pin of the flip-flop. module resetff( output reg oData, input iClk, iRst, input iData ); always @(posedge iClk ,negedge iRst) if(!iRst) oData <= 0; else oData <= iData; endmodule Clock source Reset controller iData Q oData D
    • Asynchronous reset(Cont.)  Can this cause meta-stability? Clock source Reset controller Clock Reset Recovery time Timing conditions meting Reset recovery time meting iData Q Q oData D
    • Asynchronous reset(Cont.) Clock Reset Recovery time Timing conditions violation Q Recovery time violation
    • Synchronous reset  Reset presented to all functional flip-flops is fully synchronous to the clock.  Reset will always meet the reset recovery time conditions assuming the proper buffering is provided for the high fan-out of the synchronized reset signal.  What about effect of synchronous reset on area?  So what will we do if we have asynchronous reset? Reset controller Clock source asynchronous input Q D Q Reset synchronizer module resetsync( output reg oRstSync, input iClk, iRst ); reg R1; always @(posedge iClk) begin R1 <= iRst; oRstSync <= R1; end endmodule D Q Clk synchronous system synchronized output
    • Synchronous reset(Cont.)  The interesting thing about this reset topology is the duration of reset.  Example : a single reset is synchronized to a fast clock domain and a relatively slow clock domain. Reset Fast Clock Synchronized reset for fast clock Slow Clock Synchronized reset for slow clock
    • Synchronous reset(Cont.)  Example(cont.): Reset controller asynchronous Q input D D Q D Q synchronized input Clk Fast Clock synchronous system Q asynchronous Q input Slow/gated Clock D D Q D Q synchronized input Clk synchronous system But at the end , It’s connected to asynchronous pin!!
    • Asynchronous assertion synchronous deassertion  Captures the best of both techniques is a method that asserts all resets asynchronously but deasserts them synchronously. ‘1’ D Reset controller Clock source R1 D module resetsync( output reg oRstSync, input iClk, iRst ); reg R1; always @(posedge iClk ,negedge iRst) If(!iRst) begin R1 <= 0; oRstSync <= 0; end oRstSync else begin R1 <= 1; oRstSync <= R1; end endmodule
    • Mixing flop types  It’s not advisable to mix both resettable and non resettable flip-flops in same “always” block (“process” statement), but Why?!! iDat oDat D D Reset controller Expected output Clock source iDat D D oDat Reset controller Clock source Real output module resetckt ( output reg oDat, Input iReset, iClk, input iDat ); reg datareg; always @(posedge iClk) if(!iReset) datareg <= 0; else begin datareg <= iDat; oDat <= datareg; end endmodule
    • Internally generated resets  From your point of view, what the dangerous effect is of Internally generated resets? how we can solve these problems?
    • Multiple clock domains  For each clock separate synchronizer, reset tree and reset buffering. Reset controller asynchronous Q input D D Q D Q synchronized input Clk Fast Clock synchronous system Q asynchronous Q input Slow/gated Clock D D Q D Q synchronized input Clk synchronous system
    • thanks digital design