Microcontroller 8051

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  • Intel’s x86: 8086,8088,80386,80486, Pentium
    Motorola’s 680x0: 68000, 68010, 68020,68030,6040
  • versatility 多用途的: any number of applications for PC
  • processor 整合到整個系統中, 你只看到此系統的外觀, 應用, 感覺不到有 processor 在其中.
    Embedded system 通常只有一項應用, 而 PC 有許多 applications (game, accounting, fax, mail...)
    A printer is an example of embedded system since the processor inside it performs one task only.
  • Program is to read data from P0 and then send data to P1
  • Microcontroller 8051

    1. 1. Contents: Introduction Block Diagram and Pin Description of the 8051 Registers Memory mapping in 8051 Stack in the 8051 I/O Port Programming Timer Interrupt
    2. 2. Why do we need to learn Microprocessors/controllers?  The microprocessor is the core of computer systems.  Nowadays many communication, digital entertainment, portable devices, are controlled by them.  A designer should know what types of components he needs, ways to reduce production costs and product reliable .
    3. 3. Different aspects of a microprocessor/controller  Hardware :Interface to the real world  Software :order how to deal with inputs
    4. 4. The necessary tools for a microprocessor/controller         CPU: Central Processing Unit I/O: Input /Output Bus: Address bus & Data bus Memory: RAM & ROM Timer Interrupt Serial Port Parallel Port
    5. 5. Microprocessors: General-purpose microprocessor  CPU for Computers  No RAM, ROM, I/O on CPU chip itself  Example : Intel’s x86, Motorola’s 680x0 CPU GeneralPurpose Microprocessor Many chips on mother’s board Data Bus RAM ROM I/O Port Address Bus General-Purpose Microprocessor System Timer Serial COM Port
    6. 6. Microcontroller :  A smaller computer  On-chip RAM, ROM, I/O ports...  Example : Motorola’s 6811, Intel’s 8051, Zilog’s Z8 and PIC 16X CPU I/O Port RAM ROM Serial Timer COM Port A single chip Microcontroller
    7. 7. Microprocessor vs. Microcontroller Microprocessor  CPU is stand-alone, RAM, ROM, I/O, timer are separate  designer can decide on the amount of ROM, RAM and I/O ports.  expansive  versatility  general-purpose Microcontroller • CPU, RAM, ROM, I/O and timer are all on a single chip • fix amount of on-chip ROM, RAM, I/O ports • for applications in which cost, power and space are critical • single-purpose
    8. 8. Embedded System  Embedded system means the processor is embedded into that application.  An embedded product uses a microprocessor or microcontroller to do one task only.  In an embedded system, there is only one application software that is typically burned into ROM.  Example : printer, keyboard, video game player
    9. 9. Block Diagram External interrupts Interrupt Control On-chip ROM for program code Timer/Counter On-chip RAM Timer 1 Timer 0 CPU OSC Bus Control 4 I/O Ports P0 P1 P2 P3 Address/Data Serial Port TxD RxD Counter Inputs
    10. 10. Pin Description of the 8051 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8051 (8031) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0 P0.1(AD1) ) P0.2(AD2 P0.3(AD3) ) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14 P ) 2.5(A13 P2.4(A12 ) P ) 2.3(A11 P2.2(A10) ) P2.1(A9) P2.0(A8) 
    11. 11. Pins of 8051 ( 1/4 )  Vcc ( pin 40 ): – Vcc provides supply voltage to the chip. – The voltage source is +5V.  GND ( pin 20 ): ground  XTAL1 and XTAL2 ( pins 19,18 )
    12. 12. Figure (a). XTAL Connection to 8051  Using a quartz crystal oscillator  We can observe the frequency on the XTAL2 pin. C2 XTAL2 30pF C1 XTAL1 30pF GND 
    13. 13. Pins of 8051 ( 2/4 )  RST ( pin 9 ): reset – It is an input pin and is active high ( normally low ) .  The high pulse must be high at least 2 machine cycles. – It is a power-on reset.  Upon applying a high pulse to RST, the microcontroller will reset and all values in registers will be lost.  Reset values of some 8051 registers 
    14. 14. Figure (b). Power-On RESET Circuit Vcc + 10 uF 31 30 pF 8.2 K 30 pF 11.0592 MHz 19 18 EA/VPP X1 X2 9 RST 
    15. 15. Pins of 8051 ( 3/4 )  /EA ( pin 31 ): external access – There is no on-chip ROM in 8031 and 8032 . – The /EA pin is connected to GND to indicate the code is stored externally. – /PSEN & ALE are used for external ROM. – For 8051, /EA pin is connected to Vcc. – “/” means active low.  /PSEN ( pin 29 ): program store enable – This is an output pin and is connected to the OE pin of the ROM.
    16. 16. Pins of 8051 ( 4/4 )  ALE ( pin 30 ): address latch enable – It is an output pin and is active high. – 8051 port 0 provides both address and data. – The ALE pin is used for de-multiplexing the address and data by connecting to the G pin of the 74LS373 latch.  I/O port pins – The four ports P0, P1, P2, and P3. – Each port uses 8 pins. – All I/O pins are bi-directional.
    17. 17. Pins of I/O Port  The 8051 has four I/O ports – Port 0 ( pins 32-39 ): P0 ( P0.0 ~ P0.7 ) – Port 1 ( pins 1-8 ) : P1 ( P1.0 ~ P1.7 ) – Port 2 ( pins 21-28 ): P2 ( P2.0 ~ P2.7 ) – Port 3 ( pins 10-17 ): P3 ( P3.0 ~ P3.7 ) – Each port has 8 pins.  Named P0.X ( X=0,1,...,7 ) , P1.X, P2.X, P3.X  Ex : P0.0 is the bit 0 ( LSB ) of P0  Ex : P0.7 is the bit 7 ( MSB ) of P0  These 8 bits form a byte.  Each port can be used as input or output (bi-direction). 
    18. 18. Hardware Structure of I/O Pin  Each pin of I/O ports – Internal CPU bus : communicate with CPU – A D latch store the value of this pin  D latch is controlled by “Write to latch” – Write to latch = 1 : write data into the D latch – 2 Tri-state buffer :  TB1: controlled by “Read pin” – Read pin = 1 : really read the data present at the pin  TB2: controlled by “Read latch” – Read latch = 1 : read value from internal latch – A transistor M1 gate  Gate=0: open  Gate=1: close
    19. 19. D Latch:
    20. 20. A Pin of Port 1 Read latch TB2 Vcc Load(L1) Internal CPU bus D Write to latch Clk P1.X pin Q P1.X Q M1 TB1 P0.x Read pin 8051 IC
    21. 21. Writing “1” to Output Pin P1.X Read latch Vcc TB2 Load(L1) 2. output pin is Vcc 1. write a 1 to the pin Internal CPU bus D Write to latch Clk 1 Q P1.X pin P1.X Q 0 M1 TB1 Read pin 8051 IC output 1
    22. 22. Writing “0” to Output Pin P1.X Read latch Vcc TB2 Load(L1) 2. output pin is ground 1. write a 0 to the pin Internal CPU bus D Write to latch Clk 0 Q P1.X pin P1.X Q 1 M1 TB1 Read pin 8051 IC output 0
    23. 23. Reading “High” at Input Pin Read latch 1. TB2 write a 1 to the pin MOV P1,#0FFH Internal CPU bus 2. MOV A,P1 Vcc external pin=High Load(L1) D 1 Q 1 P1.X Write to latch Clk 0 Q M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC P1.X pin
    24. 24. Reading “Low” at Input Pin Read latch 1. Vcc 2. MOV A,P1 TB2 write a 1 to the pin Load(L1) external pin=Low MOV P1,#0FFH Internal CPU bus D 1 Q 0 P1.X Write to latch Clk Q 0 M1 TB1 Read pin 3. Read pin=1 Read latch=0 Write to latch=1 8051 IC P1.X pin
    25. 25. Other Pins  P1, P2, and P3 have internal pull-up resisters. – P1, P2, and P3 are not open drain.  P0 has no internal pull-up resistors and does not connects to Vcc inside the 8051. – P0 is open drain. – Compare the figures of P1.X and P0.X.   However, for a programmer, it is the same to program P0, P1, P2 and P3.  All the ports upon RESET are configured as output.
    26. 26. A Pin of Port 0 Read latch TB2 Internal CPU bus D Write to latch Clk P0.X pin Q P1.X Q M1 TB1 P1.x Read pin 8051 IC
    27. 27. Port 0 with Pull-Up Resistors Vcc Port 0 P0.0 DS5000 P0.1 P0.2 8751 P0.3 P0.4 8951 P0.5 P0.6 P0.7 10 K
    28. 28. Port 3 Alternate Functions P3 Bit Function Pin P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 RxD TxD INT0 INT1 T0 T1 WR RD 10 11 12 13 14 15 16 17 
    29. 29. RESET Value of Some 8051 Registers: Register PC ACC B PSW SP DPTR RAM are all zero. Reset Value 0000 0000 0000 0000 0007 0000 
    30. 30. Registers A B R0 DPTR DPH DPL R1 R2 PC PC R3 R4 R5 R6 R7 Some 8-bitt Registers of the 8051 Some 8051 16-bit Register
    31. 31. Memory mapping in 8051  ROM memory map in 8051 family 4k 0000H 8k 32k 0000H 0000H 0FFFH DS5000-32 8751 AT89C51 1FFFH from Atmel Corporation 8752 AT89C52 7FFFH from Dallas Semiconductor
    32. 32.  RAM memory space allocation in the 8051 7FH Scratch pad RAM 30H 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0
    33. 33. Stack in the 8051  The register used to access the stack is called SP (stack pointer) register. 7FH Scratch pad RAM 30H  The stack pointer in the 8051 is only 8 bits wide, which means that it can take value 00 to FFH. When 8051 powered up, the SP register contains value 07. 2FH Bit-Addressable RAM 20H 1FH 18H 17H 10H 0FH 08H 07H 00H Register Bank 3 Register Bank 2 Stack) Register Bank 1) Register Bank 0
    34. 34. Timer :
    35. 35. TMOD Register:  Gate : When set, timer only runs while INT(0,1) is high.  C/T : Counter/Timer select bit.  M1 : Mode bit 1.  M0 : Mode bit 0.
    36. 36. TCON Register:         TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Timer 0 overflag. TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag.
    37. 37. Interrupt :
    38. 38. Interrupt Enable Register :  EA : Global enable/disable.  --- : Undefined.       ET2 :Enable Timer 2 interrupt. ES :Enable Serial port interrupt. ET1 :Enable Timer 1 interrupt. EX1 :Enable External 1 interrupt. ET0 : Enable Timer 0 interrupt. EX0 : Enable External 0 interrupt.

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