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  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • Transcript

    • 1. Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.
    • 2. VLSI Lab VLSI LABORATORY FRONT END DESIGN (CAD) BACK END DESIGN (CAD) TECHNOLOGY (TCAD)
    • 3.
      • Proper hardware
      • Proper software
      • Foundry or link up with some fab lab
      • Test facility
      • Purpose
    • 4. DESIGN STEPS
      • SCHEMATIC
      • LAYOUT DESIGN
      • DRC
      • LAYOUT Vs SCHEMATIC
      • PARASITIC EXTRACTION
      • POST LAYOUT SIMULTION
    • 5. List of Experiments
      • To generate layout for CMOS Inverter circuit and simulate it for verification.
      • To prepare layout for given logic function and verify it with simulations.
      • Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool.
      • Implementation of basic logic gates and its testing.
      • Implementation of adder circuits and its testing.
      • Implementation of J-K and D Flip Flops and its testing.
      • Implementation 4 to 1 multiplexer and its testing.
      • Implementation of 3 to 8 decoder and its testing.
      • Implementation of sequential adder and its testing.
      • Implementation of BCD counter and its testing.
      • Simulation of CMOS Inverter using SPICE for transfer characteristic.
      • Simulation and verification of two input CMOS NOR gate using SPICE.
      • Introduction to Block Diagram Mathod
      • Design of digital Logic using block diagram.
    • 6. Project
      • Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students.
    • 7. Design Abstraction Levels n+ n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
    • 8. Microwind
      • Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator
    • 9. Tools from Microwind
      • Microwind
      • DSCH
      • Microwind3 Editor
      • Microwind 2D viewer
      • Microwind 3D viewer
      • Microwind analog simulator
      • Microwind tutorial on MOS devices
      • View of Silicon Atoms
    • 10. Getting Microwind
      • Go to the website
      • http://www.microwind.net/document
      • Download the freeware version of the microwind
      • Unzip the files in a Folder
    • 11. Microwind Downloads
    • 12. INTRODUCTION THE TOOL User-friendly and intuitive design tool for educational use. The student draws the masks of the circuit layout and performs analog simulation The tool displays the layout in 2D, static 3D and animated 3D
    • 13. Our Approach
      • MOS DEVICE
      • Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids
      • Our approach : step-by-step illustration of the most important relationships between layout and performance.
      • Design of the MOS
      • I/V Simulation
      • 2D view
      • Time domain analysis
      1. 2. 3. 4.
    • 14. Feature Size
      • Chips are specified with set of masks
      • Minimum dimensions of masks determine transistor size (and hence speed, cost, and power)
      • Feature size f = distance between source and drain
      • Set by minimum width of polysilicon
      • Feature size improves 30% every 3 years or so
      • Normalize for feature size when describing design Rules
      • E.g. λ = 0 . 090 μ m in 0.180 μ m process
    • 15.
      • Layout design rules:
      • For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks.
      • They act as interface between the circuit designer and the process engineer.
    • 16. Editing Icons Access to Simulation 2D 3D Views Layout Library Simulation Properties Palette of Layers Active Layers Current Technology Work Area One dot on the grid is 5 lambda or 0.30 µm Menu Command Microwind Environment
    • 17. Design Rules N- Well
      • r101 Minimum width 12 λ
      • r102 Between wells 12 λ
      • r110 Minimum well Area 144 λ 2
      r 102 r 101 N - Well
    • 18.
      • r201 Minimum N+ and P+ diffusion width 4 λ
      r 201 r 201 N - Well P+ Diff N+ Diff
    • 19.
      • r202 Between two P+ and N+ diffusions 4 λ
      N - Well P+ Diff N+ Diff r 202 r 202
    • 20.
      • r203 Extra N-well after P+ diffusion 6 λ
      N - Well P+ Diff N+ Diff r 203 r 203
    • 21.
      • r204 Between N+ diffusion and n-well 6 λ
      r 204 N - Well P+ Diff N+ Diff
    • 22.
      • r210 Minimum diffusion area 16 λ 2
      r 210 r 210 N - Well P+ Diff N+ Diff
    • 23.
      • r301 Polysilicon Width 2 λ
      N - Well P+ Diff N+ Diff Polysilicon r 301 r 301 Polysilicon
    • 24.
      • r302 Polysilicon gate on Diffusion 2 λ
      N - Well P+ Diff N+ Diff Polysilicon r 302 r 302 Polysilicon
    • 25.
      • r307 Extra Polysilicon surrounding Diffusion 3 λ
      N - Well P+ Diff N+ Diff Polysilicon r 307 r 307 r 307 r 307 Polysilicon
    • 26.
      • r304 Between two Polysilicon boxes 3 λ
      N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 304 r 304
    • 27.
      • r307 Diffusion after Polysilicon 4 λ
      N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 307 r 307 r 307 r 307
    • 28.
      • r401 Contact width 2 λ
      Contact Polysilicon Contact Metal/Polysilicon Contact r 401
    • 29.
      • r404 Extra Poly surrounding contact 1 λ
      Contact Polysilicon Contact Metal/Polysilicon Contact r 404 r 404
    • 30.
      • r405 Extra metal surrounding contact 1 λ
      Contact Polysilicon Contact Metal/Polysilicon Contact r 405 r 405
    • 31.
      • r403 Extra diffusion surrounding contact 1 λ
      N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 403 r 403
    • 32.
      • r501 Between two Metals 4 λ
      Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 r 501 r 501
    • 33.
      • r510 Minimum Metal area 16 λ 2
      r 510 r 510 r 510 r 510 r 510 r 510 Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6
    • 34. Step 1: Select Foundary
    • 35. Step 2: Select Foundary
    • 36. Step 3: n+ Diffussion
    • 37. Step 4: Polysilicon
    • 38. Step 5: n+diff and Metal Contact
    • 39.
      • This Completes nMOS design
      • Now go for pMOS Design, and the first need is to construct N Well
    • 40. Step 6: Create N Well
    • 41. Step 6: p+ Diffusion
    • 42. Step 7: Polysilicon
    • 43. Step 8: Contacts
    • 44. Final Connections
      • pMOS Completed
      • Now Interconnection of pMOS and nMOS to complete inverter
      • Connect Source of pMOS to VDD and Source of nMOS to VSS.
      • Short the Drain of both pMOS and nMOS.
    • 45. INVERTER: Complete Design
    • 46. Check DRC
    • 47. Assign Source
      • Assign Signal (Clock) to Gate Terminal
      • Add Visible node at Output
    • 48. Inverter with Source
    • 49. Run Simulation
    • 50. VTC Characteristics
    • 51. Thanks Give Your Feedbacks at: www.amitdegada.weebly.com/blog.html
    • 52.  
    • 53.