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  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • 34 Praxair Semiconductor Manufacturing Technology, Module 3: Semiconductor Manufacturing Processes References I am grateful for the contributions from SEMATECH, the Austin Community College, and MKS Instruments. For further reading, I especially recommend the reference from Scientific American.
  • Lab inv l

    1. 1. Lab 1: To generate layout for CMOS Inverter circuit and simulate it for verification.
    2. 2. VLSI Lab VLSI LABORATORY FRONT END DESIGN (CAD) BACK END DESIGN (CAD) TECHNOLOGY (TCAD)
    3. 3. <ul><li>Proper hardware </li></ul><ul><li>Proper software </li></ul><ul><li>Foundry or link up with some fab lab </li></ul><ul><li>Test facility </li></ul><ul><li>Purpose </li></ul>
    4. 4. DESIGN STEPS <ul><li>SCHEMATIC </li></ul><ul><li>LAYOUT DESIGN </li></ul><ul><li>DRC </li></ul><ul><li>LAYOUT Vs SCHEMATIC </li></ul><ul><li>PARASITIC EXTRACTION </li></ul><ul><li>POST LAYOUT SIMULTION </li></ul>
    5. 5. List of Experiments <ul><li>To generate layout for CMOS Inverter circuit and simulate it for verification. </li></ul><ul><li>To prepare layout for given logic function and verify it with simulations. </li></ul><ul><li>Introduction to programmable devices (FPGA, CPLD), Hardware Description Language (VHDL), and the use programming tool. </li></ul><ul><li>Implementation of basic logic gates and its testing. </li></ul><ul><li>Implementation of adder circuits and its testing. </li></ul><ul><li>Implementation of J-K and D Flip Flops and its testing. </li></ul><ul><li>Implementation 4 to 1 multiplexer and its testing. </li></ul><ul><li>Implementation of 3 to 8 decoder and its testing. </li></ul><ul><li>Implementation of sequential adder and its testing. </li></ul><ul><li>Implementation of BCD counter and its testing. </li></ul><ul><li>Simulation of CMOS Inverter using SPICE for transfer characteristic. </li></ul><ul><li>Simulation and verification of two input CMOS NOR gate using SPICE. </li></ul><ul><li>Introduction to Block Diagram Mathod </li></ul><ul><li>Design of digital Logic using block diagram. </li></ul>
    6. 6. Project <ul><li>Mini Project: VHDL/Verilog based mini project with emphasis on design and implementation into the group of maximum 3 students. </li></ul>
    7. 7. Design Abstraction Levels n+ n+ S G D + DEVICE CIRCUIT GATE MODULE SYSTEM
    8. 8. Microwind <ul><li>Microwind is a tool for designing and simulating circuits at layout level. The tool features full editing facilities (copy, cut, past, duplicate, move), various views (MOS characteristics, 2D cross section, 3D process viewer), and an analog simulator </li></ul>
    9. 9. Tools from Microwind <ul><li>Microwind </li></ul><ul><li>DSCH </li></ul><ul><li>Microwind3 Editor </li></ul><ul><li>Microwind 2D viewer </li></ul><ul><li>Microwind 3D viewer </li></ul><ul><li>Microwind analog simulator </li></ul><ul><li>Microwind tutorial on MOS devices </li></ul><ul><li>View of Silicon Atoms </li></ul>
    10. 10. Getting Microwind <ul><li>Go to the website </li></ul><ul><li>http://www.microwind.net/document </li></ul><ul><li>Download the freeware version of the microwind </li></ul><ul><li>Unzip the files in a Folder </li></ul>
    11. 11. Microwind Downloads
    12. 12. INTRODUCTION THE TOOL User-friendly and intuitive design tool for educational use. The student draws the masks of the circuit layout and performs analog simulation The tool displays the layout in 2D, static 3D and animated 3D
    13. 13. Our Approach <ul><li>MOS DEVICE </li></ul><ul><li>Traditional teaching : in-depth explanation of the potentials, fields, threshold voltage, and eventually the expression of the current Ids </li></ul><ul><li>Our approach : step-by-step illustration of the most important relationships between layout and performance. </li></ul><ul><li>Design of the MOS </li></ul><ul><li>I/V Simulation </li></ul><ul><li>2D view </li></ul><ul><li>Time domain analysis </li></ul>1. 2. 3. 4.
    14. 14. Feature Size <ul><li>Chips are specified with set of masks </li></ul><ul><li>Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) </li></ul><ul><li>Feature size f = distance between source and drain </li></ul><ul><li>Set by minimum width of polysilicon </li></ul><ul><li>Feature size improves 30% every 3 years or so </li></ul><ul><li>Normalize for feature size when describing design Rules </li></ul><ul><li>E.g. λ = 0 . 090 μ m in 0.180 μ m process </li></ul>
    15. 15. <ul><li>Layout design rules: </li></ul><ul><li>For complex processes, it becomes difficult to understand the intricacies of the fabrication process and interpret different photo masks. </li></ul><ul><li>They act as interface between the circuit designer and the process engineer. </li></ul>
    16. 16. Editing Icons Access to Simulation 2D 3D Views Layout Library Simulation Properties Palette of Layers Active Layers Current Technology Work Area One dot on the grid is 5 lambda or 0.30 µm Menu Command Microwind Environment
    17. 17. Design Rules N- Well <ul><li>r101 Minimum width 12 λ </li></ul><ul><li>r102 Between wells 12 λ </li></ul><ul><li>r110 Minimum well Area 144 λ 2 </li></ul>r 102 r 101 N - Well
    18. 18. <ul><li>r201 Minimum N+ and P+ diffusion width 4 λ </li></ul>r 201 r 201 N - Well P+ Diff N+ Diff
    19. 19. <ul><li>r202 Between two P+ and N+ diffusions 4 λ </li></ul>N - Well P+ Diff N+ Diff r 202 r 202
    20. 20. <ul><li>r203 Extra N-well after P+ diffusion 6 λ </li></ul>N - Well P+ Diff N+ Diff r 203 r 203
    21. 21. <ul><li>r204 Between N+ diffusion and n-well 6 λ </li></ul>r 204 N - Well P+ Diff N+ Diff
    22. 22. <ul><li>r210 Minimum diffusion area 16 λ 2 </li></ul>r 210 r 210 N - Well P+ Diff N+ Diff
    23. 23. <ul><li>r301 Polysilicon Width 2 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon r 301 r 301 Polysilicon
    24. 24. <ul><li>r302 Polysilicon gate on Diffusion 2 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon r 302 r 302 Polysilicon
    25. 25. <ul><li>r307 Extra Polysilicon surrounding Diffusion 3 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon r 307 r 307 r 307 r 307 Polysilicon
    26. 26. <ul><li>r304 Between two Polysilicon boxes 3 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 304 r 304
    27. 27. <ul><li>r307 Diffusion after Polysilicon 4 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 307 r 307 r 307 r 307
    28. 28. <ul><li>r401 Contact width 2 λ </li></ul>Contact Polysilicon Contact Metal/Polysilicon Contact r 401
    29. 29. <ul><li>r404 Extra Poly surrounding contact 1 λ </li></ul>Contact Polysilicon Contact Metal/Polysilicon Contact r 404 r 404
    30. 30. <ul><li>r405 Extra metal surrounding contact 1 λ </li></ul>Contact Polysilicon Contact Metal/Polysilicon Contact r 405 r 405
    31. 31. <ul><li>r403 Extra diffusion surrounding contact 1 λ </li></ul>N - Well P+ Diff N+ Diff Polysilicon Polysilicon r 403 r 403
    32. 32. <ul><li>r501 Between two Metals 4 λ </li></ul>Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6 r 501 r 501
    33. 33. <ul><li>r510 Minimum Metal area 16 λ 2 </li></ul>r 510 r 510 r 510 r 510 r 510 r 510 Metal 1 Metal 2 Metal 3 Metal 4 Metal 5 Metal 6
    34. 34. Step 1: Select Foundary
    35. 35. Step 2: Select Foundary
    36. 36. Step 3: n+ Diffussion
    37. 37. Step 4: Polysilicon
    38. 38. Step 5: n+diff and Metal Contact
    39. 39. <ul><li>This Completes nMOS design </li></ul><ul><li>Now go for pMOS Design, and the first need is to construct N Well </li></ul>
    40. 40. Step 6: Create N Well
    41. 41. Step 6: p+ Diffusion
    42. 42. Step 7: Polysilicon
    43. 43. Step 8: Contacts
    44. 44. Final Connections <ul><li>pMOS Completed </li></ul><ul><li>Now Interconnection of pMOS and nMOS to complete inverter </li></ul><ul><li>Connect Source of pMOS to VDD and Source of nMOS to VSS. </li></ul><ul><li>Short the Drain of both pMOS and nMOS. </li></ul>
    45. 45. INVERTER: Complete Design
    46. 46. Check DRC
    47. 47. Assign Source <ul><li>Assign Signal (Clock) to Gate Terminal </li></ul><ul><li>Add Visible node at Output </li></ul>
    48. 48. Inverter with Source
    49. 49. Run Simulation
    50. 50. VTC Characteristics
    51. 51. Thanks Give Your Feedbacks at: www.amitdegada.weebly.com/blog.html

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