PIC Microcontroller Instruction Set
Outline <ul><li>Instruction set </li></ul><ul><li>Instruction description </li></ul><ul><li>Assembler directives </li></ul>
Instruction Set <ul><li>PIC16Cxx @ PIC16Fxx: 14-bit word (opcode) </li></ul><ul><li>Byte-oriented, bit-oriented & literal ...
Instruction Set   cont…
 
<ul><li>Instruction Descriptions </li></ul>
ADDLW   K <ul><li>Add the literal value K to register WREG and put the result back in the WREG register </li></ul><ul><li>...
ADDLW   K     cont… <ul><li>Instruction: ADDLW  15H </li></ul>W =  25 H Before After W = 10H
ADDWF   f, d <ul><li>Add together contents of WREG and a file register location (SFR @ GPR).  </li></ul><ul><li>Put the re...
ADDWF   f, d     cont… <ul><li>Instruction: MOVLW  17H </li></ul><ul><li>ADDWF  5H, 0 </li></ul>W =  17 H 5H = 0H Before A...
MOVF f, d      <ul><li>Move the content of f register upon the status of d </li></ul><ul><li>(f)    (d) </li></ul><ul><li...
MOVLW   k      <ul><li>Load k literal into WREG register </li></ul><ul><li>k    (W) </li></ul><ul><li>Don’t cares will be...
MOVWF   f      <ul><li>Move data from WREG register to f register </li></ul><ul><li>(W)    (f) </li></ul><ul><li>Not affe...
Review      <ul><li>Write instructions to move value 34H into the WREG register. </li></ul><ul><li>Write instructions to a...
Review      <ul><li>5. What is the result of the following code and where is it kept? </li></ul><ul><li>MOVLW 15H </li></u...
Review      <ul><li>Which of the following is (are) illegal? </li></ul><ul><li>(a)  ADDLW  300H (b)  ADDLW 50H </li></ul><...
Review     <ul><li>10. The instruction “MOVLW 44H” is a ____-byte instruction. </li></ul><ul><li>11. True or false.  All t...
Review     <ul><li>13. Give the value in fileReg 0x20 for the following: </li></ul><ul><li>MYCOUNT EQU 0x95 </li></ul><ul>...
Review     <ul><li>15. Find the C, Z and DC flag bits for the following code: </li></ul><ul><li>MOVLW  9FH </li></ul><ul><...
ANDLW   k     <ul><li>Logical AND k literal with the content of WREG register & the result is placed in the WREG register ...
ANDWF   f, d     <ul><li>AND the WREG register with f register </li></ul><ul><li>(W) + (f)    (d) </li></ul><ul><li>Affec...
BCF   f, b     <ul><li>Clear bit ‘b’ in file register </li></ul><ul><li>0    (f<b>) </li></ul><ul><li>Not affect on STATU...
BSF   f, b     <ul><li>Set bit ‘b’ in f register </li></ul><ul><li>1    (f<b>) </li></ul><ul><li>Not affect on STATUS reg...
BTFSS   f, b     <ul><li>Execute the next instruction if bit ‘b’ in file register ‘f’ is ‘ 0 ’, otherwise discard executin...
BTFSC   f, b     <ul><li>Execute the next instruction if bit ‘b’ in file register ‘f’ is ‘ 1 ’, otherwise discard executin...
Review     <ul><li>Assume RA3 is an input, represents condition of a door alarm.  If it goes LOW, it means that the door i...
CALL  k     <ul><li>Call subroutine </li></ul><ul><li>(PC) + 1    TOS (top of stack) </li></ul><ul><li>k    PC<10:0>  <...
CLRF  f     <ul><li>Clear the content of ‘f’ register </li></ul><ul><li>00h    (f) </li></ul><ul><li>1    Z </li></ul><u...
CLRW      <ul><li>Clear the content WREG register </li></ul><ul><li>00h    (W) </li></ul><ul><li>1    Z </li></ul><ul><l...
COMP f, d      <ul><li>Complement the content of ‘f’ register </li></ul><ul><li>(f)    (d) </li></ul><ul><li>Instruction:...
DECF f, d      <ul><li>Decrease ‘f’ register </li></ul><ul><li>(f) – 1    (d) </li></ul><ul><li>Instruction:  DECF CNT, 1...
DECFSZ  f, d       <ul><li>Decrease ‘f’ register and skip the next instruction if the result is 0; otherwise execute the n...
GOTO k      <ul><li>Unconditional branch </li></ul><ul><li>k    PC<10:0>  </li></ul><ul><li>(PCLATCH<4:3>)    PC<12:11> ...
Review     <ul><li>Toggle all the bits of the Port B by sending to it the values 55H and AAH continuously.  Put a time del...
INCF   f, d      <ul><li>Increase the content of ‘f’ register </li></ul><ul><li>(f) + 1    (d) </li></ul><ul><li>d is des...
INCFSZ   f, d    <ul><li>Increase the content of ‘f’ register and skip the next instruction if the result is 0; otherwise ...
Review     <ul><li>The difference between “INCF f, W” & “INCF f, F” </li></ul><ul><li>MOVLW O </li></ul><ul><li>MOVWF Ox20...
IORLW   k      <ul><li>Inclusive OR literal ‘k’ with the content of WREG register </li></ul><ul><li>(W) OR k    (W) </li>...
IORWF   f, d      <ul><li>Inclusive OR the content of WREG register with f register  </li></ul><ul><li>(W) OR (f)    (d) ...
Review     <ul><li>Find the contents of register WREG after execution of the following code: </li></ul><ul><li>MOVLW  0 </...
NOP      <ul><li>No operation </li></ul><ul><li>Instruction:  NOP </li></ul>
RETFIE      <ul><li>Return from interrupt </li></ul><ul><li>TOS    PC </li></ul><ul><li>1    GIE (Global Interrupt Enabl...
RETLW   k      <ul><li>Return with loading literal ‘k’ onto WREG register, k    (W) </li></ul><ul><li>TOS    PC </li></u...
RETURN     <ul><li>Return from subroutine </li></ul><ul><li>POP the TOS and load into the PC </li></ul><ul><li>2-cycle ins...
RLF f, d     <ul><li>Rotate left f through carry </li></ul><ul><li>Affect bit ‘C’ of STATUS register </li></ul><ul><li>Ins...
RRF f, d     <ul><li>Rotate right f through carry </li></ul><ul><li>Affect bit ‘C’ of STATUS register </li></ul><ul><li>In...
Review     <ul><li>Find the contents of file register MYREG after execution of the following code: </li></ul><ul><li>MYREG...
Review     <ul><li>Find the contents of file register MYREG after execution of the following code: </li></ul><ul><li>MREG ...
SLEEP      <ul><li>00h    WDT </li></ul><ul><li>0    WDT prescalar </li></ul><ul><li>1    TO </li></ul><ul><li>0    PD...
SUBLW k     <ul><li>Subtract WREG register (2’s complement) from literal ‘k’ and put the result onto WREG register </li></...
SUBWF   f, d     <ul><li>Subtract WREG register (2’s complement) from f register  </li></ul><ul><li>(f) – (W)    (d) </li...
Review     <ul><li>Show the steps involved in the following. </li></ul><ul><li>MOVLW 0x23 </li></ul><ul><li>SUBLW 0x3F </l...
SWAPF   f, d     <ul><li>Exchange the upper & lower nibbles of f register </li></ul><ul><li>(f<3:0)    (d<7:4>), (f<7:4) ...
Review     <ul><li>Find the contents of the MYREG register in the following code. </li></ul><ul><li>MYREG EQU 0x20 </li></...
XORLW   k      <ul><li>Exclusive OR (XOR) the content of WREG register with k literal </li></ul><ul><li>(W) XOR k    (W) ...
XORWF   f, d      <ul><li>Exclusive OR (XOR) the content of WREG register with f register </li></ul><ul><li>(W) XOR (f)  ...
Review     <ul><li>Show the results of the following: </li></ul><ul><li>MOVLW 0x54 </li></ul><ul><li>XORLW 0x78 </li></ul>...
Assembler Directives   <ul><li>Also known as pseudo-instructions </li></ul><ul><li>Give directions to assembler </li></ul>...
Assembler Directives   <ul><li>Using EQU for fixed data assignment: </li></ul><ul><li>;in hexadecimal </li></ul><ul><li>DA...
Assembler Directives   <ul><li>Using EQU for SFR address assignment: </li></ul><ul><li>COUNTER EQU 0x00 </li></ul><ul><li>...
Assembler Directives   <ul><li>Using EQU for RAM address assignment: </li></ul><ul><li>MYREG EQU 0x12 </li></ul><ul><li>MO...
Assembler Directives   <ul><li>SET directive: </li></ul><ul><li>Define a constant value or a fixed address </li></ul><ul><...
Assembler Directives   <ul><li>LIST directive: </li></ul><ul><li>Unique to PIC assembler </li></ul><ul><li>Indicate specif...
Assembler Directives   <ul><li>_config directive: </li></ul><ul><li>Tells the assembler the configuration bits for the tar...
Upcoming SlideShare
Loading in...5
×

Chp5 pic microcontroller instruction set copy

6,361

Published on

Published in: Education, Technology, Sports
3 Comments
1 Like
Statistics
Notes
No Downloads
Views
Total Views
6,361
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
422
Comments
3
Likes
1
Embeds 0
No embeds

No notes for slide

Chp5 pic microcontroller instruction set copy

  1. 1. PIC Microcontroller Instruction Set
  2. 2. Outline <ul><li>Instruction set </li></ul><ul><li>Instruction description </li></ul><ul><li>Assembler directives </li></ul>
  3. 3. Instruction Set <ul><li>PIC16Cxx @ PIC16Fxx: 14-bit word (opcode) </li></ul><ul><li>Byte-oriented, bit-oriented & literal and control </li></ul>
  4. 4. Instruction Set cont…
  5. 6. <ul><li>Instruction Descriptions </li></ul>
  6. 7. ADDLW K <ul><li>Add the literal value K to register WREG and put the result back in the WREG register </li></ul><ul><li>( W ) + k  ( W ) </li></ul><ul><li>K is an 8-bit value: 0-255 (decimal), 00-FF (hex) </li></ul><ul><li>L: literal (actual value) </li></ul><ul><li>Affect STATUS bits: C , DC , Z </li></ul>
  7. 8. ADDLW K cont… <ul><li>Instruction: ADDLW 15H </li></ul>W = 25 H Before After W = 10H
  8. 9. ADDWF f, d <ul><li>Add together contents of WREG and a file register location (SFR @ GPR). </li></ul><ul><li>Put the result in the register WREG if d = 0 otherwise it is stored back in register f. </li></ul><ul><li>( W ) + ( f )  ( d ) </li></ul><ul><li>0  f  127, d  [0, 1] </li></ul><ul><li>Affect STATUS bits: C , DC , Z </li></ul>
  9. 10. ADDWF f, d cont… <ul><li>Instruction: MOVLW 17H </li></ul><ul><li>ADDWF 5H, 0 </li></ul>W = 17 H 5H = 0H Before After W = 0H 5H = 0H
  10. 11. MOVF f, d <ul><li>Move the content of f register upon the status of d </li></ul><ul><li>(f)  (d) </li></ul><ul><li>Affect bit ‘Z’ of STATUS register </li></ul><ul><li>Instruction: MOVF FSR, 0 </li></ul>W = value in FSR register Z = 1 Before After W = 09AH FSR = 0H
  11. 12. MOVLW k <ul><li>Load k literal into WREG register </li></ul><ul><li>k  (W) </li></ul><ul><li>Don’t cares will be assembled as 0’s </li></ul><ul><li>Not affect bit of STATUS register </li></ul><ul><li>Instruction: MOVLW 5AH </li></ul>W = 5AH Before After W = 09AH
  12. 13. MOVWF f <ul><li>Move data from WREG register to f register </li></ul><ul><li>(W)  (f) </li></ul><ul><li>Not affect bit of STATUS register </li></ul><ul><li>Instruction: MOVWF PORTB </li></ul>PORTB = 09AH W = 09AH Before After PORTB = 00H W = 09AH
  13. 14. Review <ul><li>Write instructions to move value 34H into the WREG register. </li></ul><ul><li>Write instructions to add the values 16H and CDH. Place the result in the WREG register. </li></ul><ul><li>True or false. No value can be moved directly into the WREG register. </li></ul><ul><li>What is the largest hex value that can be moved into an 8-bit register? What is the decimal equivalent of that hex value? </li></ul>
  14. 15. Review <ul><li>5. What is the result of the following code and where is it kept? </li></ul><ul><li>MOVLW 15H </li></ul><ul><li>ADDLW 13H </li></ul><ul><li>Which of the following is (are) illegal? </li></ul><ul><li>(a) MOVLW 500 (b) MOVLW 50 </li></ul><ul><li>(c) MOVLW 00 (d) MOVLW 255H </li></ul><ul><li>(e) MOVLW 25H (f) MOVLW F5H </li></ul><ul><li>(g) MOVLW mybyte, 50H </li></ul>
  15. 16. Review <ul><li>Which of the following is (are) illegal? </li></ul><ul><li>(a) ADDLW 300H (b) ADDLW 50H </li></ul><ul><li>(c) ADDLW $500 (d) ADDLW 255H </li></ul><ul><li>(e) ADDLW 12H (f) ADDLW 0F5 </li></ul><ul><li>(g) ADDLW 25H </li></ul><ul><li>8. True or false. We have many WREG registers in the PIC16. </li></ul><ul><li>9. The literal value in MOVLW is _____ bits wide. </li></ul>
  16. 17. Review <ul><li>10. The instruction “MOVLW 44H” is a ____-byte instruction. </li></ul><ul><li>11. True or false. All the instructions in the PIC16 are 2-cycle instructions. </li></ul><ul><li>12. Give the value in WREG for the following: </li></ul><ul><li>MYCOUNT EQU 15 </li></ul><ul><li>MOVLW MYCOUNT </li></ul>
  17. 18. Review <ul><li>13. Give the value in fileReg 0x20 for the following: </li></ul><ul><li>MYCOUNT EQU 0x95 </li></ul><ul><li>MYREG EQU 0x20 </li></ul><ul><li>MOVLW MYCOUNT </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>14. Give the value in fileReg 0x63 for the following: </li></ul><ul><li>MYDATA EQU D’12’ </li></ul><ul><li>MYREG EQU 0x63 </li></ul><ul><li>FACTOR EQU 0x10 </li></ul><ul><li>MOVLW MYDATA </li></ul><ul><li>ADDLW FACTOR </li></ul><ul><li>MOVWF MYREG </li></ul>
  18. 19. Review <ul><li>15. Find the C, Z and DC flag bits for the following code: </li></ul><ul><li>MOVLW 9FH </li></ul><ul><li>ADDLW 61H </li></ul><ul><li>16. Find the C, Z and DC flag bits for the following: </li></ul><ul><li>MOVLW 82H </li></ul><ul><li>ADDLW 22H </li></ul>
  19. 20. ANDLW k <ul><li>Logical AND k literal with the content of WREG register & the result is placed in the WREG register </li></ul><ul><li>(W) AND k  (W) </li></ul><ul><li>Affect Z bit of STATUS register </li></ul><ul><li>Instruction: ANDLW 5FH </li></ul>W = 03 H Before After W = A3H
  20. 21. ANDWF f, d <ul><li>AND the WREG register with f register </li></ul><ul><li>(W) + (f)  (d) </li></ul><ul><li>Affect Z bit of STATUS register </li></ul><ul><li>Instruction: ANDWF FSR, 1 </li></ul>W = 17H FSR = 02 H Before After W = 17H FSR = 0C2H
  21. 22. BCF f, b <ul><li>Clear bit ‘b’ in file register </li></ul><ul><li>0  (f<b>) </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: BCF STATUS, 5 </li></ul>STATUS = 087H Before After STATUS = 0A7H
  22. 23. BSF f, b <ul><li>Set bit ‘b’ in f register </li></ul><ul><li>1  (f<b>) </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: BSF INTCON, 7 </li></ul>INTCON = 08BH Before After INTCON = 0BH
  23. 24. BTFSS f, b <ul><li>Execute the next instruction if bit ‘b’ in file register ‘f’ is ‘ 0 ’, otherwise discard executing next instruction </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: H BTFSS STATUS, 2 </li></ul><ul><li> I GOTO LOOP </li></ul><ul><li> J ……… </li></ul><ul><li> ……… </li></ul>PC = Add. J if STATUS<2> = 1, PC = Add. I if STATUS<2> = 0 Before After PC = address H
  24. 25. BTFSC f, b <ul><li>Execute the next instruction if bit ‘b’ in file register ‘f’ is ‘ 1 ’, otherwise discard executing next instruction </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: H BTFSC PORTA, 3 </li></ul><ul><li> I GOTO LOOP </li></ul><ul><li> J ……… </li></ul><ul><li> ……… </li></ul>PC = Add. J if PORTA<3> = 0, PC = Add. I if PORTA<3> = 1 Before After PC = address H
  25. 26. Review <ul><li>Assume RA3 is an input, represents condition of a door alarm. If it goes LOW, it means that the door is opened. Create a program to monitor the bit continuously. Whenever it goes LOW, send a HIGH pulse to port RB5 and turn on buzzer </li></ul><ul><li>BSF 03H, 5 </li></ul><ul><li>BSF 85H, 3 </li></ul><ul><li>BCF 86H, 5 </li></ul><ul><li>BCF 03H, 5 </li></ul><ul><li>HERE BTFSC 05H, 3 </li></ul><ul><li>GOTO OFF </li></ul><ul><li>BSF 6H, 5 </li></ul><ul><li>GOTO HERE </li></ul><ul><li>OFF BCF 6H, 5 </li></ul><ul><li>GOTO HERE </li></ul>PIC RA3 RB5 Vcc
  26. 27. CALL k <ul><li>Call subroutine </li></ul><ul><li>(PC) + 1  TOS (top of stack) </li></ul><ul><li>k  PC<10:0> </li></ul><ul><li>(PCLATCH<4:3>)  PC<12:11> </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: SO CALL THEN </li></ul><ul><li> ……… </li></ul><ul><li> ……… </li></ul>PC = add. THEN; TOS = add. SO+1 Before After PC = add. SO
  27. 28. CLRF f <ul><li>Clear the content of ‘f’ register </li></ul><ul><li>00h  (f) </li></ul><ul><li>1  Z </li></ul><ul><li>Instruction: CLRF PORTA </li></ul>PORTA = 00H Z = 1 Before After PORTA = 5AH
  28. 29. CLRW <ul><li>Clear the content WREG register </li></ul><ul><li>00h  (W) </li></ul><ul><li>1  Z </li></ul><ul><li>Instruction: CLRW </li></ul>W = 00H Z = 1 Before After W = 5AH
  29. 30. COMP f, d <ul><li>Complement the content of ‘f’ register </li></ul><ul><li>(f)  (d) </li></ul><ul><li>Instruction: COMP ONE, 0 </li></ul>ONE = 13H W = 0ECH Before After ONE = 13H W = 02H
  30. 31. DECF f, d <ul><li>Decrease ‘f’ register </li></ul><ul><li>(f) – 1  (d) </li></ul><ul><li>Instruction: DECF CNT, 1 </li></ul>CNT = 00H Z = 1 Before After CNT = 01H Z = 0
  31. 32. DECFSZ f, d <ul><li>Decrease ‘f’ register and skip the next instruction if the result is 0; otherwise execute the next instruction </li></ul><ul><li>(f) – 1  (d), skip if result = 0 </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Instruction: HERE DECFSZ CNT, 1 </li></ul><ul><li>GOTO HERE </li></ul><ul><li> CONT ……… </li></ul><ul><li> …… .. </li></ul>CNT = CNT - 1 PC = add. CONT if CNT = 0; PC = add. HERE + 1 if CNT  0 Before After PC = add. HERE
  32. 33. GOTO k <ul><li>Unconditional branch </li></ul><ul><li>k  PC<10:0> </li></ul><ul><li>(PCLATCH<4:3>)  PC<12:11> </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Instruction: HERE GOTO THERE </li></ul><ul><li> ……… </li></ul><ul><li> THERE ……… </li></ul>PC = add. THERE Before After PC = add. HERE
  33. 34. Review <ul><li>Toggle all the bits of the Port B by sending to it the values 55H and AAH continuously. Put a time delay in between each issuing of data to Port B. </li></ul><ul><li>MYREG EQU 0x08 </li></ul><ul><li>ORG 0 </li></ul><ul><li>BACK MOVLW 0x55 </li></ul><ul><li>MOVWF PORTB </li></ul><ul><li>CALL DELAY </li></ul><ul><li>MOVLW 0xAA </li></ul><ul><li>MOVWF PORTB </li></ul><ul><li>CALL DELAY </li></ul><ul><li>GOTO BACK </li></ul><ul><li>;this is the delay subroutine </li></ul><ul><li>ORG 300H </li></ul><ul><li>DELAY MOVLW 0xFF </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>AGAIN NOP </li></ul><ul><li>NOP </li></ul><ul><li>DECFSZ MYREG, F </li></ul><ul><li>GOTO AGAIN </li></ul><ul><li>RETURN </li></ul><ul><li>END </li></ul>
  34. 35. INCF f, d <ul><li>Increase the content of ‘f’ register </li></ul><ul><li>(f) + 1  (d) </li></ul><ul><li>d is destination </li></ul><ul><li>Instruction: INCF SATU, 1 </li></ul>SATU = 00H Z = 1 Before After SATU = 0FFH
  35. 36. INCFSZ f, d <ul><li>Increase the content of ‘f’ register and skip the next instruction if the result is 0; otherwise execute the next instruction </li></ul><ul><li>(f) + 1  (d), skip if result = 0 </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Instruction: HERE INCFSZ CNT, 1 </li></ul><ul><li> GOTO loop </li></ul><ul><li> CONT ……… </li></ul><ul><li> …… .. </li></ul>CNT = CNT + 1 PC = add. CONT if CNT = 0; else add. HERE + 1 Before After PC = add. HERE
  36. 37. Review <ul><li>The difference between “INCF f, W” & “INCF f, F” </li></ul><ul><li>MOVLW O </li></ul><ul><li>MOVWF Ox20 </li></ul><ul><li>INCF 0x20, W </li></ul><ul><li>INCF 0x20, W </li></ul><ul><li>INCF 0x20, W </li></ul><ul><li>INCF 0x20, F </li></ul><ul><li>INCF 0x20, F </li></ul><ul><li>INCF 0x20 </li></ul><ul><li>INCF 0x20 </li></ul><ul><li>INCF 0x20, W </li></ul>;WREG = 0 ;0x20 = (0), WREG = 1 ;0x20 = (0), WREG = 1 ;0x20 = (0), WREG = 1 ;0x20 = (1), WREG = 1 ;0x20 = (2), WREG = 1 ;0x20 = (3), WREG = 1 ;0x20 = (4), WREG = 1 ;0x20 = (4), WREG = 5
  37. 38. IORLW k <ul><li>Inclusive OR literal ‘k’ with the content of WREG register </li></ul><ul><li>(W) OR k  (W) </li></ul><ul><li>Affect bit ‘Z’ of STATUS register </li></ul><ul><li>Instruction: IORLW 35H </li></ul>W = 0BFH Z = 0 Before After W = 09AH Z = ?
  38. 39. IORWF f, d <ul><li>Inclusive OR the content of WREG register with f register </li></ul><ul><li>(W) OR (f)  (d) </li></ul><ul><li>Affect bit ‘Z’ of STATUS register </li></ul><ul><li>Instruction: IORWF RESULT, 0 </li></ul>RESULT = 13H W = 93H Z = 0 Before After RESULT = 13H W = 91H
  39. 40. Review <ul><li>Find the contents of register WREG after execution of the following code: </li></ul><ul><li>MOVLW 0 </li></ul><ul><li>IORLW 0x99 </li></ul><ul><li>XORLW 0xFF </li></ul>
  40. 41. NOP <ul><li>No operation </li></ul><ul><li>Instruction: NOP </li></ul>
  41. 42. RETFIE <ul><li>Return from interrupt </li></ul><ul><li>TOS  PC </li></ul><ul><li>1  GIE (Global Interrupt Enable) </li></ul><ul><li>Not affect bit of STATUS register </li></ul><ul><li>Instruction: RETFIE </li></ul>PC = TOS GIE = 1 Before After
  42. 43. RETLW k <ul><li>Return with loading literal ‘k’ onto WREG register, k  (W) </li></ul><ul><li>TOS  PC </li></ul><ul><li>Not affect on STATUS register </li></ul><ul><li>Instruction: RETLW 088H </li></ul>W = 088H Before After W = 09AH
  43. 44. RETURN <ul><li>Return from subroutine </li></ul><ul><li>POP the TOS and load into the PC </li></ul><ul><li>2-cycle instruction </li></ul><ul><li>Instruction: RETURN </li></ul>PC = TOS Before After
  44. 45. RLF f, d <ul><li>Rotate left f through carry </li></ul><ul><li>Affect bit ‘C’ of STATUS register </li></ul><ul><li>Instruction: RLF REG, 1 </li></ul>REG = 1111 1110 = 0FEH C = 1 Before After REG = 1111 1111 = 0FFH C = 0
  45. 46. RRF f, d <ul><li>Rotate right f through carry </li></ul><ul><li>Affect bit ‘C’ of STATUS register </li></ul><ul><li>Instruction: RRF REG, 1 </li></ul>REG = 0111 1011 = 07BH C = 1 Before After REG = 1111 0111 = 0F7H C = 0
  46. 47. Review <ul><li>Find the contents of file register MYREG after execution of the following code: </li></ul><ul><li>MYREG EQU 0x20 </li></ul><ul><li>BCF STATUS, C </li></ul><ul><li>MOVLW 0x26 </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>RRF MYREG, F </li></ul><ul><li>RRF MYREG, F </li></ul><ul><li>RRF MYREG, F </li></ul>;C=0 ;WREG=0010 0110 ;MYREG=0001 0011 C=0 ;MYREG=0000 1001 C=1 ;MYREG=1000 0100 C=1
  47. 48. Review <ul><li>Find the contents of file register MYREG after execution of the following code: </li></ul><ul><li>MREG EQU 0x20 </li></ul><ul><li>BSF STATUS, C </li></ul><ul><li>MOVLW 0x15 </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>RLF MYREG, F </li></ul><ul><li>RLF MYREG, F </li></ul><ul><li>RLF MYREG, F </li></ul><ul><li>RLF MYREG, F </li></ul>;C=1 ;WREG=0001 0101 ;MYREG=0010 1011 C=0 ;MYREG=0101 0110 C=0 ;MYREG=1010 1100 C=0 ;MYREG=0101 1000 C=1
  48. 49. SLEEP <ul><li>00h  WDT </li></ul><ul><li>0  WDT prescalar </li></ul><ul><li>1  TO </li></ul><ul><li>0  PD </li></ul><ul><li>Affect TO & PD bits of STATUS register </li></ul><ul><li>Instruction: SLEEP </li></ul>
  49. 50. SUBLW k <ul><li>Subtract WREG register (2’s complement) from literal ‘k’ and put the result onto WREG register </li></ul><ul><li>k – (W)  (W) </li></ul><ul><li>Affect C, DC & Z bits of STATUS register </li></ul><ul><li>Instruction: SUBLW 02H </li></ul>W = 01H C = 1 Z = 0 Before After W = 01H C = ? Z = ?
  50. 51. SUBWF f, d <ul><li>Subtract WREG register (2’s complement) from f register </li></ul><ul><li>(f) – (W)  (d) </li></ul><ul><li>Affect C, DC & Z bits of STATUS register </li></ul><ul><li>Instruction: SUBWF 02H, 0 </li></ul>W = 04H F = 05H C = 1 Z = 0 Before After W = 01H F = 05H C = ? Z = ?
  51. 52. Review <ul><li>Show the steps involved in the following. </li></ul><ul><li>MOVLW 0x23 </li></ul><ul><li>SUBLW 0x3F </li></ul>K = 3F 0011 1111 - WREG = 23 0010 0011 1C 0011 1111 + 1101 1101 (2’s complement) 1 0001 1100 C = 1, Z = 0 (result is +ve)
  52. 53. SWAPF f, d <ul><li>Exchange the upper & lower nibbles of f register </li></ul><ul><li>(f<3:0)  (d<7:4>), (f<7:4)  (d<3:0>) </li></ul><ul><li>Not affect STATUS register </li></ul><ul><li>Instruction: SWAPF ON, 1 </li></ul>ON = 04FH W = 09AH Before After ON = 0F4H W = 09AH
  53. 54. Review <ul><li>Find the contents of the MYREG register in the following code. </li></ul><ul><li>MYREG EQU 0x20 </li></ul><ul><li>MOVLW 0x72 </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>SWAPF MYREG, F </li></ul>;WREG = 72H ;MYREG = 72H ;MYREG = 27H
  54. 55. XORLW k <ul><li>Exclusive OR (XOR) the content of WREG register with k literal </li></ul><ul><li>(W) XOR k  (W) </li></ul><ul><li>Store the result in WREG register </li></ul><ul><li>Affect bit ‘Z’ of STATUS register </li></ul><ul><li>Instruction: XORLW 0AFH </li></ul>W = 01AH Before After W = 0B5H
  55. 56. XORWF f, d <ul><li>Exclusive OR (XOR) the content of WREG register with f register </li></ul><ul><li>(W) XOR (f)  (d) </li></ul><ul><li>Affect bit ‘Z’ of STATUS register </li></ul><ul><li>Instruction: XORWF REG, 1 </li></ul>REG = 01AH W = 0B5H Before After REG = 0AFH W = 0B5H
  56. 57. Review <ul><li>Show the results of the following: </li></ul><ul><li>MOVLW 0x54 </li></ul><ul><li>XORLW 0x78 </li></ul>54H = 0 1 0 1 0 1 0 0 78H = 0 1 1 1 1 0 0 0 2CH = 0 0 1 0 1 1 0 0 54H XOR 78H = 2CH, Z = 0
  57. 58. Assembler Directives <ul><li>Also known as pseudo-instructions </li></ul><ul><li>Give directions to assembler </li></ul><ul><li>EQU, ORG, END </li></ul><ul><li>EQU directive: </li></ul><ul><li>Define a constant value or a fixed address </li></ul><ul><li>COUNT EQU 0x25 </li></ul><ul><li>… . </li></ul><ul><li>MOVLW COUNT </li></ul>
  58. 59. Assembler Directives <ul><li>Using EQU for fixed data assignment: </li></ul><ul><li>;in hexadecimal </li></ul><ul><li>DATA1 EQU 39 </li></ul><ul><li>DATA2 EQU 0x39 </li></ul><ul><li>DATA3 EQU 39H </li></ul><ul><li>DATA4 EQU H’39’ </li></ul><ul><li>DATA5 EQU h’39’ </li></ul><ul><li>;in binary </li></ul><ul><li>DATA6 EQU B’00110101’ </li></ul><ul><li>DATA7 EQU b’00110101’ </li></ul>;in decimal DATA8 EQU D’28’ DATA9 EQU d’28’ ;in ASCII DATA10 EQU A’2’ DATA11 EQU a’2’ DATA12 EQU ‘2’
  59. 60. Assembler Directives <ul><li>Using EQU for SFR address assignment: </li></ul><ul><li>COUNTER EQU 0x00 </li></ul><ul><li>PORTB EQU 0x06 </li></ul><ul><li>MOVLW COUNTER </li></ul><ul><li>MOVWF PORTB </li></ul><ul><li>INCF PORTB, F </li></ul><ul><li>INCF PORTB, F </li></ul><ul><li>INCF PORTB, F </li></ul>
  60. 61. Assembler Directives <ul><li>Using EQU for RAM address assignment: </li></ul><ul><li>MYREG EQU 0x12 </li></ul><ul><li>MOVLW 0 </li></ul><ul><li>MOVWF MYREG </li></ul><ul><li>MOVLW 22H </li></ul><ul><li>ADDWF MYREG, F </li></ul><ul><li>ADDWF MYREG, F </li></ul><ul><li>ADDWF MYREG, F </li></ul>
  61. 62. Assembler Directives <ul><li>SET directive: </li></ul><ul><li>Define a constant value or a fixed address </li></ul><ul><li>Identical with EQU directive, the only difference is the value assigned by the SET directive may be reassigned later </li></ul><ul><li>END directive: </li></ul><ul><li>Indicate the end of the source (asm) file </li></ul>cont…
  62. 63. Assembler Directives <ul><li>LIST directive: </li></ul><ul><li>Unique to PIC assembler </li></ul><ul><li>Indicate specific PIC chip for which the program should be assembled </li></ul><ul><li>LIST P = 16F84A </li></ul><ul><li>#include directive: </li></ul><ul><li>Tells the PIC assembler to use the libraries associated with the specific chip to compile the program </li></ul>cont…
  63. 64. Assembler Directives <ul><li>_config directive: </li></ul><ul><li>Tells the assembler the configuration bits for the target device </li></ul><ul><li>Incorrect use may cause the chip unusable  </li></ul><ul><li>CONFIG OSC=HS </li></ul><ul><li>CONFIG WDT=OFF </li></ul><ul><li>radix directive: </li></ul><ul><li>Indicate numbering system whether it is hexadecimal or decimal </li></ul><ul><li>RADIX DEC </li></ul>cont…
  1. ¿Le ha llamado la atención una diapositiva en particular?

    Recortar diapositivas es una manera útil de recopilar información importante para consultarla más tarde.

×