Chp3 designing bus system, memory & io copy

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Chp3 designing bus system, memory & io copy

  1. 1. Designing Bus System, Memory & I/O
  2. 2. The 68k Address & Data Bus <ul><li>16-bit wide data bus </li></ul><ul><li>24-bit address bus </li></ul><ul><li>A 0 bit controls and signals </li></ul>D15 D0 D8 D7
  3. 3. The 68k Address & Data Bus Cont…
  4. 4. Example <ul><li>1. Explain the different functions of the internal A 0 bit when used for: </li></ul><ul><li>a. byte addressing </li></ul><ul><li>b. word addressing </li></ul>a. A 0 is used to activate UDS or LDS b. A 0 is ignored, UDS and LDS are both low
  5. 5. Example <ul><li>2. Show the states of UDS and LDS when the 68000 is involve in the following memory accesses: </li></ul><ul><li>a. a byte write to address 3000 </li></ul><ul><li>b. a byte write to address 3001 </li></ul><ul><li>c. a word write to address 3000 </li></ul>a. UDS = 0, LDS = 1 b. UDS = 1, LDS = 0 c. UDS = 0, LDS = 0
  6. 6. Bus Buffering CPU Memory Control Data Address bidirectional unidirectional
  7. 7. Accessing Memory Read Data from Memory
  8. 8. Memory Accessing Cont… Read Data from Memory
  9. 9. Memory Accessing Write Data to Memory
  10. 10. Memory Accessing Cont… Write Data to Memory
  11. 11. Designing a Memory Address Decoder <ul><li>monitor the state of the address bus </li></ul><ul><li>determine right time to enable the memory chip </li></ul><ul><li>facilitate address bus and configure time to activate memory chip </li></ul><ul><li>Memory chip: RAMs or EPROMs </li></ul>
  12. 12. Designing a Memory Address Decoder Cont… <ul><li>68000 contain many devices. </li></ul><ul><li>Only one can communicate with up at one time. </li></ul><ul><li>Address Decoder select only one active device </li></ul>EPROM or SRAM CS* SEL* AS* Memory AddressDecoder Address bus Valid Address A1-A23 AS* SEL*
  13. 13. Designing a Memory Address Decoder Cont…  P AS* Address bus Address bus lower section Address bus upper section Address decoder Device selector RAM switch LED ROM
  14. 14. Full Address Decoder <ul><li>Challenge : </li></ul><ul><li>The designer of the memory decoder is to chip-enable the memory device at the correct time. </li></ul><ul><li>Steps: </li></ul><ul><li>1. Determine the address range for device </li></ul><ul><li>a. find the first address of the RAM (base address) </li></ul><ul><li>b. what is the entire range of RAM addresses </li></ul><ul><li>c. find the last address </li></ul><ul><li>2. Determine which address line go to memory and the decoder </li></ul><ul><li>a. find the sum of line address at the device </li></ul><ul><li>b. low address line from the uP go to the memory </li></ul><ul><li>c. balance of the address go to the decoder </li></ul><ul><li>3. Design a decoder to detect the require address line by using </li></ul><ul><li> digital gets </li></ul>
  15. 15. Full Address Decoder <ul><li>Example 3.1: </li></ul><ul><li>Determine the address range for 2764 </li></ul><ul><li>chip used for EPROM. </li></ul><ul><li>Solution: </li></ul><ul><li>All EPROM in 68k system must start at $000000 </li></ul><ul><li>One 2764 chip contain 8kbyte. </li></ul><ul><li>For 68000, must be used coupled </li></ul><ul><li>If we are using 2 chip, the EPROM size is 8 kbyte x 2 = 16kb </li></ul>Cont…
  16. 16. Full Address Decoder <ul><li>Address line calculation: </li></ul><ul><li>Address line = Log 2 Address </li></ul><ul><li>= Log 2 16 kilobyte </li></ul><ul><li>= Log 2 16(1024) </li></ul><ul><li>= Log 10 16384 / log 10 2 </li></ul><ul><li>= 14 lines </li></ul><ul><li>a. Base address : $000000 </li></ul><ul><li>b. Entire range : 16384 (0 – 16383) </li></ul><ul><li>c. Last EPROM address : 16383 10 =$ 003FFF </li></ul>Cont…
  17. 17. Full Address Decoder <ul><li>For 68000 </li></ul><ul><li>a. A0 : no connection </li></ul><ul><li>b. A1-A14 : 14 direct line to 2764 </li></ul><ul><li>c. A15-A23 : to decoder </li></ul>Cont… ROM 16kbyte Not used Memory Map $000000 $3FFFFF $400000 $FFFFFF
  18. 18. Full Address Decoder <ul><li>Example 3.2: </li></ul><ul><li>A memory device consist 64 word (128kbyte), RAM must be interface with 68000. Base address $480000. </li></ul><ul><li>Solution: </li></ul><ul><li>1.Memory started at $480000: </li></ul><ul><li>Location : $480000 + $20000 = $4A0000 </li></ul><ul><li>Last Address : $4A0000 – 1 = $49FFFF </li></ul><ul><li>Address range : $480000 - $49FFFF </li></ul>Cont…
  19. 19. Full Address Decoder <ul><li>2. Determine the address line connected to address decoder </li></ul><ul><li>$480000 = 0100 1000 0000 0000 0000 0000 </li></ul><ul><li>$49FFFF = 0100 1001 1111 1111 1111 1111 </li></ul><ul><li>Start from right: </li></ul><ul><li>A1-A16 : direct to memory </li></ul><ul><li>A0 : directly to UDS* and LDS* </li></ul><ul><li>Checking : 2 17 = 128k </li></ul><ul><li>So line balance A17- A23 go to decoder </li></ul>Cont…
  20. 20. Full Address Decoder <ul><li>3. Design circuit that sense AS* = 0 and </li></ul><ul><li>A23-A17 = 0100100 </li></ul><ul><li>Circuit below decode $480000 - $49FFFF address by detecting A23-A17 = 0100100 </li></ul>Cont…
  21. 21. Full Address Decoder Cont…
  22. 22. Partial Address Decoder <ul><li>Most of the applications would require much smaller memories </li></ul><ul><li>Challenge: </li></ul><ul><li>To reduce logic when developing memory decoder </li></ul><ul><li>Steps: </li></ul><ul><li>1. Determine address range for every device </li></ul><ul><li>a. find starting address (base address) </li></ul><ul><li>b. find Device size </li></ul><ul><li>c. find Last address </li></ul><ul><li>2. Determine the total of address line for every device that go directly to memory </li></ul><ul><li>a. find the total of address line in the device </li></ul><ul><li>b. low address line from the µP go directly to the memory. </li></ul><ul><li>3. Use the decoder to activated one device at a time by referring on the address line balance & total of device </li></ul>
  23. 23. Partial Address Decoder <ul><li>Example 3.3: Designing partial decoder </li></ul><ul><li>RAM : start address $400000, 64k word ( 128k byte ) </li></ul><ul><li>ROM : start address $000000, 16k word ( 32k byte ) </li></ul><ul><li>I/O : address $800000-$80001F </li></ul><ul><li>Steps: </li></ul><ul><li>RAM : $400000 ~ $41FFFF ($400000 + 128k –1) </li></ul><ul><li>ROM : $000000 ~ $007FFF ($000000 + 32k – 1) </li></ul><ul><li>I/O : $800000 ~ $ 80001F </li></ul><ul><li>Place X in the address table </li></ul><ul><li>RAM: A0 –A 16 directly to device </li></ul><ul><li>ROM: A0 – A 14 directly to device </li></ul><ul><li>I/O :A0 –A 4 directly to device </li></ul>Cont…
  24. 24. Partial Address Decoder <ul><li>Choose minimum address line: A23 & A22 </li></ul>Cont…
  25. 25. Partial Address Decoder <ul><li>Design using ½ 74LS139 </li></ul>Cont…
  26. 26. Partial Address Decoder <ul><li>Design using full 74LS139 </li></ul>Cont…
  27. 27. Generating <ul><li>Data transfer acknowledge </li></ul><ul><li>A signal that tells the 68K CPU data may be read from or written into memory </li></ul><ul><li>Synchronize memory access time </li></ul>
  28. 28. Generating <ul><li>Example 3.4: </li></ul><ul><li>A typical RAM might require 100ns to become active after it gets enabled. This due to the time required by the internal RAM circuitry to correctly decode the supplied address and turn on its internal buffers. This 100ns access time must fits within the time frame of the memory read or writes cycle, or else problems such as data loss might arise. So is needed. </li></ul>Cont…
  29. 29. Direct Memory Access (DMA) <ul><li>A process where external device requests the use of the CPU’s buses (address bus, data bus & control bus) for its own use </li></ul><ul><li>Video pattern generator (external) shares video RAM with CPU & high-speed data transfer circuits such as those used in hard disk. </li></ul>
  30. 30. Direct Memory Access (DMA) Cont…
  31. 31. Direct Memory Access (DMA) Cont…
  32. 32. Direct Memory Access (DMA) <ul><li>Example 3.5: </li></ul><ul><li>Recall that a memory-read cycle requires a minimum of eight states (four CLK cycles) to read a word from memory. If 1,024 reads are performed, a total of 4,096 CLK cycles are needed. A DMA controller is able to read memory faster, since it uses a different type of bus cycle to access memory. Let us assume that we are using a DMA controller that is capable of reading memory every two CLK cycles (once it controls the buses). Now, suppose that the DMA controller has been programmed to read the same 1,024 locations, in bursts of 128 words. Each burst will use 256 CLK cycles, plus some additional CLK cycles for controller overhead, such as bus request/grant protocol. With 16 CLK cycles of overhead, each burst requires 212 CLK cycles. The total number of CLK cycles required for the 1,024-word block is 2,116, a little more than half that required by the 68000 itself. Thus, a DMA controller can be very useful when large blocks of data must be transferred. </li></ul>Cont…
  33. 33. Memory-Mapped I/O <ul><li>A process to write into particular memory location & read later </li></ul><ul><li>Communicate with outside world </li></ul><ul><li>Also known as memory-mapped I/O port </li></ul>
  34. 34. Memory-Mapped I/O <ul><li>Example 3.6: </li></ul><ul><li>Imagine that you have a keyboard that supplies an 8-bit ASCII code (complete with parity) whenever you press a key. Your job is to somehow get this parallel information into your computer. By using memory-mapped I/O, a memory location may be set aside that, when read, will contain the 8-bit code generated by the keyboard. Conversely, data may be sent to the outside world by writing to a memory-mapped output location. </li></ul>Cont…
  35. 35. Memory-Mapped I/O Cont…
  36. 36. Parallel Data Transfer: 6821 PIA
  37. 37. Serial Data Transfer: 6850 ACIA

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