FIGURE 5.1 Double-conversion FM receiver block diagram Basically - - - > similar to AM receivers Double-Conversion Superheterodyne FM Receivers
Prevent mixer saturation when strong RF signals are received 8) AGC Remove info signal from FM wave 7) Detector/demodulator Clipping amplitude varied (noise) 6) Limiter Provide gain & sensitivity 5) IF Amplifier Down converts 1 st IF to 2 nd IF * Normally 2 nd IF low - - > 455 KHz 4) 2 nd mixer/converter Down converts RF to 1 st IF * Normally 1 st IF high - - > 10.7 MHz 3) 1 st mixer/converter Establish SNR & NF 2) RF Amplifier Reject f image 1) Preselector Main Function Main Stage / Block
C c , C 1 & C 2 are chosen so that short circuits for the IF centre frequency
IF signal is fed directly (in phase) across L3 via center tapping of T1
- - - > IF voltage, V p appears directly across L3 with no phase inversion
V p ∠ θ o <= = > V L3 ∠ θ o
Incoming IF signal is inverted 180 o by T1 and divided equally between V La & V Lb V La ∠ θ o <= = > V Lb ∠ θ o + 180 o
Vs (secondary winding of T1, V La + V Lb ) have 180 o phase inversion
with Vp because characteristic of centre tapping of T1
Vp ∠ θ o <= = > Vs∠ θ o + 180 o
Both tuned exactly to the IF centre frequency V p V s V La V Lb
6. Is (secondary winding T1) always have 90 o phase inversion with V La & V LB Is ∠ θ o <= = > VLb ∠ θ o ± 90 o & VLb ∠ θ o ± 90 o 7. V D1 is the vector sum of V L3 & V La V D2 is the vector sum of V L3 & V Lb Previously, know that V L3 is fed directly by Vin - - - > same phase & value. 8. If input frequency ( f in ) same with resonant freq of the secondary tank circuit (IF centre freq), I s is in the phase with total secondary voltage (V s ) : f in = f o (IF centre frequency) : C 1 & C 2 charge to equal magnitude voltage but opposite polarities : V D1 & V D2 will have equal voltages : V out = V C1 - V C2 = 0 The phase relation can be represented as Figure 5.5 (b) 9. If IF goes above resonance (X L > X C ), tank circuit impedance become inductive & I s lags the V s by some angle, θ ’ o which is proportional to the magnitude of the ∆ f : f in > f o (incoming IF signal freq > IF centre freq) : C 1 charges & C 2 discharges : V D1 > V D2 (sum vector of V D1 > sum vector of V D2 ) : V out = V C1 – V C2 = +ve value The phase relation can be represented as Figure 5.5 (c) V La V Lb Is V D2 V La V Lb Vin V D1 V s I s Θ ’ o
Advantage : relatively immune to amplitude variations in its input signal.
Figure 5.7 shows the schematic diagram for a ratio detector.
Same as the Foster-Seeley discriminator but with 3 limiting changes.
D 2 has been reversed current (I d ) flow through the outermost loop of the circuit
Shunt capacitor, C s charges to approximately the peak voltage across the secondary winding of T 1 . The reactance of C s is low, and R s simply provides a dc path for diode current.
Therefore, the time constant for R s and C s is sufficiently long so that rapid changes in the amplitude of the input signal due to thermal noise or other interfering signals are shorted to ground and have no effect on the average voltage across C s .
Consequently, C 1 and C 2 charge and discharge proportional to frequency changes in the input signal and are relatively immune to amplitude variations.
Also, the output voltage from a ratio detector is taken with respect to ground, and for the diode polarities shown in Figure 5.7(a), the average output voltage is positive.
At resonance, the output voltage is divided equally between C 1 and C 2 and redistributed as the input frequency is deviated above and below resonance.
Therefore, changes in Vout are due to the changing ratio of the voltage across C 1 and C 2 , while the total voltage is clamped by C s .
Figure 5.7(b) shows the output frequency response curve for the ratio detector shown in Figure 5.7(a). It can be seen that at resonance, Vout is not equal to 0 V but, rather, to one-half of the voltage across the secondary windings of T 1 . Because a ratio detector is relatively immune to amplitude variations, it is often selected over a discriminator.
However, a discriminator produces a more linear output voltage-versus-frequency response curve.
If the IF amplitude is sufficiently limited prior to reaching the PLL and the loop is properly compensated, the PLL loop gain is constant and equal to K V .
after frequency lock had occurred the VCO would track frequency changes in the input signal by maintaining a phase error at the input of the phase comparator.
Therefore, if the PLL input is a deviated FM signal and the VCO natural frequency is equal to the IF center frequency, the correction voltage produced at the output of the phase comparator and fed back to the input of the VCO is proportional to the frequency deviation and is, thus, the demodulated information signal.
Therefore, the demodulated signal can be taken directly from the output of the internal buffer and is mathematically given as
Figure 5.8(b) shows a schematic diagram for an FM demodulator using the XR-2212. R 0 and C 0 are course adjustments for setting the VCO's free-running frequency. R x is for fine tuning, and RF and R c set the internal op-amp voltage gain (K a ). The PLL closed-loop frequency response should be compensated to allow un-attenuated demodulation of the entire information signal bandwidth.
The PLL op-amp provides voltage gain and current drive stability
PLL is the best frequency demodulator, because the filtering circuit removes noise and interference and its linear output reproduce the output signal
Figure 5.8 (b) PLL FM demodulator using the XR-2212 PLL
All new FM broadcast receivers are being built with provision for receiving stereo, or two-channel broadcasts.
The left (L) and right (R) channel signals from the program material are combined to form two different signals, one of which is the left-plus-right signal and one of which is the left-minus-right signal
The (L - R) signal is double-sideband suppressed carrier (DSBSC) modulated about a carrier frequency of 38 kHz, with the LSB in the 23- to 38-kHz slot and the USB in the 38- to 53-kHz slot. The (L + R) signal is placed directly in the 0- to 15-kHz slot, and a pilot carrier at 19 kHz is added to synchronize the demodulator at the receiver.
The output from the FM detector is a composite audio signal containing the frequency-multiplexed (L + R) and (L - R) signals and the 19-kHz pilot tone. This composite signal is applied directly to the input of the decode matrix.
The composite audio signal is also applied to one input of a phase-error detector circuit, which is part of a phase locked loop 38-kHz oscillator.
The output drives the 38-kHz voltage-controlled oscillator, whose output provides the synchronous carrier for the demodulator.
The oscillator output is also frequency divided by 2 (in a counter circuit) and applied to the other input of the phase comparator to close the phase locked loop.
The phase-error signal is also passed to a Schmitt trigger circuit, which drives an indicator lamp on the panel that lights when the error signal goes to zero, indicating the presence of a synchronizing input signal (the 19-kHz pilot tone).
The outputs from the 38-kHz oscillator and the filtered composite audio signals are applied to the balanced demodulator, whose output is the (L - R) channel.
The ( L + R) and (L - R) signals are passed through a matrix circuit that separates the L and R signals from each other. These are passed through de-emphasis networks and low-pass filters to remove unwanted high-frequency components and are then passed to the two channel audio amplifiers and speakers.
On reception of a monaural signal, the pilot-tone indicator circuit goes off, indicating the absence of pilot tone, and closes the switch to disable the (L - R) input to the matrix.
The (L + R) signal is passed through the matrix to both outputs. An ordinary monaural receiver tuned to a stereo signal would produce only the (L + R) signal, since all frequencies above 15 kHz are removed by filtering, and no demodulator circuitry is present.
Thus the stereo signal is compatible with the monaural receivers.