PhD Defense: Operation of SiGe HBTs in Extreme Environments

Operation of SiGe HBTsonSOI in Extreme Environments Ph.D. Defense Exam By: Marco Bellini Defense Committee: Dr. ShyhChiang Shen, Chair Dr. John D. Cressler, Advisor Dr. John Papapolymerou Dr. Stephen Ralph Dr. Hao Min Zhou February 26th, 2009 School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, GA 30332, USA Marco Bellini, 2/26/09 1

Outline ● Introduction of Bulk HBTs and HBTsonSOI ● Extreme Environments ● Contributions: high temperatures cryogenic temperatures radiation ● Proposed Research ● Conclusions Marco Bellini, 2/26/09 2

Contributions ● Developed a new technique to optimize device speed Electrochemical Society Symposium, vol. 16, pp. 10791088, 2008. ● First low and highT studies of SiGe HBTsonSOI IEEE WOLTE 2006, vol. WPP264, pp. 8792, 2006. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 14, 2006. ● First analysis of 1/f noise in inverse mode SPIE 2007 Fluctuation and Noise Conference, pp. H1H9, 2007. ● Explained resistance to “Mixed Mode” electrical stress IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 234237, 2007. ● Compared radiation response of thick and thinfilm SOI IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 31823186, 2006. IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 22452250, 2007. ● Understood layout impact on charge collection IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 31973201, 2008. ● First analysis of effects of radiation on thermal resistance IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 31973201, 2008. Marco Bellini, 2/26/09 3

Bulk SiGe HBTs • Bandgap Engineering Improves DC and AC Performance • Superb Cryogenic Performance and TID Hardness • Thick, High NC Subcollector (3 µ m, 1019 cm3) Reduces RC B B E C E EC Subcollector C EV Ge Substrate pSi Marco Bellini, 2/26/09 11

Bulk HBTs vs SOI HBTs • Compatibility with SOI CMOS and Reduction of Parasitics • Elimination of Substrate Leakage (HighT Latchup) • Decreased Vulnerability to Single Event Upset B E C Subcollector (3 µ m) 0.12 µ m Substrate 0.14 µ m ~ 3 µ m thick subcollector 0.12 µ m SiliconOnInsulator (SOI) layer NSUB ~ 1019 cm3 Marco Bellini, 2/26/09 NC ~ 1017 cm3 11

Why SiGe HBTonSOI? • Advantages of SiGe HBTs: better β , VA, fT, fmax, NFmin than Si BJTs high output resistance and transconductance per unit area excellent cryogenic performance easy integration with CMOS technology + • Advantages of SOI CMOS: reduction of device parasitics elimination of substrate leakage (latchup immunity at highT) decreased vulnerability to SEU? (Achilles’ Heel of bulk SiGe)  Builtin Radiation Hardness (TID and SEU) Marco Bellini, 2/26/09 6

Why SiGe HBTonSOI? • Evolution of Si Bipolar Devices : Emitter: Polysilicon Base: SiGe Collector: SOI Hitachi IBM IBM Marco Bellini, 2/26/09 7

Why SiGe HBTonSOI? • Evolution of Si Bipolar Devices : Emitter: Polysilicon Base: SiGe Collector: SOI Hitachi IBM IBM Marco Bellini, 2/26/09 4

Bulk and SOI Devices Bulk ThickFilm ThinFilm Subcollector Subcollector Substrate IBM TI IBM Comparable npn technology npn + pnp npn only ~ 3 µ m thick subcollector 1.5 µ m SOI Layer with 0.12 µ m SOI Layer subcollector NSUB ~ 1019 cm3 0.145 µ m BOX 0.14 µ m BOX IEEE TNS v.54, n.6, pp.2245, 2007 Marco Bellini, 2/26/09 5

HBT on ThinFilm SOI • Fabricated by IBM (Compatible with 130 nm SOI CMOS) • Fully and Partially Depleted Versions F.O.M. (300K) β 1200 V A 400 V fT at 30 VS = 0V GHz fmax at 45 ↨ 120 nm VS =0V GHz ↨ 140 nm BVCE0 4.8 V BVCB0 13 V Marco Bellini, 2/26/09 VS 6

Extreme Environments • Cryogenic Temperatures ( down to 77 K or even 4 K ) • High Temperatures ( up to 300 °C ) • Radiation ( Total Ionizing Dose AND SEU ) Drilling Moon / Mars Aerospace Cars Marco Bellini, 2/26/09 7

TCAD Simulation • Numerical Simulations Solve Semiconductor Equations over a Finite Element Grid • Calibrated Simulations Estimate Local Physical Quantities (Potential, Carrier Concentration, Currents…) EB oxide ∇ ⋅ ε∇ φ = − q( p − n + N D − N A ) − ρ traps E B  ∂n ∇ ⋅ J n = qRnet + q SiGe ∂t  ∂p − ∇ ⋅ J p = qRnet + q ∂t   STI ∂n J n = qnµ n E + qDn oxide ∂x   ∂p J p = qnµ p E − qDn ∂x C Marco Bellini, 2/26/09 11

TCAD Simulations S Marco Bellini, 2/26/09 9

TCAD Simulations Marco Bellini, 2/26/09 9

TCAD Simulations n Marco Bellini, 2/26/09 9

Substrate Effect (JN) Jn VCB = 0 V VS  SOI BOX n Marco Bellini, 2/26/09 10

Substrate Effect (JN) Jn VCB = 0 V SOI BOX The e accumulation layer creates a low resistivity n path ● lower RC ● higher fT, fmax Marco Bellini, 2/26/09 10

Substrate Effect (JN) Chen, T.; Bellini, M.; Zhao, E.; Comeau, J.P.; Sutton, A.K.; Grens, C.M.; Cressler, J.D.; Jin Cai; Ning, T.H., Proc of IEEE BCTM, 2005, pp. 256259, 911 Marco Bellini, 2/26/09 11

Multiplication Factor (M1) • At High VCB, E Causes Carrier Multiplication and IB Inversion • M1 Depends from the Doping, Current Flow and Electric Field In,E E B In,IN E In,IN C Ip,E Ip,E (M1) In,IN (M1) In,IN Marco Bellini, 2/26/09 11

Multiplication Factor (M1) • M1 is Calculated as Excess Current at Forced IE • For Bulk Devices, M1 has Characteristic “Round” Shape VCB IE IC M −1 = −1 IE − IB V Marco Bellini, 2/26/09 CB = 0 11

Electric Field (M1) VBE = 0 V VCB  n Marco Bellini, 2/26/09 12

Electric Field (M1) VBE = 0 V VCB depletes the collector n ● M1 saturation at VS = 0 V Marco Bellini, 2/26/09 12

Electric Field (M1) VBE = 0 V VCB depletes the collector VS shifts the peak of the n Electric Field ● M1 saturation at VS = 0 V ● M1 increase with VS Marco Bellini, 2/26/09 12

Electric Field (M1) VS = 20 V VS = 0 V Chen, T.; Bellini, M.; Zhao, E.; Comeau, J.P.; Sutton, A.K.; Grens, C.M.; Cressler, J.D.; Jin Cai; Ning, T.H., Proc of IEEE BCTM, 2005, pp. 256259, 911 Bellini, M.; Chen, T.; Zhu, C.; Cressler, J.D. and Cai, J., Proc of IEEE BCTM, 2006 , pp.14, 810 Marco Bellini, 2/26/09 13

High Injection (fT) VCB = 2 V p VBE  n Marco Bellini, 2/26/09 14

High Injection (fT) VCB = 2 V p e injection in the depleted collector triggers HBE n ● HBE depends on NC Marco Bellini, 2/26/09 14

High Injection (fT) VCB = 2 V p e injection in the depleted collector triggers HBE VS reduces HBE n ● HBE depends on NC ● high VS improves fT, fmax Marco Bellini, 2/26/09 14

High Injection (fT) VS 63 MeV protons Chen, T; Sutton, A.K.; Bellini, M.; Haugerud, B.M.; Comeau, J.P.; Liang, Q.; Cressler, J.D.; Jin Cai; Ning, T.H.; Marshall, P.W.; Marshall, C.J., IEEE TNS, vol.52, no.6, pp. 23532357, Dec. 2005 Bellini, M.; Chen, T.; Zhu, C.; Cressler, J.D. and Cai, J., Proc of IEEE BCTM, 2006 , pp.14, 810 Marco Bellini, 2/26/09 15

HighT • DC and AC Performance • 1/f Noise • Impact Ionization Marco Bellini, 2/26/09 16

High Temperature • Increased SelfHeating Due to RTH at High VBE • Larger Amount of Base Leakage at HighT T Bellini, M.; Cressler, J.D.; Jin Cai, Proc. of IEEE BCTM, 2007, pp.234237 Marco Bellini, 2/26/09 17

Current Gain and AC • Peak Current Gain Region Not Affected by SelfHeating • AC and DC Performance Still Acceptable Even at HighT T Marco Bellini, 2/26/09 18

Inverse Mode 1/f Noise • IB (vs. IB2 ) Dependence Due to SCR G/R Recombination • 1/f Tdependence Affected by Leakage Current Behavior µ n Bellini, M.; Cheng, P., Appaswamy, A.; Cressler, J. D. and Cai, J. 2007 SPIE F&N, Italy 2007 Marco Bellini, 2/26/09 20

Inverse Mode 1/f Noise • IB (vs. IB2 ) Dependence Due to SCR G/R Recombination • 1/f Tdependence Affected by Leakage Current Behavior T µ n Bellini, M.; Cheng, P., Appaswamy, A.; Cressler, J. D. and Cai, J. 2007 SPIE F&N, Italy 2007 Marco Bellini, 2/26/09 20

Avalanche Multiplication • SOI Device Similar to Bulk at High Substrate Voltage • TCAD Simulations Confirm Increase of Substrate Effect TCAD Simulation Accumulation Layer Marco Bellini, 2/26/09 21

CryoT • Reliability at 300 K and 77 K Marco Bellini, 2/26/09 23

Accelerated Stressing • MixedMode Stress: simultaneous high current (JE) and high voltage (VCB) stress applied (circuit relevant) Bellini, M et al., Proc of IEEE BCTM, 2006 , pp.14, 810 Marco Bellini, 2/26/09 26

Reliability (300 K & 77 K) • Presence of Significant Recovery Effects during Stress • Possible Bond Breaking + Repassivation Mechanism MixedMode TCAD Marco Bellini, 2/26/09 27

Device Optimization • 3D Regional Transit Time Analysis Marco Bellini, 2/26/09 28

CBEBC Layout • 150 nm ThinFilm SOI Requires Depleted Collector Design • LC Distance Limits AC Performance CBEBC Layout 400 nm150 nm Marco Bellini, 2/26/09 50

CBEBC Layout • 150 nm ThinFilm SOI Requires Depleted Collector Design • LC Distance Limits AC Performance CBEBC Layout 400 nm150 nm Marco Bellini, 2/26/09 51

3D Current Flow • Substrate Bias Shifts Current Flow Towards SOI/BOX • 3D TCAD Shows Lateral Extension of Electron Layer Marco Bellini, 2/26/09

1D Transit Time Analysis • 1D Grid is Easily Integrated and Accurate for Bulk Devices • Base Voltage Perturbation Alters the Electron Density n E B C Marco Bellini, 2/26/09 9

1D Transit Time Analysis • 1D Grid is Easily Integrated and Accurate for Bulk Devices • Base Voltage Perturbation Alters the Electron Density n E B Line ∆ n C Marco Bellini, 2/26/09 10

3D Transit Time Analysis • 3D Transit Time Analysis Needs 3D Integration Techniques • Can Accurately Model SOI Devices with CBEBC Layout Volume ∆ n Marco Bellini, 2/26/09 10

3D Transit Time Analysis • fT Calculated from Integration Over the 3D Device • Much Faster than AC Simulation But Cannot Estimate fmax Marco Bellini, 2/26/09 12

Regional Analysis • Highlights Regional Contributions to Transit Time • Tremendous Opportunity for Device Optimization Marco Bellini, 2/26/09

Accumulated Transit Time • In 1D, Analysis the Entire Grid is the (Only) Streamline • In 3D, Transit Time Is Integrated Along Multiple Streamlines from Emitter to Collector Marco Bellini, 2/26/09

Accumulated Transit Time • In 1D, Analysis the Entire Grid is the (Only) Streamline • In 3D, Transit Time Is Integrated Along Multiple Streamlines from Emitter to Collector Σ Marco Bellini, 2/26/09

Accumulated Transit Time • Can Be Used for Optimization in Extreme Environments • Impact of EB, CB SCR and Transition to Neutral Collector Bellini, M et al., ECS Trans, 2008, vol.16, pp. 10791088 Waikiki, HI Marco Bellini, 2/26/09 14

Radiation • Gain Degradation • Substrate Effect on Inverse Gummel and CBC • Thermal Resistance • Impact of Layout on Single Event Upset Marco Bellini, 2/26/09 28

Proton DC Response • SOI and Bulk Devices Have Identical EB Structure • No degradation Introduced by SOI (expected) Inverse Bulk SOI Forwardmode Marco Bellini, 2/26/09 75

Substrate Effect • VS Reduces PostIrradiation Leakage in Inverse Mode • TCAD Shows Current Flowing Away from Si/SiO2 Interface Marco Bellini, 2/26/09 76

Thermal Resistance • RTH of HBTonSOI Increases with VS and Radiation • TCAD Shows Local Heating at SOI/BOX Interface Marco Bellini, 2/26/09 Bellini, M et al., Nuclear Science, IEEE Transactions on , vol.55, no.6, pp.31973201, Dec. 2007 77

Thermal Resistance • RTH of HBTonSOI Increases with VS and Radiation • TCAD Shows Local Heating at SOI/BOX Interface Marco Bellini, 2/26/09 Bellini, M et al., Nuclear Science, IEEE Transactions on , vol.55, no.6, pp.31973201, Dec. 2007 78

Single Event Upset • CollectorSubstrate Junction Aids Charge Collection • SOI Effectively Shuts Down the Charge Collection Path heavy ion SOI Marco Bellini, 2/26/09 J. Pellish et al., NSREC 06 34

Single Event Upset • Fully Calibrated 3D TCAD Simulation of Strike in E Center • The Collector Current Changes Sign During the Transient Emitter Center Strike Marco Bellini, 2/26/09 80

Marco Bellini, 2/26/09 81

Single Event Upset • Ion Strike Location Between Emitter and Base • Different Current Pulse Shape Due to Layout and Doping Bellini, M et al., Nuclear Science, IEEE Transactions on , vol.55, no.6, pp.31973201, Dec. 2007 Marco Bellini, 2/26/09 85

Summary ● Developed a new technique to optimize device speed Electrochemical Society Symposium, vol. 16, pp. 10791088, 2008. ● First low and highT studies of SiGe HBTsonSOI IEEE WOLTE 2006, vol. WPP264, pp. 8792, 2006. IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 14, 2006. ● First analysis of 1/f noise in inverse mode SPIE 2007 Fluctuation and Noise Conference, pp. H1H9, 2007. ● Explained resistance to “Mixed Mode” electrical stress IEEE Bipolar/BiCMOS Circuits and Technology Meeting, pp. 234237, 2007. ● Compared radiation response of thick and thinfilm SOI IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 31823186, 2006. IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 22452250, 2007. ● Understood layout impact on charge collection IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 31973201, 2008. ● First analysis of effects of radiation on thermal resistance IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 31973201, 2008. Marco Bellini, 2/26/09 86

Contributions Journal Papers [1] Bellini, M.; Phillips, S. D.; Diestelhorst, R. M.; Cheng, P.; Cressler, J. D.; Marshall, P. W.; Turowski, M.; Avenier, G.; Chantre, A.; and Chevalier, P., “Novel Total Dose and HeavyIon Charge Collection Phenomena in a New SiGe HBT on ThinFilm SOI Technology”, Nuclear Science, IEEE Transactions on , vol.55, no.6, pp.31973201, Dec. 2007 [2] Bellini, M.; Jun, B.; Sutton, A. K.; Appaswamy, A. C.; Cheng, P.; Cressler, J. D.; Marshall, P. W.; Schrimpf, R. D.; Fleetwood, D. M.; ElKareh, B.; Balster, S.; Steinmann, P.; Yasuda, H., "The Effects of Proton and XRay Irradiation on the DC and AC Performance of Complementary (npn + pnp) SiGe HBTs on ThickFilm SOI," Nuclear Science, IEEE Transactions on , vol.54, no.6, pp.22452250, Dec. 2007 [3] Bellini, M.; Jun, B.; Chen, T.; Cressler, J. D.; Marshall, P. W.; Chen, D.; Schrimpf, R. D.; Fleetwood, D. M.; Cai, J., "XRay Irradiation and Bias Effects in FullyDepleted and PartiallyDepleted SiGe HBTs Fabricated on CMOSCompatible SOI," Nuclear Science, IEEE Transactions on , vol.53, no.6, pp.31823186, Dec. 2006 [4] Appaswamy, A.; Bellini, M.; WeiMin Lance Kuo; Peng Cheng; Jiahui Yuan; Chendong Zhu; Cressler, J.D.; Guofu Niu; Joseph, A.J., "Impact of Scaling on the InverseMode Operation of SiGe HBTs," Electron Devices, IEEE Transactions on , vol.54, no.6, pp.14921501, June 2007 [5] Sutton, A.K.; Bellini, M.; Cressler, J.D.; Pellish, J.A.; Reed, R.A.; Marshall, P.W.; Guofu Niu; Vizkelethy, G.; Turowski, M.; Raman, A., "An Evaluation of TransistorLayout RHBD Techniques for SEE Mitigation in SiGe HBTs," Nuclear Science, IEEE Transactions on , vol.54, no.6, pp.20442052, Dec. 2007 [6] Najafizadeh, L.; Sutton, A.K.; Diestelhorst, R.M.; Bellini, M.; Bongim Jun; Cressler, J.D.; Marshall, P.W.; Marshall, C.J., "A Comparison of the Effects of XRay and Proton Irradiation on the Performance of SiGe Precision Voltage References," Nuclear Science, IEEE Transactions on , vol.54, no.6, pp.22382244, Dec. 2007 [7] Sutton, A. K.; Gnana Prakash, A. P.; Jun, B.; Zhao, E.; Bellini, M.; Pellish, J.; Diestelhorst, R. M.; Carts, M. A.; Phan, A.; Ladbury, R.; Cressler, J. D.; Marshall, P. W.; Marshall, C. J.; Reed, R. A.; Schrimpf, R. D.; Fleetwood, D. M., "An Investigation of Dose Rate and Source Dependent Effects in 200 GHz SiGe HBTs," Nuclear Science, IEEE Transactions on , vol.53, no.6, pp.31663174, Dec. 2006 [8] Jun, B.; Diestelhorst, R. M.; Bellini, M.; Espinel, G.; Appaswamy, A.; Prakash, A. P. G.; Cressler, J. D.; Chen, D.; Schrimpf, R. D.; Fleetwood, D. M.; Turowski, M.; Raman, A., "TemperatureDependence of OffState Drain Leakage in XRay Irradiated 130 nm CMOS Devices," Nuclear Science, IEEE Transactions on , vol.53, no.6, pp.32033209, Dec. 2006 [9] Najafizadeh, L.; Bellini, M.; Prakash, A. P. G.; Espinel, G. A.; Cressler, J. D.; Marshall, P. W.; Marshall, C. J., "Proton Tolerance of SiGe Precision Voltage References for Extreme Temperature Range Electronics," Nuclear Science, IEEE Transactions on , vol.53, no.6, pp.32103216, Dec. 2006 [10] Chen, T; Sutton, A.K.; Bellini, M.; Haugerud, B.M.; Comeau, J.P.; Qingqing Liang; Cressler, J.D.; Jin Cai; Ning, T.H.; Marshall, P.W.; Marshall, C.J., "Proton radiation effects in vertical SiGe HBTs fabricated on CMOScompatible SOI," Nuclear Science, IEEE Transactions on , vol.52, no.6, pp. 23532357, Dec. 2005 Marco Bellini, 2/26/09 40

Contributions Conference Papers [1] Bellini, M.; Cressler, J.D.; Turowski, M.; Avenier, G.; Chantre, A. and Chevalier, P. “3D Regional Transit Time Analysis of SiGe HBTs on ThinFilm SOI”, ECS Trans, 2008, vol.16, pp. 10791088 Waikiki, HI [2] Bellini, M.; Phillips, S. D.; Diestelhorst, R. M.; Cheng, P.; Cressler, J. D.; Marshall, P. W.; Turowski, M.; Avenier, G.; Chantre, A.; and Chevalier, P., “Novel Total Dose and HeavyIon Charge Collection Phenomena in a New SiGe HBT on ThinFilm SOI Technology”, presented at IEEE NSREC 2008, Tucson, AZ [2] Bellini, M.; Cressler, J.D.; Jin Cai, "Assessing the HighTemperature Capabilities of SiGe HBTs Fabricated on CMOS compatible Thinfilm SOI," Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE , pp.234237, Sept. 30 2007 Oct. 2 2007 [4] Bellini, M.; Jun, B.; Sutton, A. K.; Appaswamy, A. C.; Cheng, P.; Cressler, J. D.; Marshall, P. W.; Schrimpf, R. D.; Fleetwood, D. M.; ElKareh, B.; Balster, S.; Steinmann, P.; Yasuda, H., "The Effects of Proton and XRay Irradiation on the DC and AC Performance of Complementary (npn + pnp) SiGe HBTs on ThickFilm SOI," presented at IEEE NSREC 2006, Ponte Vedra, FL. [5] Bellini, M.; Jun, B.; Chen, T.; Cressler, J. D.; Marshall, P. W.; Chen, D.; Schrimpf, R. D.; Fleetwood, D. M.; Cai, J., "XRay Irradiation and Bias Effects in FullyDepleted and PartiallyDepleted SiGe HBTs Fabricated on CMOSCompatible SOI," presented at IEEE NSREC 2007, Waikiki, HI [6] Bellini, M.; Cheng, P., Appaswamy, A.; Cressler, J. D. and Cai, J. “1/f Noise in SiGe HBTs Fabricated on CMOSCompatible ThinFilm SOI”, presented at 2007 SPIE Fluctuation and Noise Conference, Italy 2007 [7] Bellini, M.; Chen, T.; Zhu, C.; Cressler, J.D. and Cai, J., "Reliability Issues in SiGe HBTs Fabricated on CMOSCompatible ThinFilm SOI," Bipolar/BiCMOS Circuits and Technology Meeting, 2006, pp.14, 810 Oct. 2006 [8] Bellini, M.; Chen, T.; Cressler, J. D. ,and Cai, J.; “Cryogenic Operation of SiGe HBTs on CMOScompatible ThinFilm SOI Substrates”, presented at the 7th European Workshop on Low Temperature Electronics, Noordwijk, The Netherlands, June, 2006 [9] Cheng, P.; Appaswamy, A.; Bellini, M.; Cressler, J. D., "Probing Hot Carrier Phenomena in npn and pnp SiGe HBTs," Silicon Monolithic Integrated Circuits in RF Systems, 2008. SiRF 2008. IEEE Topical Meeting on, pp.5457, 2325 Jan. 2008 [10] Kuo, W.M.L.; Appaswamy, A.; Krithivasan, R.; Bellini, M.; Cressler, J.D.; Freeman, G., "Reverse Active Operation of 200 GHz SiGe HBTs," Semiconductor Device Research Symposium, 2005 International, pp. 183184, Dec. 79, 2005 [11] Najafizadeh, L.; Bellini, M.; Espinel, G.and J. D. Cressler, "On the Cryogenic Operation of the SiGe Bandgap Voltage References", 7th European Workshop on Low Temperature Electronics, Noordwijk, The Netherlands, June, 2006 [12] Chen, T.; Bellini, M.; Zhao, E.; Comeau, J.P.; Sutton, A.K.; Grens, C.M.; Cressler, J.D.; Jin Cai; Ning, T.H., "Substrate bias effects in vertical SiGe HBTs fabricated on CMOScompatible thin film SOI," Bipolar/BiCMOS Circuits and Technology Meeting, 2005. Proceedings of the, pp. 256259, 911 Oct. 2005 Marco Bellini, 2/26/09 41

Acknowledgements • Defense Exam Committee Dr. Cressler (Advisor), Dr. Shen, Dr. Papapolymerou, Dr. Ralph, Dr. Zhou • IBM, Texas Instruments, STMicroelectronics • Fulbright IIE, D'Onofrio Fellowship Board • GEDC & Support Staff Dr. Scholz, DeeDee Bennett, Joi Adams, Tammy Scott, Chris Evans, help@ECE,… • SiGe Research Group Zhenrong, Qingqing, Akil, Becca, Mustayeen, Adnan, Curtis, Mustansir, Tianbing, Enhai, Jon, Lance, Ram, Chendong, Yuan, BB, Joel, Xingtao, Laleh, Aravind, Jiahui, Tushar, Tom, Steven, Ryan, Gus, Bongim, Prakash, Nand, Prabir, Anuj, Kurt, Stephen, Partha, Seth, John, JJ… • Family and Friends Marco Bellini, 2/26/09 42

Thank You! Marco Bellini, 2/26/09 43

PhD Defense: Operation of SiGe HBTs in Extreme Environments

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