Upcoming SlideShare
×

# Structured Electronics Assignment

421 views
330 views

Published on

0 Likes
Statistics
Notes
• Full Name
Comment goes here.

Are you sure you want to Yes No
• Be the first to comment

• Be the first to like this

Views
Total views
421
On SlideShare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
8
0
Likes
0
Embeds 0
No embeds

No notes for slide

### Structured Electronics Assignment

1. 1. STRUCTURED ELECTRONICS ASSIGNMENT 5MD30, Quartile 3, 2010 Mayur Sarode student id:0730085 1
2. 2. Contents A. General configuration ..................................................................................................................................... 4 1.1 Motivation of the choice of feedback ....................................................................................................... 4 1.2 Numerical value of the feedback configuration ........................................................................................ 5 1.3 Implementation of feedback configuration ............................................................................................... 5 1.4 Implementing the transfer function .......................................................................................................... 6 B. Noise Figure .................................................................................................................................................. 8 2.1 Derive the expressions for the CE and CS configurations .Explain the impact of collector and drain current, input impedance and the input internal resistor on the noise figure. ..................................................................... 8 2.1(a) Expression for the noise figure of the single ended common emitter stage ............................................... 8 2.3(a) Optimum noise figure as a function of Collector Current ......................................................................... 12 2.4(a) Calculate the numerical value of these configurations using the spice models A and B ........................... 12 2.1(b) Expression for the noise figure of the differential common emitter stage ................................................. 14 2.3 (b) Optimum noise figure as a function of Collector Current ........................................................................ 18 2.4 (b) Calculate the numerical value of these configurations using Spice models A and B ............................... 19 2.5(b) Simulate the transfer function for the differential BJT pair ...................................................................... 20 2.6 (a) Expression for Common source configuration for a JFET amplifier in single ended mode........................ 20 2.8(a) Optimum noise figure as a function of drain Current ............................................................................... 25 2.9(a) Calculate the numerical value of these configurations using the spice model A and B .............................. 25 2.10(a) Simulate the transfer function for single ended JFET ............................................................................. 27 2.6 (b) Expression for Common source configuration for a JFET amplifier in differential model ......................... 28 2.2(a)(b),2.7(a)(b) Compare the capabilities of the two technologies.................................................................. 33 2.8(b) Optimum noise figure as a function of drain Current ............................................................................... 32 2.9(b) Calculate the numerical value of these configurations using the spice model A and B ............................. 33 2.10(b) Simulate the transfer function .............................................................................................................. 35 2
3. 3. C: Feedback and noise ...................................................................................................................................... 364.1 Implement the first stage of the feedback configuration of assignment 1 by a JFET or a BJT differentialstage……………… ................................................................................................................................................. 364.2 Derive an expression of the noise figure for the total feedback system. Explain the impact of CollectorCurrent, input impedance and the internal input resistor on the noise figure. ................................................... 364.3 Calculate the numerical value of the feedback configuration ....................................................................... 414.4. Implement the feedback configuration in the simulator in use and simulate the transfer function ............. 414.5 Simulate the transfer function ..................................................................................................................... 42C. Last Stage .................................................................................................................................................... 436. Implement the Last stage in the configuration in A.1 by a CMOS or Bipolar ................................................. 437. Determine the collector or the drain current ................................................................................................... 43D. Open Loop gain ............................................................................................................................................ 454.1 Determine the voltage gain transfer function as a function of frequency. ...................................................... 464.2. Determine the positioning of the poles and zeros ........................................................................................ 464.3 Remove the ideal nullator and determine the open and closed loop function of the feedback .................. 49E. Closed loop gain5.1 Determine the transfer function and the noise figure of closed loop…………………………………………………………53F. Stability6.1 Check the stability of the system ................................................................................................................. 54 3
4. 4. Assignment 1: General Feedback ConfigurationA. General configurationIn this assignment we simulate a negative feedback amplifier circuit. The design of the circuit consists of two parts.1. Design of the amplifier using a nullor.2. Design of the feedback loop. Amplifier is an active component and is modeled by a nullor. Nullor is a combination of a norator and a nullator.A nullor is chosen as it has infinite voltage gain , current gain ,transconductance and transimpedance. The nullorcan be assumed to be an ideal amplifier. In ADS it is represented by a two port network (A B C D chain matrixselected from Equation based linear library). Due to high input impedance of an amplifier, values of the chainmatrix are either 0 or very small. The nullor adapts the output such a way that the input current and voltage is 0. Inour simulation we have kept the value ABCD parameters as e-10 .The specifications of the circuit are given in table 1 and table 2. The signal bandwidth is specified to between 50Hz to 1.5 MHz.1.1 Motivation of the choice of feedback From the source specification of the assignment, the input is a piezoelectric sensor which is specified by thecharge. Taking the output of the sensor over a period of time t , current can be measured. The specifications of theload indicate output is voltage. It can be inferred that we need to design a negative feedback topology having inputas current and output as voltage. The kind of topology is shown in figure and is called a shunt – shunt feedback.Negative feedback is chosen as the gain at the amplifier can be controlled. Although the gain of the amplifier isreduced, it improves the gain sensitivity, bandwidth and doesn’t improve the input noise of the circuit. The inputand output impedance of the circuit can be modified without affecting the gain of the circuit. Negative feedbackreduces output signal clipping. 4
5. 5. Figure 1.1 Choice of feedback1.2 Numerical value of the feedback configuration The asymptotic gain of the chosen amplifier configuration is given by Vl Zs Is Vl 0.5volts Is 100 pC 0.5 1 1 Zs 12 nF 100*10 Cf The impedance in the feedback configuration is a capacitance of 1nF value.1.3 Implementation of feedback configuration Figure 1.2: ADS simulation of feedback circuit with nullor In ADS the piezoelectric current source is represented by a frequency dependent sinusoidal A.C current source .The amplitude of the sinusoidal current source varies with frequency given by the equation. polar (2 freq * I s , / 2) 5
6. 6. The AC frequency is sweeped from 10 Hz to 1.5 MHz in step of 10 Hz to plot the transfer function and the output voltage.1.4 Implementing the transfer function Figure 1.3: the transfer function simulated in ADS is given by which is the measure of gain of feedback the circuitThe transfer function simulated in Fig. 1.3 is given below which is the measure of gain of feedback the circuit. Vl Zin 10 log( ) IsThus the circuit is within the maximum gain limits specified (SNR 70 dBm) in the assignment. The gain varies withfrequency because the transfer function of capacitance is dependent on the frequency of the input signal.The second transfer function simulated is the variation of the output voltage with the sweep frequency of theamplifier as shown in Fig 1.4. It can be inferred that the output voltage is independent of frequency. Thus theamplifier is working in the linear region. 6
7. 7. Figure 1.4 Magnitude of output voltage 7
8. 8. Assignment 2: Noise FigureB. Noise Figure2.1 Derive the expressions for the CE and CS configurations .Explain the impact of collector anddrain current, input impedance and the input internal resistor on the noise figure.2.1(a) Expression for the noise figure of the single ended common emitter stageThe noise model of the single ended common emitter BJT is as shown below Figure 2.1 small signal noise model of a BJTic and ib are shot noise currents and vnb is the noise voltage due to the base resistance. ibf is the flicker noise current.It is too small to be significant, hence we can ignore it. We need to bring the noise current source ic the input side.After the network transformation, the noise model looks as follows. Vnb BIc Rb Ib DIc Figure 2.2 small signal noise model of a BJT with the collector noise transformed to input 8
9. 9. The values of the above noise sources are as followsFor the BJT, B = Vt/Ic and D = 1/Beta. The noise course Dic can be neglected since the value of D is very smalldue to the large value of Beta. After neglecting Dic, the remaining noise sources are un-correlated. Thus we need toadd their power spectral densities. The PSD of the noise sources are written as follows. Vnb2 = 4KTRb ib2 = 2qIb (B*ic)2 = B2*2qIc Vs2 = 4KTRsIf we transform the current source ib to a voltage source by Norton-thevenin transform, the value of the voltagesource is (Rs + Rb)*2qIbThe expression for Noise Figure is written as follows.NF = 10*log10(1 + (NoiseDUT / Noisein))NoiseDUT = 4KTRb + B2*2qIc + (Rs + Rb)2qIbSimplifying and substituting the constants, we getNoiseDUT =4KTRb + 2q(Vt)2/Ic + (Rs + Rb)2*(1/Beta)*2qIcNoisein = 4KTRsThus the final expression for the noise figure isNF = 10log10(1 + (4KTRs + 4KTRb + 2q(Vt)2/Ic + (Rs + Rb)2*(1/Beta)*2qIc) / 4KTRs)The above equation is simulated in MATLAB and compared with the curve obtained in ADS. 9
10. 10. Figure 2.3 variation of noise figure with the collector current simulated in ADS Figure 2.4 variation of noise figure with the collector current simulated in MATLABThe noise figure depends on three variables namely, collector current, base resistance and the internal sourceresistance. The relation to the collector is apparent from the above figures. Initially the noise figure falls as afunction of the collector bias current. For the particular value of the collector bias current, the noise figure is lowest. 10
11. 11. After this point, the noise figure increases as a function of the collector bias current. The point where the noisefigure is lowest is point of optimum collector bias current. Note that, optimum collector current for noise figuredoes not guarantee best gain.The relation of NF with the input base resistance is shown in the following graph. Figure 2.5 variation of noise figure with the base resistance simulated in MATLABThe Noise Figure increases non-linearly with the input base resistance.. Figure 2.6 variation of noise figure with source resistance simulated in MATLAB 11
12. 12. The relation of the noise figure to the internal source resistance is exponential.2.3(a) Optimum noise figure as a function of Collector CurrentReiterating the expression for the noise figure, we can see its dependence on the collector bias current.NF = 10log10(1 + (4KTRb + 2q(Vt)2/Ic + (Rs + Rb)2*(1/Beta)*2qIc) / 4KTRs)If we keep the source and the internal base resistance constant, we can differentiate the above equation with respectto the collector bias current. To obtain a minima for the NF curve, we equate the slope to zero. Thus,NF / Ic = -2qVt2/Ic2 + (Rs + Rb)2*D*2q = 02qVt2*Ic2 = (Rs + Rb)2*D*2qIc (optimum) = Vt / (Rs + Rb)*D2.4(a) Calculate the numerical value of these configurations using the spice models A and BFor the Spice model A, the transistor is NPN with R b = 300The NF curve is shown below. Figure 2.7 variation of noise figure with source resistance simulated in MATLAB for spice model A 12
13. 13. The optimum noise figure calculated is 8.669 and the optimum collector bias current is 0.0014 A.For the Spice model B, the transistor is PNP with R b = 130The NF curve is shown below. Figure 2.8 variation of noise figure with source resistance simulated in MATLAB for spice model BThe optimum noise figure calculated is 5.782 and the optimum collector bias current is 0.0027 A.The optimum noise figure calculated is 5.782 and the optimum bias current is 0.0027 A.2.5(a) simulating the transfer functions Figure 2.9 Single ended BJT simulation 13
14. 14. 2.1(b) Expression for the noise figure of the differential common emitter stageThe noise model for the differential common emitter BJT is as shown below. Figure 2.10 transferring the collector shot noise to the input of the differential pair Figure 2.11 Equivalent current and voltage source at the input 14
15. 15. Figure 2.12 Applying delta current transformation Figure 2.13 Cancelling out redundant sources 15
16. 16. Figure 2.14 transferring the sources to the first differential input Figure 2.15 reduced small signal model of differentialIn the above figure, the noise sources BCEic2 and BCEic1 result from the transformation of the collector shot noise tothe input ports. ub1 and ub2 are the noise sources due to the base resistances of the two transistors.The noise current sources i1 and i2 are written asi1 = ib1 + DCE*ic1 i2 = ib2 + DCE*ic2We must note that the sources BCEic2 and DCE*ic2 are correlated, as well as, BCEic1 and DCE*ic1. 16
17. 17. We transform the current sources to voltage sources using Norton-Thevenin transformation. The resulting circuitdiagram is drawn below. Rb Bceic2 ub2 Bceic1 ub1 ib1*(2Rb+Rs)/2 Ib2*(2Rb+Rs)/2 Rb Figure 2.16 Applying thevenin theoremThe expression for the noise figure is given asNF = 1 + (NoiseDUT / Noisein)Adding the correlated sources and adding the power spectral densities of the uncorrelated sources, the expressionfor NoiseDUT is obtained as follows.NoiseDUT = 8KTRb + 2*BCE2*q*Ic + (2Rb + Rs)2*q*Ib + 2(2Rb + Rs)2*(DCE2)q*Ic –2DCE*BCE*2qIcSimplifying and substituting the constants, we getNoiseDUT = 8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIcThus, from the above equation, the expression for Noise figure is written as,NF = 10log (1 + (8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIc) / 4KTRs )The above equation is simulated in MATLAB and compared with the curve obtained in ADS. 17
18. 18. Figure 2.17 Variation of Noise figure with collector current Ic1 and Ic2 simulated in Matlab Figure 2.18 Variation of Noise figure with collector current Ic1 and Ic2 simulated in ADS2.3 (b) Optimum noise figure as a function of Collector Current 18
19. 19. Reiterating the expression for the noise figure, we can see its dependence on the collector bias current.NF = 10log (1 + (8KTRb + (8e-22 / Ic) + (1.8e-16*Ic) - 2DCE*BCE*2qIc) / 4KTRs )If we keep the source and the internal base resistance constant, we can differentiate the above equation with respectto the collector bias current. To obtain minima for the NF curve, we equate the slope to zero. Thus,Ic (optimum) = ((8e-22/(1.8e-162 DCE*BCE*2qIc )*4KTRs))^0.52.4 (b) Calculate the numerical value of these configurations using Spice models A and BFor the Spice model A, the transistor is NPN with R b = 300 m2 indep(m2)= 0.002 plot_vs(nf(2),IC1.i+IC2.i)=14.240 IBB=0.000005 m2For the Spice model B, the transistor is PNP with Rb = 130 13 m1 12 indep(m1)=0.002 plot_vs(nf(2),IC1.i+IC2.i)=9.817 IBB=0.000082 nf(2) 11 m1 10 9 0.0000 0.0002 0.0004 0.0006 0.0008 0.0010 0.0012 0.0014 0.0016 0.0018 0.0020 0.0022 IC1.i+IC2.i 19
20. 20. The noise figure depends on three variables namely, collector current, base resistance and the internal sourceresistance. The relation to the collector is apparent from the above figures. Initially the noise figure falls as afunction of the collector bias current. For the particular value of the collector bias current, the noise figure is lowest.After this point, the noise figure increases as a function of the collector bias current. The point where the noisefigure is lowest is point of optimum collector bias current. Note that, optimum collector current for noise figuredoes not guarantee best gain.The NF for spice model B is lower than the spice model A because of the lower value of the base resistance of thespice model B.The variation of the base resistance and the source resistance have the same curves as that of single ended BJTtranssitor shown in Figure 2.5 and Figure 2.62.5(b) Simulate the transfer function for the differential BJT pair2.6 (a) Expression for Common source configuration for a JFET amplifier in single ended mode.The small signal noise model is used to calculate the noise figure of the CS JFET. 20
21. 21. Figure 2.19 Small signal noise model of a JFET Figure 2.20 Small signal noise model of a JFET with the drain and flicker noise transferred to input Figure 2.21 Equivalent thevenin of the noise modelFig 2.19 shows the noise model of a JFET amplifier. The contribution to the noise figure is from the followingsources 21
22. 22. id= thermal noise in the channel (channel conductance between the source and drain)idf = flicker noise between source and the drainig= shot noise generated by saturation current I giig =induced gate noise voltageIdss=drain saturation currentAfter ignoring the contributions of iig , idf ,The Power spectral density of DUT(Pdut) and the source(Ps) is given byequations … the circuit in Figure 2 is used to drive the expression for the noise figure expression. 1 B Cgs.S gm 0.030 (Cgd Cgs ).S m1 D 0.025 Cgd .S gm 0.020 m1 Id.i id 2 4 KTcgm 0.015 indep(m1)= 2.000 0.010 plot_vs(Id.i, Vds)=0.025 Vgs=0.600000 0.005 4 KT *(2 f ) 2 Cgs 2ig 2 0.000 3 gm 0 2 4 6 8 10 Vdsgm ( 2 / Vth)( Idss * Id )0.5 Variation of the drain current with drain source voltage atVgs=0 Pdut ( f )F 1 Ps ( f ) ( B D( Rg Rs )) 2 4 KTcgm ( Rs Rg )ig 4 KTRgNF 10 log[1 ] (4 KTRs ) Vth is the threshold current which is found from the specifications in the ADS (-4.449). Idss is the drain saturation current. The drain saturation current was found to be 0.025 A by making V gs=0 22
23. 23. Impact of drain current on the noise figure 9 8 7 6 Noise figure[dB] 5 4 3 2 X: 0.25 Y: 1.511 1 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Id(drain current) Figure 2.22 Variation of Noise Figure with drain current simulated in MATAB 14 12 m2 Id.i= 0.264 10 plot_vs(nf(2),Id.i)=0.618 Vgs=0.700000 8 nf(2) 6 4 2 m2 0 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 Id.i Figure 2.23 Variation of Noise Figure with drain current simulated in ADS 23
24. 24. Impact of gate resistance Rg on the noise figure 5.5 5 4.5 4 3.5 Noise figure[dB] 3 2.5 2 1.5 1 0.5 0 10 20 30 40 50 60 70 80 90 100 gate resistance(Rg) Figure 2.24 Variation of Noise Figure with gate resistance simulated in MATLABImpact of source resistance on the noise figure 14 12 10 Noise figure[dB] 8 6 4 2 0 0 10 20 30 40 50 60 70 80 90 100 source resistance(Rs) Figure 2.25 Variation of Noise Figure with source resistance simulated in MATLAB 24
25. 25. Figure 2.26 Variation of Noise Figure with source resistance simulated in ADS2.8(a) Optimum noise figure as a function of drain CurrentReiterating the expression for the noise figure, we can see its dependence on the collector bias current. ( B D( Rg Rs))2 4 KTcgm ( Rs Rg )ig 4 KTRgNF 10log[1 ] (4 KTRs)If we keep the source and the internal base resistance constant, we can differentiate the above equation with respectto the collector bias current. To obtain minima for the NF curve, we equate the slope to zero. Thus, ( Rg Rs )(2 pif )2 Cgs 2Idopt ( 2/Vth)2 .Idss.c( B D( Rg Rs ))2 )2.9(a) Calculate the numerical value of these configurations using the spice model A and BFor the Spice model A, the JFET parameters are with Cgs = 5.74 pF ,Cgd=6.46pF. The noise figure as a function ofdrain current is plotted in Fig,2,23. The noise figure was found to be 0.632 dBFor the Spice model B, the JFET parameters are with Cgs = 47.7 pF , Cgd=47.7 pF. The noise figure as a functionof drain current is plotted in Fig 2,24. The noise figure was found to be 1.596 dB. The lower noise figure for spicemodel A is due to its lower value of gate source capacitance. 25
26. 26. Figure 2.27 Variation of Noise Figure with source resistance simulated in ADSFigure 2.28 Variation of Noise Figure with source resistance simulated in ADS 26
27. 27. 2.10(a) Simulate the transfer function for single ended JFET Figure 2.29 Single ended JFET noise figure simulation 27
28. 28. 2.6 (b) Expression for Common source configuration for a JFET amplifier in differential model Rg1 Vng1 Vng2 Rg2 Rs Ig1 Id1 Id1 Ig2 Rs2 Vs1 Vns Vs2 Vng1 Vng2 Bid2 Bid1 Rg1 Rg2 Ig1 Ig2 Rs2 Rs Did1 DId2 Vs1 Vs2 Figure 2.30 (a) small signal model of a differential JFET amplifier (b) With the drain shot noise transferred to input Bid1 Bid2 2Rg Rs Vs1 I1 I2 Un1+un2 Figure 2.31 Equivalent current and voltage noise sources 28
29. 29. Ueq Ieq Figure 2.32 Equivalent current and voltage noise sources (further simplified)Rs (2Rg+Rs)I2 (2Rg+Rs)I1 Rg ug2 Bid2 ug1 Bid2 Rg Figure 2.33 Equivalent thevenin noise modeli1 ig 1 Did 1;i2 ig 2 Did 2Pdut (8 KTRg B 2id 12 B 2id 2 2 (i12 i 2 2 )( Rs 2 Rg ) 2 )Ps 4 KTRs Pdut INF 1 Ps (8 KTRg B 2id 12 B 2id 22 (i12 i 22 )( Rs 2 Rg )2 )NF 10log 10 (1 ) 4 KTRs 29
30. 30. Impact of drain current on noise figure noise figure plot for differential configuration of cmos 5 4.5 4Noise figure[dB] 3.5 3 2.5 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 Id(drain current) Figure 2.34 Variation of Noise figure with drain current in MATLAB 30 m1 indep(m1)= 0.528 20 plot_vs(nf(2),Id1.i+Id2.i)=1.149 Vgs=0.700000 nf(2) 10 m1 0 0.0 0.1 0.2 0.3 0.4 0.5 0.6 Id1.i+Id2.i Figure 2.35 variation of Noise figure with drain current simulated in ADS 30
31. 31. The noise figure of the differential JFET decreases exponentially with the variation of drain current. The draincurrent is varied by changing the gate current to the JFET.The noise figure of a JFET doesn’t have a minimumbecause the NF depends on the gate source capacitance Cgs. Cgs is not a constant but varies with the frequency ofthe input signal.A difference of 1~1.5 dB can be seen from the plots of matlab and ADS. This is due to the assumptions that havebeen taken while simulating the noise figure in the both the softwares. In matlab , the contribution of the shot noisegenerated by the saturation current Ig (ig in the above equation) flowing through the reversed biased source anddrain is small and neglected.Impact of gate resistance on the noise figure noise figure plot for differential configuration of cmos 8 7.5 7 6.5 6 Noise figure[dB] 5.5 5 4.5 4 3.5 3 0 10 20 30 40 50 60 70 80 90 100 Rg Figure 2.36 variation of Noise figure with gate resistance simulated in MATLABAs the internal gate resistance is varied, the noise figure of the differential configuration increases exponentially.The noise figure of the differential pair is proportional to the gate resistance and directly contributes to the noise ofthe system. 31
32. 32. Impact of source resistance on the noise figure Figure 2.37 variation of Noise figure with source resistance simulated in ADS noise figure plot for differential configuration of cmos 16 14 12 Noise figure[dB] 10 8 6 4 2 0 10 20 30 40 50 60 70 80 90 100 Rs Figure 2.38 variation of Noise figure with source resistance simulated in MATLABThe noise figure for a differential configuration of JFET decreases exponentially with source resistance.This isbecause the ratio of Noise figure is caclulated with repsect to the source resistance noise (4KTRs). For impdancematching , the source resistance is kept at 50 ohm. 32
33. 33. 2.4(a)(b),2.8(a)(b) Compare the capabilities of the two technologies.JFETS have high input impedance compared to BJT transistorsJFET is based on CMOS technology and has the following advantages. Has less power dissipation than BJT’s Lower noise margin (From the noise figure plots of the two circuits.) Has better packaging density and integration Can be used as a good switch in digital design.Bipolar transistors are Have higher gm then the CMOS technology so results in a higher gain. Higher gain at the output Faster than CMOS due to higher ft BJT’s are better modeled and hence more predictable Consume base current and have more area than MOSFET’s JFETS have higher input impedance than the BJT’s Noisier than JFET’S2.8(b) Optimum noise figure of differential JFET as a function of drain CurrentThe optimum collector current for minimum noise figure is found out differentiating the expression below wrt toIc . (8 KTRg B2id12 B2id 22 (i12 i 22 )( Rs 2 Rg )2 )NF 10 log 10 (1 4 KTRs ( Rs 2 Rg ) 2 (4 KTRs )(4 KT )(2 pif ) 2 Cgs 2 2/3Idopt = ( ) 2 3( ) Idss .2 B 2 Vth2.9(b) Calculate the numerical value of these configurations using the spice model A and B 33
34. 34. For the Spice model A, the JFET parameters are with Cgs = 5.74 pF , Cgd=6.46pF. The noise figure as a function ofdrain current is plotted in Fig,2,23For the Spice model B, the JFET parameters are with Cgs = 47.7 pF , Cgd=47.7pF. The noise figure as a functionof drain current is plotted in Fig 2,24 .From the curves it can be inferred that noise figure of spice model B has a lower noise figure than that of spicemodel A. this is because a larger capacitance results in a smaller impedance ( Z=1/(2pifCgs)) ,hence a lowercontribution to noise figure . Figure 2.39 Variation of Noise figure with drain current for spice model A simulated in ADS 34
35. 35. Figure 2.33 Variation of Noise figure with drain current for spice model B simulated in ADS2.10(b) Simulate the transfer function Figure 2.40 Simulation of JFET differential pair in ADS 35
36. 36. Assignment 3: Feedback and NoiseC: Feedback and noise 4.1 Implement the first stage of the feedback configuration of assignment 1 by a JFET or a BJT differential stage. The first stage of the feedback circuit is designed to optimize noise. Noise is optimized first because in the first stage the bandwidth of the system is infinite, there is no distortion .Hence noise, and distortion and bandwidth are orthogonal to each other. In a cascade amplifier the last stage will have larger amplitude of signals compared to the first stage. Hence the effect of noise will be more at the 1st stage when the signal level is low than in the last stage where noise level is negligible compared to the signal level. If the gain of the 1 st stage is made large, then the noise contribution of the subsequent stages of an amplifier is negligible. Hence if we design the 1 st stage for noise, then noise contributions of the subsequent stages can be neglected in the analysis of the circuit. Noise behavior can be analyzed in presence of the nullor. The different noise sources due to noise producing components of an active circuit can be modeled by an equivalent voltage and current noise source at the input or at the output. If the noise is modeled at the input then the noise can be compared with the source signal to measure the SNR at the input. Modeling noise at the output gives the exact measurement of the noise sources. Noise modeled at the output can be transferred to the input using the ABCD chain matrix. The first stage of the feedback is implemented b a differential BJT amplifier. From the Vce Vs collector current plot for differential mode BJT, a collector current of 1.8 m A is inferred. The β (current gain factor) of BC550 ,hence the biasing current IB =Ic/ β.The base current for th differential pair is 4.80 µA.4.2 Derive an expression of the noise figure for the total feedback system.Explain the impact of Collector Current, input impedance and the internalinput resistor on the noise figure . In this assigment the feedback is implemented with a BJT differential pair configuration Figure 3.1 Blcok diagram of the amplifier cirucit withfeedback 36
37. 37. From the equivalent noise model of the BJT differential pair derived in the Assignment B, Vn Ub1 Ub 2 B(ic1 ic 2) i n i1 i 2 where i1 ib1 Dic1; i2 ib 2 Dic 2 Figure 3.2 applying voltage transform Figure 3.3 Applying thevenin to Norton transformation Figure 3.4 Applying current transform 37
38. 38. Figure 3.4 Equivalent noise current at the input Ineq in s(Cs Cf )Vn (Rs+2Rg)ineq Figure 3.5 Equivalent thevenin model Pdut (2 Rb Rs ) 2 ( Ineq) 2 Pdut (2 Rb Rs ) 2 (in s(Cs Cf )Vn) 2 Pdut (2 Rb Rs ) 2 (in s(Cs Cf )Vn) 2 Pdut (2 Rb Rs ) 2 (ib1 Dic1 ib 2 Dic 2 s (Cs Cf )(Ub1 Ub 2 B (ic1 ic 2))) 2 Ps 4 KTRs Pdut NF 10 log 10(1 ) Ps D*id1 is a very small value is neglected in calculation.Impact of collector current on the noise figure 38
39. 39. 20 19 m1 indep(m1)=0.001 18 plot_vs(nf(2),IC1.i+IC2.i)=14.567 IBB=0.000005 nf(2) 17 16 15 m1 14 0.0000 0.0005 0.0010 0.0015 0.0020 0.0025 0.0030 0.0035 IC1.i+IC2.i Figure 3.6 Variation of noise figure with collector current in ADS 28 26 24 22 Noise figure 20 18 X: 0.0152 Y: 16.05 16 14 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 collector current (Ic) Figure 3.7 Variation of noise figure with collector current in MATLABImpact of variation of base resistance Rb 39
40. 40. 45 40 35 30 Noise figure 25 20 15 10 5 0 50 100 150 200 250 300 base resistance(Rb) Figure 3.8 Variation of noise figure with base reisistance in MATLABImpact of variation of source resistance Rs Figure 3.8 Variation of noise figure with source resistance in ADS 40
41. 41. 25 24 23 22 21 Noise figure 20 19 18 17 X: 31 Y: 15.78 16 15 0 10 20 30 40 50 60 70 80 90 100 base resistance(Rb) Figure 3.9 Variation of noise figure with base resistance in MATLAB4.3 Calculate the numerical value of the feedback configurationThe numerical value of the noise figure in feedback configuration is 14.56 dB.4.4. Implement the feedback configuration in the simulator in use andsimulate the transfer function Figure 3.10 Implementation of feedback circuit with the differnetial input in ADS 41
42. 42. 4.5 Simulate the transfer functionFrom figure 3.2 it can be inferred that that SNR of the feedback circuit constantly increases to 132 dB .This may be due to the variation of impedance of capacitance with frequency.From Fig 3.3 ,it can be observed the power gain of the circuit constantly increases with frequency. Figure 3.11 the singal to noise ratio of the feedback cirucit. Figure 3.12 The power gain of the feedback configuration 42
43. 43. Assignment 3: Last StageC. Last Stage6. Implement the Last stage in the configuration in A.1 by a CMOS or Bipolar The last stage is designed to avoid clipping of the output signal . to bias the transistor so that outputsignal never clips for the specific signal range, the maximum load condition has to be found out. Thetotal load at the output stage can be calculated byIt can be expressed in the formWhere the load is calculated for the maximum possible frequency of the input signal (1.5 MHz). Theload impedance was found out to beZ(s)~92 ohm7. Determine the collector or the drain currentThe maximum output current for a constant output voltage of 0.5 volt and load impedance of 92 ohm is5.4 mA . The maximum output current is chosen 50 % beyond the minimum which is 8.1 mA . The bias 43
44. 44. current (base current) is calculated by the formula. The bias current (base current ) is found out from theIc vs Vce plot. It was inferred to be 21 uA. m1 indep(m1)= 0.700 plot_vs(IC.i, VCE)=0.003 IBB=0.000010 0.008 0.006 0.004 m1 IC.i 0.002 0.000 -0.002 0 2 4 6 8 10 VCE 44
45. 45. Assignment 4: Open Loop gainD. Open Loop gain After optimizing the noise and distortion of the amplifier, the amplifier is required to beoptimized for bandwidth. LP(loop –poles product) is a relatively simple measure of estimating thebandwidth of the amplifier circuit. The frequency behavior of the amplifier is split into two separateparts. Absolute Frequency: It is proportional to the distance between the poles and the origin. It is dependent on the constituent devices in the circuit and cannot be altered. Relative frequency: It is proportional to the relative pole positions. The relative frequency behavior can be altered by adding passive components in the circuit. Amplifier circuits usually use a relative frequency behavior of Butterworth type as it has a maximum flat magnitude transfer.The product of the DC loop gain and the poles is a measure of maximum attainable bandwidth and islarge for accurate amplifiers. The open loop gain is calculated by opening the circuit at any point (preferably the nullor) in thecircuit. In this assignment, an open loop gain of a BJT differential amplifier is calculated.For obtaining a negative loop gain, the input stage is implemented as a differential pair.The open loop gain of the circuit is given by the ratio Vin/Vaux. Figure 4.1 Small signal parameters of the charge amplifierTo find the open loop gain, the circuit is opened at a nullor of the first transistor of the differentialamplifier. 45
46. 46. Figure 4.2 Small singal parameters with the loop open at the output transistor nullor4.1 Determine the voltage gain transfer function as a function of frequency. V2The voltage gain transfer function is the ratio of .For simplification of calculations, Vin is Vinconsidered to be unity. The transfer function is given by equation4.2. Determine the positioning of the poles and zerosDue to pure capacitive feedback nature of the circuit, the DC loop gain of the charge amplifier is zero.This is because of a zero added at the origin due to the capacitive feedback. It can be compensated byattaching a resistor in parallel with the capacitance so that the time constant of the feedback network andthe input impedance of the nullor implementation are equal. The value of Rf was found from theexpression Cs Rf R1( ) 1M CfApplying Nodal analysis at nodes Vin,V1 ,V2 and Vcom 46
47. 47. gm3 V 2(1 / R 3 1 / Rload s * Cl 1 / Rf ) Vin ( s * Cf 1 / Rf ) 0...(1) Vin ( s*Cf s*Cs s*Cgs1 gm1 1/ Rf ) V 2( s*Cf 1/ Rf ) Vcom ( gm1 s*Cgs1 1/ R1) 0....(2) Vcom ( gm1 1/ R1 1/ R 2 gm 2 s*Cgs1) Vin ( gm1 s*Cgs1) V 1(1/ R 2) 0.....(3) (V 1)( s*Cgs 3 1/ R 2) Vcom ( gm 2 1/ R 2) 0....(4)The loop gain Vin/Vaux was calculated in mathematica. It is denoted by L(s). The ratio was found to be The following values of the BJT transistor parameters were used Cf=1*10^-9 Cs=10*10^-9 Cl=100*10^-9 Cbe1=11.5*10^-12 Cbe3=11.5*10^-12 gm1=0.0496 gm2=0.23709 gm3=0.0496 R3=10.153*10^3 R2=52.85*10^3 Rf=10^6 Rload=10^4 Ic The transconductance parameters gm1, gm2 and gm3 were calculated using the formula .The output Vt Va resistance is found from the formula R1,R2,R3 is found from the equation where Va is the early Ic voltage found from the model parameters. 47
48. 48. The poles are calculated from the characteristic equation:The four poles were calculated to be{{s-3.82755×109} ,p1=-6.09e8 Hz{s-734994}, p2=-1.16e5 Hz{s-3621.48}, p3=-576.3764 Hz{s-49.5064}}, p4=-7.87 HzThe zeros of the transfer function is found form the equationThe zeros were found to be{s= -8.6302×109},{s= -1.34392×108-1.35258×108j},{s= -1.34392×108+1.35258×108j},{s= 1.33981×108-1.33171×108j},{s= 1.33981×108+1.33171×108j}The DC loop gain L(0) is calculated by substituting s=0 in the loop gain transfer function. It was foundto beThe bandwidth of the system is calculated from the eq . 48
49. 49. The bandwidth for the 4 poles was calculated to be 9.93e+005 Hz which is less than the requiredbandwidth. This indicates that all the 4 poles are not the dominant poles. To find whether the chosenpoles are dominant or not, the sum of the loop poles (pl1+pl2) should be greater than the sum of theButterworth system of poles (ps1 and ps2). 1ps1 ps 2 = - 2* * 2 * BW =-1.41e6 Hz 2pl1 pl 2 = -1.16e5 -576.3764=-1.16e5 HzHence pl1 pl 2 > ps1 ps 2Considering p1, the sum of the loop poles is equal to p1 which is very small compared to the systempoles ( -1.41e6 Hz),so p1 is not a dominant pole.Similarly considering p4, the bandwidth of the 3 pole system is 1.73e4 Hz which is less than the requiredbandwidth. Hence p4 is a non dominant pole.Using the poles p2 and p3 the maximum bandwidth of the second order system is calculated to be (B max (1 3.12e6)*1.161e5*576.37) = 14.43e6 HzAs Bmax is greater than the specified bandwidth, frequency compensation can be applied to achieve thisbandwidth. Phantom zero is one of the preferred techniques used in frequency compensation, 4.3 Remove the ideal nullator and determine the open and closed loop function of the feedbackThe open loop function of the feedback is determined by the ratio Vin/V2 when the amplifier loop isopened at the second nullor. The output voltage is given by V2 in the following expression 49
50. 50. Vin is given by loop gain function derived aboveThe closed loop function of the feedback is given by Vin/V2 where theVin is assumed to be unity for simplifying the calculations and V2 is given by 50
51. 51. Assignment 5E. Closed Loop gain5.1 Determine the transfer function and the noise figure of the closed loop system Figure 5.1 The complete feedback amplifier circuit without the nullorThe closed loop transfer function is given by the equation L( s )At ( s ) At 1 L( s )Where At is the asymptotic gain given by Cf, the feedback capacitor and L(s) is the loop gain of thefeedback amplifier. 51
52. 52. The expression for closed loop gain is given byThe open loop transfer function is given byLWhere α is the open loop transfer function and β is the feedback transfer function and L the loop gain. 1At so the open loop transfer function is given by L * At and given be the expressionThe noise figure of the feedback loop is simulated in ADS using the s parametersIt can be inferred that that addition of the output stage has not increased the noise figure of the system .Inassignment 2 the minimum noise figure of the differential BJT was observed to be ~14dBm. Thecomplete circuit has a minimum noise figure of 11dBm. Hence the first stage of the feedback circuit hasbeen correctly optimized for noise figure. 52
53. 53. Figure 5.2 The noise figure of the feedback cirucit 53
54. 54. Assignment 66.1 Check the stability of the systemIn this assignment we perform frequency compensation such that the poles of the closed loop system arein the Butterworth position. Frequency compensation is changing the coefficient of the s terms in thecharacteristic polynomial without changing the LP product.The characteristic polynomial of a Butterworth second order system is given by the equationPhantom zero is method of frequency compensation which adds a zero to the loop. This zero is notvisible in the transfer function is called a phantom zero. The phantom zero is realized at the input. Thetype of component to be used as a phantom load depends on the source impedance.(given in table .) Thephantom zero is not implemented in the feedback as it is not possible for a parallel connection of acompensation element to increase beyond phantom pole. At the output the load capacitor introduces anattenuation of high frequency.Figure 6.1 Small signal model of the amplifier cirucitThe closed loop transer function of ampilifer compensated with a phantom load is given by 54
55. 55. The location of the phantom zero is given by the equationWhere p1= -1.16e5 Hz,p2= -576.37 Hz andLP = 2.086e14 HzThe required phantom zero is located at n1 = -10.27e6 HzThe value of the phantom load (the resistor) is calculated from the formulaRph = 1.5497 ohmThis phantom zero was added to the circuit as shown in FigureFigure 6.2 Frequency compensation by addition of phantom load Rph 55
56. 56. Figure 6.3 ADS simulation of the complete amplifier cuircuit with phantom loadThe stability of the system is measured by the Rollette’s stability criterion, which is given byFor K>1 the circuit is unconditionally stable and K<1 the circuit is unconditionally stable.From the stability curve Fig 6.3 it can be observed that the feedback circuit is unstable until the 590 KHzand then conditionally stable till the 1.5 MHz.From the Fig 6.4, it is inferred that the output signal is constant at 0.5 volts throughout the frequencyrange of the input signal.From Fig 6.5 , the signal to noise ratio is observed to be 115 dBm which is larger than the required SNRof 70 dBm. Hence the feedback circuit meets the required specifications. 56
57. 57. Figure 6.4 Variation of Stability factor with frequency Figure 6.5 Plot of output voltage Vs frequency. Figure 6.6 Variation of SNR with frequency 57