The 8051 Microcontroller: Instruction Set
<ul><li>BYTE INSTRUCTION: </li></ul><ul><ul><li>MOV A, Rn (Rn ranges) </li></ul></ul><ul><ul><li>MUL AB </li></ul></ul><ul...
<ul><li>ARITHMETIC INSTRUCTION. </li></ul><ul><li>DATA TRANSFER INSTRUCTION. </li></ul><ul><li>LOGICAL INSTRUCTION. </li><...
<ul><li>ARITHMETIC OPERATIONS. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2. </li></ul><ul><li>FLAGS AFFECTED. </li>...
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>ADDRESSING MODE. </li></ul...
Before execution ADD A, R3 A 13 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution ADD A, R3 A 44 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 1
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>ADDRESSING MODE. </li></ul...
Before execution INC A A 1F B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution INC A A 20 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>SOURCE TO DESTINATION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>MOV/MOVC/MOVX...
<ul><li>FUNCTION. </li></ul>MOV <destination byte>, <source Byte> <ul><li>Flags affected. </li></ul><ul><li>Length-1, 2 or...
Before execution MOV A, R7 A 00 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution MOV A, R7 A 14 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul><ul><li>COMPULSORY OPERAND. </li><...
Before execution XCH A, R5 A 27 B R0 R1 R2 R3 R4 R5 72 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution XCH A, R5 A 72 B R0 R1 R2 R3 R4 R5 27 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>PERFORMS LOGICAL OPERATIONS. </li></ul><ul><li>LENGTH-1,2 OR 3 </li></ul><ul><li>FLAG AFFECTED. </li></ul>Logical ...
<ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul>ANL A, R0
Before execution ANL A, R2 A 10 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution ANL A, R2 A 00 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul>CPL A
Before execution CPL A A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution CPL A A 00 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>TRANSFERS PROGRAM CONTROL. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul>Branching Instruc...
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>2 OR 3 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>DJNZ <byt...
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul>JNZ rel
<ul><li>FUNCTIONS. </li></ul><ul><li>PERFORMED ON BITS. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul>Logic...
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>CLR bit
Before execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0
After execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
<ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>CPL bit
Before execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
After execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0
By: Mayank Sharma
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8051 Instruction Set

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A short presentation on instruction set of MC-8051

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  • No flags affected.
  • 1. Two operands source and destination. 2. MOVC ¬†instruction moves a byte from the code or program memory to the accumulator 3. Length 1 2 n 3 bytes 4. if MOVX present, transfer to/from external memory
  • 15 combos of source n destination code is possible
  • 8051 Instruction Set

    1. 1. The 8051 Microcontroller: Instruction Set
    2. 2. <ul><li>BYTE INSTRUCTION: </li></ul><ul><ul><li>MOV A, Rn (Rn ranges) </li></ul></ul><ul><ul><li>MUL AB </li></ul></ul><ul><li>BYTE INSTRUCTION: </li></ul><ul><ul><li>DNJZ Rn, rel </li></ul></ul><ul><ul><li>SUBB A, direct address </li></ul></ul><ul><li>BYTE INSTRUCTION </li></ul><ul><ul><li>ANL direct, #data </li></ul></ul><ul><ul><li>MOV direct, #data </li></ul></ul>Length of Instructions:
    3. 3. <ul><li>ARITHMETIC INSTRUCTION. </li></ul><ul><li>DATA TRANSFER INSTRUCTION. </li></ul><ul><li>LOGICAL INSTRUCTION. </li></ul><ul><li>BRANCHING INSTRUCTION. </li></ul><ul><li>LOGICAL OPERATION ON BITS INSTRUCTION. </li></ul>Classification of instructions:
    4. 4. <ul><li>ARITHMETIC OPERATIONS. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2. </li></ul><ul><li>FLAGS AFFECTED. </li></ul>Arithmetic instruction
    5. 5. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>ADDRESSING MODE. </li></ul>ADD A, Rn
    6. 6. Before execution ADD A, R3 A 13 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    7. 7. After execution ADD A, R3 A 44 B R0 R1 R2 R3 31 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 1
    8. 8. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>ADDRESSING MODE. </li></ul>INC Rn
    9. 9. Before execution INC A A 1F B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    10. 10. After execution INC A A 20 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    11. 11. <ul><li>SOURCE TO DESTINATION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>MOV/MOVC/MOVX </li></ul>Data transfer group
    12. 12. <ul><li>FUNCTION. </li></ul>MOV <destination byte>, <source Byte> <ul><li>Flags affected. </li></ul><ul><li>Length-1, 2 or 3 </li></ul><ul><li>Source-Destination combo. </li></ul>
    13. 13. Before execution MOV A, R7 A 00 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    14. 14. After execution MOV A, R7 A 14 B R0 R1 R2 R3 R4 R5 R6 R7 14 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    15. 15. <ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul><ul><li>COMPULSORY OPERAND. </li></ul>XCH A, Rn
    16. 16. Before execution XCH A, R5 A 27 B R0 R1 R2 R3 R4 R5 72 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    17. 17. After execution XCH A, R5 A 72 B R0 R1 R2 R3 R4 R5 27 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    18. 18. <ul><li>PERFORMS LOGICAL OPERATIONS. </li></ul><ul><li>LENGTH-1,2 OR 3 </li></ul><ul><li>FLAG AFFECTED. </li></ul>Logical group
    19. 19. <ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul>ANL A, R0
    20. 20. Before execution ANL A, R2 A 10 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    21. 21. After execution ANL A, R2 A 00 B R0 R1 R2 01 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    22. 22. <ul><li>FUNCTION. </li></ul><ul><li>FLAGS AFFECTED. </li></ul><ul><li>LENGTH. </li></ul>CPL A
    23. 23. Before execution CPL A A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    24. 24. After execution CPL A A 00 B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    25. 25. <ul><li>TRANSFERS PROGRAM CONTROL. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul>Branching Instructions
    26. 26. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>2 OR 3 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>DJNZ <byte>, <rel-address>
    27. 27. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH. </li></ul><ul><li>FLAGS AFFECTED. </li></ul>JNZ rel
    28. 28. <ul><li>FUNCTIONS. </li></ul><ul><li>PERFORMED ON BITS. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul>Logical operations on Bit
    29. 29. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>CLR bit
    30. 30. Before execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0
    31. 31. After execution CLR C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    32. 32. <ul><li>FUNCTION. </li></ul><ul><li>LENGTH- </li></ul><ul><li>1 OR 2 </li></ul><ul><li>FLAGS AFFECTED. </li></ul>CPL bit
    33. 33. Before execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 0 0 - 1 1 0 - 0
    34. 34. After execution CPL C A FF B R0 R1 R2 R3 R4 R5 R6 R7 CY AC F0 RS1 RS0 OV - P 1 0 - 1 1 0 - 0
    35. 35. By: Mayank Sharma
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