Multiprocessor Architecture for Image Processing

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Multiprocessor Architecture for Image Processing

  1. 1. Multiprocessor Architecture for Image processing Mayank Kumar – 2006EE10331 Pushpendre Rastogi – 2006EE50412 Under the guidance of Dr.Anshul Kumar
  2. 2. Objectives <ul><li>To learn to work on FPGA platform. </li></ul><ul><li>Learning the design philosophy of a soft core multiprocessor architecture. </li></ul><ul><li>Using multiprocessor architecture to implement adaptive background mixture model for motion segmentation. i.e Background modeling and change detection algorithm. (Cris stauffer) </li></ul>
  3. 3. Motivation <ul><li>Signal processing, especially Image processing involves repetitive computation which can easily be divided into parallel computations </li></ul><ul><li>There are many algorithm that follows “locally sequential globally parallel” computation. </li></ul><ul><li>Surveillance camera related processing need economic real time solutions. </li></ul><ul><li>FPGA provides an easy way to alter design depending on algorithm requirements – making soft multicore processing feasible. </li></ul><ul><li>Architecture of the Processing Elements (PE) could be optimized for image processing. </li></ul>
  4. 4. Adaptive background mixture model <ul><li>The algorithm helps to generate an adaptive model for the background and helps in motion detection. </li></ul><ul><li>This can be applied for surveillance. </li></ul><ul><li>The algorithm is spatially parallel, thus computations for different part of the image can be done simultaneously. </li></ul><ul><li>This will help in real time operation of this algorithm on embedded platform. </li></ul>
  5. 5. Nature of parallelism <ul><li>Data Partitioning: The task is partitioned so that each processor performs exactly the same function, but on different sub-blocks of data. </li></ul><ul><li>For different image regions, our chosen algorithm is sequential in nature, which can be efficiently implemented through a processor. </li></ul>
  6. 6. Basic Idea Camera Video ADC` Virtex II Pro RGB Conversion Power PC M1 M1 M1 M1 M1 M1 M1 M1 M1 M E M O R Y Video DAC MPMC Monitor Array Topology
  7. 7. Basic Idea Camera Video ADC` Virtex II Pro RGB Conversion Power PC M1 M1 M1 M1 M1 M1 M1 M1 M1 M E M O R Y Video DAC MPMC Monitor Array Topology
  8. 8. Inter-processor Communication [12] <ul><li>For transferring large chunks of image data, we will be using shared external DDR Ram as </li></ul><ul><ul><li>It provides large memory space for storing multiple frames. </li></ul></ul><ul><ul><li>Multiple processors can access the RAM simultaneously using MPMC. </li></ul></ul><ul><li>For sharing intermediate computation results we will use FSL Links between neighboring processors. </li></ul><ul><ul><li>Unidirectional point-to-point communication. </li></ul></ul><ul><ul><li>Unshared non-arbitrated communication mechanism. </li></ul></ul><ul><ul><li>FIFO based communication. </li></ul></ul>
  9. 9. Network Topology [1] <ul><li>Completely meshed: Each node is connected to all other nodes. Adv: Reduce inter processor communication time. Disadvantage: Max 9 processors possible. </li></ul><ul><li>Ring Network : </li></ul><ul><li>Star Network </li></ul><ul><li>Array Network: (our choice) </li></ul>
  10. 10. Overall Plan <ul><li>Analysis of the algorithm. </li></ul><ul><li>Configuring Video input and output for XUPV2P FPGA kit. </li></ul><ul><li>Finalizing the architecture </li></ul><ul><ul><li>For one processor </li></ul></ul><ul><ul><li>For two processors </li></ul></ul><ul><ul><li>For multiprocessors </li></ul></ul><ul><li>Implementing </li></ul><ul><ul><li>Basic Test algorithm </li></ul></ul><ul><ul><li>The algorithm </li></ul></ul>
  11. 11. Work Done <ul><li>Studied Background mixture Model for foreground subtraction algorithm [2], [3] , as a case study. </li></ul><ul><li>Analysis of the algorithm for: </li></ul><ul><ul><li>Parallelism exploitation </li></ul></ul><ul><ul><li>Length of code for implementation </li></ul></ul><ul><ul><li>Memory requirements to store data. </li></ul></ul><ul><ul><li>Feasibility </li></ul></ul>
  12. 12. Work Done Camera Video ADC` Virtex II Pro RGB Conversion Power PC Video DAC Monitor Top Down Approach
  13. 13. Work Done <ul><li>Studied Microblaze architecture. [4] </li></ul><ul><li>Studied </li></ul><ul><ul><li>FSL Link [5] </li></ul></ul><ul><ul><li>PLB, LMB, OPB Buses [6] </li></ul></ul><ul><ul><li>XPS Design Flow [7] </li></ul></ul><ul><li>Literary survey on related works [8],[9], [10], [11] </li></ul><ul><li>Configuration Video input and output for XUPV2P FPGA kit. </li></ul>Bottom Up Approach
  14. 14. Work Ahead – Step 1 Camera Video ADC` Virtex II Pro RGB Conversion Power PC M E M O R Y Video DAC MPMC Monitor Memory Read And Write 23 rd Feb – 7 th March
  15. 15. Work Ahead – Step 2 Camera Video ADC` Virtex II Pro RGB Conversion Power PC M1 M E M O R Y Video DAC MPMC Monitor Some Simple Processing 8 th March – 15 th March
  16. 16. Work Ahead – Step 3 Camera Video ADC` Virtex II Pro RGB Conversion Power PC M1 M1 M1 M1 M1 M1 M1 M1 M1 M E M O R Y Video DAC MPMC Monitor Simple processing 24 th March – 5 th April
  17. 17. Work Ahead – Step 4 Camera Video ADC` Virtex II Pro RGB Conversion Power PC M1 M1 M1 M1 M1 M1 M1 M1 M1 M E M O R Y Video DAC MPMC Monitor Complex Processing 6 th April – 19 th April
  18. 18. Time Line <ul><li>Step 1 – 23 rd Feb – 7 th March </li></ul><ul><li>Step 2 – 8 th March – 15 th March </li></ul><ul><li>Step 3 – 24 th March – 5 th April </li></ul><ul><li>Step 4 – 6 th April – 19 th April </li></ul>
  19. 19. Related Works <ul><li>Design Development and performance evaluation of multiprocessor system on FPGA. Somen Barma, CSE IITD. [8]. </li></ul><ul><li>A Microblaze based Multiprocessor SoC[1] </li></ul><ul><li>An FPGA based soft multiprocessor system for IPv4 packet forwarding. [9] </li></ul><ul><li>An automated framework for FPGA based soft Multiprocessor System. [10] </li></ul><ul><li>Multiprocessor interconnection based on DMA for FPGA.[11] </li></ul>
  20. 20. REFERENCES <ul><li>[1] A Microblaze based Multiprocessor SOC – 2003 </li></ul><ul><li>[2] Adaptive background mixture model for real-time tracking – 1999 </li></ul><ul><li>[3] Understanding background mixture model for foreground segmentation – 2002 </li></ul><ul><li>[4] Microblaze processor reference guide </li></ul><ul><li>[5] Xilinx FSL datasheet </li></ul><ul><li>[6] Xilinx Microblaze bus interface (ppt) </li></ul><ul><li>[7] Virtex II Pro design flow – getting started </li></ul><ul><li>[8] Design Development and performance evaluation of multiprocessor system on FPGA. Somen Barma, CSE IITD. Under Prof Kolin Paul </li></ul><ul><li>[9] An FPGA based soft multiprocessor system for IPv4 packet forwarding. </li></ul><ul><li>[10] An automated framework for FPGA based soft Multiprocessor System. </li></ul><ul><li>[11] Multiprocessor interconnection based on DMA for FPGA. </li></ul><ul><li>[12] XPS White paper – Designing multiprocessor System on Platform Stdio. </li></ul>Visit www.cse.iiitd.ernet.in/~ee5060412

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