IEEE 2013 projects,M.Tech 2013 Projects,Final year Engineering Projects,Best student Projects,MS Projects,BE Projects,2013 2014 IEEE Projects
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IEEE 2013 projects,M.Tech 2013 Projects,Final year Engineering Projects,Best student Projects,MS Projects,BE Projects,2013 2014 IEEE Projects

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CITL Tech Varsity, a leading institute for assisting academicians M.Tech / MS/ B.Tech / BE (EC, EEE, ETC, CS, IS, DCN, Power Electronics, Communication)/ MCA and BCA students in various Domains & ...

CITL Tech Varsity, a leading institute for assisting academicians M.Tech / MS/ B.Tech / BE (EC, EEE, ETC, CS, IS, DCN, Power Electronics, Communication)/ MCA and BCA students in various Domains & Technologies from past several years.
DOMAINS WE ASSIST
HARDWARE:
Embedded, Robotics, Quadcopter (Flying Robot), Biomedical, Biometric, Automotive, VLSI, Wireless (GSM,GPS, GPRS, RFID, Bluetooth, Zigbee), Embedded Android.
SOFTWARE
Cloud Computing, Mobile Computing, Wireless Sensor Network, Network Security, Networking, Wireless Network, Data Mining, Web mining, Data Engineering, Cyber Crime, Android for application development.
SIMULATION:
Image Processing, Power Electronics, Power Systems, Communication, Biomedical, Geo Science & Remote Sensing, Digital Signal processing, Vanets, Wireless Sensor network, Mobile ad-hoc networks
TECHNOLOGIES WE WORK:
Embedded (8051, PIC, ARM7, ARM9, Embd C), VLSI (Verilog, VHDL, Xilinx), Embedded Android
JAVA / J2EE, XML, PHP, SOA, Dotnet, Java Android.
Matlab and NS2
TRAINING METHODOLOGY
1. Train you on the technology as per the project requirement
2. IEEE paper explanation, Flow of the project, System Design.
3. Algorithm implementation & Explanation.
4. Project Execution & Demo.
5. Provide Documentation & Presentation of the project.

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IEEE 2013 projects,M.Tech 2013 Projects,Final year Engineering Projects,Best student Projects,MS Projects,BE Projects,2013 2014 IEEE Projects IEEE 2013 projects,M.Tech 2013 Projects,Final year Engineering Projects,Best student Projects,MS Projects,BE Projects,2013 2014 IEEE Projects Document Transcript

  • Digital Signal Processing NO PRJ TITLE ABSTRACT DOMAIN YOP 1 Low- Complexity Multiplier for GF(2m) Based on All-One Polynomial s This paper presents an area-time-efficient systolic structure for multiplication over �_ _ based on irreducible all- one polynomial (AOP). We have used a novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay. It is further shown that the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input operand, and they can share the same input operand registers. From the application-specific integrated circuit and field-programmable gate array synthesis results we find that the proposed design provides significantly less area-delay and power-delay complexities over the best of the existing designs. Digital Signal Processing 2013 2 Low Latency Systolic Montgomer y Multiplier for Finite Field Based on Pentanomia ls In this paper, we present a low latency systolic Montgomery multiplier over based on irreducible pentanomials. An efficient algorithm is presented to decompose the multiplication into a number of independent units to facilitate parallel processing. Besides, a novel so-called “pre-computed addition” technique is introduced to further reduce the latency. The proposed design involves ignificantly less area-delay and power-delay complexities compared with the best of the existing designs. It has the same or shorter critical-path and involves nearly one-fourth of the latency of the other in case of the National Institute of Standards and Technology recommended irreducible pentanomials. Digital Signal Processing 2013 3 CORDIC Designs for Fixed Angle of Rotation Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits.Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro- rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed Digital Signal Processing 2013 #56, II Floor, Pushpagiri Complex, 17th Cross 8th Main, Opp Water Tank,Vijaynagar,Bangalore-560040. Website: www.citlprojects.com, Email ID: projects@citlindia.com,hr@citlindia.com MOB: 9886173099 / 9986709224, PH : 080 -23208045 / 23207367 VLSI PROJECTS – 2013 (Network-Security & Cryptographic Sciences, DSP, Arithematic Code & Digital Electronics, Digital Communication & Information Theory, Digital Image Proccesing)
  • and known angles of rotation. We find similar results of synthesis for different Xilinx field-programmable gate- array platforms 4 CORDIC Based Fast Radix-2 DCT Algorithm This letter proposes a novel coordinate rotation digital computer (CORDIC)-based fast radix-2 algorithm for computation of discrete cosine transformation (DCT). The proposed algorithm has some distinguish advantages, such as Cooley-Tukey fast Fourier transformation (FFT)-like regular data flow, uniform post- scaling factor, in-place computation and arithmetic-sequence rotation angles. Compared to existing DCT algorithms, this proposed algorithm has lower computational complexity. Furthermore, the proposed algorithm is highly scalable, modular, regular, and suitable for pipelined VLSI implementation. In addition, this letter also provides an easy way to implement the reconfigurable or unified architecture for DCTs and inverse DCTs. Digital Signal Processing 2013 5 Low power and memory efficient FFT architecture using modified CORDIC algorithm This paper presents a pipelined, reduced memory and low power CORDIC-based architecture for fast Fourier transform implementation. The proposed algorithm utilizes a new addressing scheme and the associated angle generator logic in order to remove any ROM usage for storing twiddle factors. CORDIC is implemented by a simple hardware through repeated shift-add operations Low power is achieved by the using the Coordinate Rotation Digital Computer algorithm in the place of conventional multiplication and furthermore, dynamic power consumption is reduced with no delay penalties. Digital Signal Processing 2013 6 CORDIC Designs for Fixed Angle of Rotation Rotation of vectors through fixed and known angles has wide applications in robotics, digital signal processing, graphics, games, and animation. But, we do not find any optimized coordinate rotation digital computer (CORDIC) design for vector-rotation through specific angles. Therefore, in this paper, we present optimization schemes and CORDIC circuits for fixed and known rotations with different levels of accuracy. For reducing the area- and time-complexities, we have proposed a hardwired pre-shifting scheme in barrel-shifters of the proposed circuits. Two dedicated CORDIC cells are proposed for the fixed-angle rotations. In one of those cells, micro-rotations and scaling are interleaved, and in the other they are implemented in two separate stages. Pipelined schemes are suggested further for cascading dedicated single-rotation units and bi-rotation CORDIC units for high-throughput and reduced latency implementations. We have obtained the optimized set of micro- rotations for fixed and known angles. The optimized scale-factors are also derived and dedicated shift-add circuits are designed to implement the scaling. The fixed-point mean-squared-error of the proposed CORDIC circuit is analyzed statistically, and strategies for reducing the error are given. We have synthesized the proposed CORDIC cells by Synopsys Design Compiler using TSMC 90-nm library, and shown that the proposed designs offer higher throughput, less latency and less area-delay product than the reference CORDIC design for fixed and known angles of rotation. We find similar results of synthesis for different Xilinx field- programmable gate-array platforms Digital Signal Processing 2013
  • 7 A survey of FPGA based Interference cancellation architecture s for biomedical signals This paper analyses four different architectures for real time FPGA based implementation of an adaptive Power Line Interference (PLI) canceller like using Parallel LMS, ADALINE, wavelet and sequential LMS. The adaptive canceller automatically adjust its parameters to eliminate the noise in biomedical signals and then to denoise it. Different techniques successfully remove the present PLI from ECG signal. Several advantages of FPGA based Adaptive PLI canceller are presented. It uses FPGA type Xilinx logic programmable mechanism for implementation. Digital Signal Processing 2013 8 Optimized FIR filters for digital pulse compressio n of biphase codes with low sidelobes In miniaturized radars where power, real estate, speed and low cost are tight constraints and Doppler tolerance is not a major concern biphase codes are popular and FIR filter is used for digital pulse compression (DPC) implementation to achieve required range resolution. Disadvantage of low peak to sidelobe ratio (PSR) of biphase codes can be overcome by linear programming for either single stage mismatched filter or two stage approach i.e. matched filter followed by sidelobe suppression filter (SSF) filter. Linear programming (LP) calls for longer filter lengths to obtain desirable PSR. Longer the filter length greater will be the number of multipliers, hence more will be the requirement of logic resources used in the FPGAs and many time becomes design challenge for system on chip (SoC) requirement. This requirement of multipliers can be brought down by clustering the tap weights of the filter by kmeans clustering algorithm at the cost of few dB deterioration in PSR. The cluster centroid as tap weight reduces logic used in FPGA for FIR filters to a great extent by reducing number of weight multipliers. Since kmeans clustering is an iterative algorithm, centroid for weights cluster is different in different iterations and causes different clusters. This causes difference in clustering of weights and sometimes even it may happen that lesser number of multiplier and lesser length of filter provide better PSR. Digital Signal Processing 2013 9 Design and Implementa tion of Adaptive filtering algorithm for Noise Cancellatio n in speech signal on FPGA In recent years FPGA systems are replacing dedicated Programmable Digital Signal Processor (PDSP) systems due to their greater flexibility and higher bandwidth, resulting from their parallel architecture. This paper presents the applicability of a FPGA system for speech processing. Here adaptive filtering technique is used for noise cancellation in speech signal. Least Mean Squares (LMS ) , one of the widely used algorithm in many signal processing environment , is implemented for adaption of the filter coefficients. The cancellation system is implemented in VHDL and tested for noise cancellation in speech signal. The simulation of VHDL design of adaptive filter is performed and analyzed on the basis of Signal to Noise ratio (SNR) and Mean Square Error (MSE). Digital Signal Processing 2012 10 Implementa tion of generalized dft on field programma ble gate array We introduce the implementation of Generalized Discrete Fourier Transform (GDFT) with nonlinear phase on a Field Programmable Gate Array (FPGA.) After briefly revisiting the GDFT framework, we apply the framework to a channel equalization problem in an Orthogonal Frequency Division Multiplexing (OFDM) communication system. The block diagram of the system is introduced and detailed explanations of the implementation for each block are given along with the necessary VHDL code snippets. The resource usage and registered performance of the design is reported and alternatives to improve the design in terms of performance and resolution are provided. To the best of our knowledge, this is the first hardware implementation of GDFT reported. Digital Signal Processing 2012 11 Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementa tion The Fast Fourier Transform (FFT) is one of the rudimentary operations in field of digital signal and image processing. Some of the very vital applications of the fast fourier transform include Signal analysis, Sound filtering, Data compression, Partial differential equations, Multiplication of large integers, Image filtering etc.Fast Fourier transform (FFT) is an efficient implementation of the discrete Fourier transform (DFT). This paper concentrates on the evelopment of the Fast Fourier Transform (FFT), based on Decimation-In-Time (DIT) domain, Radix-2 algorithm, this paper uses VHDL as a design entity, and their Synthesis by Xilinx Synthesis Tool on Vertex kit has been done. The input of Fast Fourier transform has been given by a PS2 KEYBOARD using a testbench and output has been displayed using the waveforms on the Xilinx Design Suite 12.1.The synthesis results show that the computation for calculating the 32-point Fast Fourier transform is efficient in terms of speed. Digital Signal Processing 2012
  • 12 Distributed Arithmetic LMS Adaptive Filter Implementa tion without Look-Up Table This paper presents an implementation of least mean squared (LMS) adaptive filter using distributed arithmetic (DA) for hardware realization. Coefficient-distributive DA will be used instead of conventional DA for more appropriation to use with adaptive filter that filter coefficients are varied by time. Moreover, adder network and multiplexer structure will be used in coefficientdistributive DA which makes the proposed LMS adaptive filter be multiplierless digital filter and also without using look-up table (LUT). The VHDL is used for hardware design and then synthesis and configure onto FPGA for real-time adaptive filtering experiment. Finally, experimental and simulation results are shown to ensure our proposed LMS adaptive filter can work. Digital Signal Processing 2012 13 Area- Efficient VLSI Implementa tion for Parallel Linear- Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm Based on fast FIR algorithms (FFAs), this brief proposes new parallel FIR filter architectures, which are beneficial to symmetric convolutions of odd length in terms of the hardware cost. The proposed parallel FIR architectures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in the subfilter section at the expense of increase in adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area, and in addition, the overhead from the increase in adders in preprocessing and postprocessing blocks stay fixed, not increasing along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a three-parallel 81-tap filter, the proposed structure saves 26 multipliers at the expense of five adders, whereas for a three-parallel 591-tap filter, the proposed structure saves 196 multipliers at the expense of five adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolution in odd length from the existing FFA parallel FIR filter, particularly when the length of the filter is large. Digital Signal Processing 2012 14 Fully Parallel and Fully Serial architecture for realization of high speed FIR Filters with FPGA's This paper presents fully parallel and fully serial architectures for Band pass filter. The performances of fully parallel and fully-serial architectures are analyzed for different quantized versions of representation. Filters generated using 8 bit fixed point implementation requires smaller area usage when compared to 16 bit fixed point implementation at the cost of imprecision. The proposed implementations are synthesized with Xilinx ISE 13.2 version. Family of device was Spartan 3E and target device was xa3s250e-4vqgl00. The key performance metrics, namely number of Slices, Slice Flip Flops, LUTs, Maximum frequency are compared. Digital Signal Processing 2012 15 A Dynamic Partial Reconfigur able FIR Filter Architectur e FIR Filter are employed in a wide range of applications. The recent demands of performance hungry applications include reusability and efficiency in terms of power dissipation. Thus the age old FIR architecture becomes less suitable and dynamic partial reconfigurable filters are the order of the day. This paper presents a partial reconfigurable FIR filter design. Our aim is to implement a partial reconfigurable filter that incorporates design flexibility allowing to be tailored to specific needs. It also addresses the issue of quicker reconfiguration and allows dynamic change of the filter order. Digital Signal Processing 2012
  • 16 Hardware Implementa tion of Discrete Fourier Transform and its Inverse Using Floating Point Numbers This paper concentrates on the FPGA implementation of discrete Fourier transforms (DFT) and inverse discrete Fourier transform (IDFT) based on floating point numbers. Floating point representation of the numbers support much wider range of values and achieve greater range at the expense of precision. Firstly general purpose arithmetic modules addition, subtraction, multiplier and divider based on 32 bit single precision IEEE-754 standard are designed and then DFT/IDFT algorithms architectures are implemented. The architectures of DFT and IDFT algorithms are based on radix 2 butterfly computations due to its less computation time .To reduce the required hardware resources, resource sharing scheme is used. Algorithms architectures are designed using hardware description language (VHDL), simulated using ModelSim6.6e tool and then hardware is implemented on Xilinx Virtex-5 LX110T board. . Digital Signal Processing 2012 17 Implementa tion of Adaptive FIR Filter for Pulse Doppler Radar Digital Signal Processing (DSP) systems involve a wide spectrum of DSP algorithms and their realizations are often accelerated by use of novel VLSI design techniques. Now-a-days various DSP systems are implemented on a variety of programmable signal processors or on application specific VLSI chips. This paper presents the design of Adaptive Finite Impulse Response (FIR) filter for moving target detection in various clutter conditions in Radar Receiver. The design uses pipelined COordinate Rotation DIgital Computer (CORDIC) unit and pipelined multiplier to get high system throughput and reduced latency in each of the pipelined stage. Saving area on silicon substrate is essential to the design of any pipelined CORDIC. The area reduction in proposed design can be achieved through optimization in the number of micro rotations. For better adaptation and performance of Adaptive Filters and to minimize quantization error, the numbers of iterations are also optimized. Digital Signal Processing 2012 18 FPGA Implementa tion of an Adaptive Filter Robust to Impulsive Noise: Two Approaches Adaptive filters are used in a wide range of applications such as echo cancellation, noise cancellation, system identification, and prediction. Its hardware implementation becomes essential in many cases where real-time execution is needed. However, impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms, particularly in specific hardware platforms. Fieldprogrammable gate arrays (FPGAs) are used widely for real-time applications where timing requirements are strict. Nowadays, two main design processes can be followed for embedded system design, namely, a hardware description language (e.g., VHDL) and a high-level synthesis design tool. This paper proposes the FPGA implementation of an adaptive algorithm that is robust to impulsive noise using these two approaches. Final comparison results are provided in order to test accuracy, performance, and logic occupation. Digital Signal Processing 2012 19 FPGA Implementa tion of Digital Up/Down Convertor for WCDMA System In this paper, we present FPGA implementation of a digital down convertor (DDC) and digital up convertor (DUC) for a single carrier WCDMA system. The DDC and DUC is complex in nature. The implementation of DDC is simple because it does not require mixers or filters. Xilinx System Generator and Xilinx ISE are used to develop the hardware circuit for the FPGA. Both the circuits are verified on the Virtex-4 FPGA. Digital Signal Processing 2012 20 Design and FPGA Implementa tion of Linear FIR Low-pass Filter Based on Kaiser Window Function Aiming at the requirements of real time signal processing, a cut-off frequency of 100 KHz, 16-tap direct form FIR linear-phase low-pass filter using Kaiser Window function was designed out based on DSP Builder system modeling approach. The signal waveforms in time domain and frequency domain before and after filtering were analyzed. Ultimately, a highest response frequency of 61.71MHz high-speed FIR low-pass filter was implemented on EP2C35F672C8 FPGA. Design efficiency and filter performance has been greatly improved. Digital Signal Processing 2012
  • 21 FPGA Implementa tion of Adaptive LMS Filter The adaptive filter constitutes an important part of the statistical signal processing. Whenever there is a requirement to process signals that result from operation in an environment of unknown statistics, the use of an adaptive filter offers an attractive solution to the problem as it usually provides a significant improvement in performance over the use of a fixed filter designed by conventional methods. Furthermore, the use of adaptive filters provides new signal-processing capabilities that would not be possible otherwise. We thus find that adaptive filters are successfully applied in such diverse fields as communications, control, radar, sonar, seismology, and biomedical engineering. Digital Signal Processing 2012 22 An event- driven FIR filter: design and Implementa tion Non-uniform sampling has proven through different works, to be a better scheme than the uniform sampling to sample low activity signals. With such signals, it generates fewer samples, which means less data to process and lower power consumption. In addition, it is well-known that asynchronous logic is a low power technology. This paper deals with the coupling between a non-uniform sampling scheme and an asynchronous design in order to implement a digital Filter. This paper presents the first design of a micropipeline asynchronous FIR filter architecture coupled to a non-uniform sampling scheme. The implementation has been done on an Altera FPGA board. Digital Signal Processing 2012 23 Area- Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutio ns Based on Fast FIR Algorithm Based on fast finite-impulse response (FIR) algorithms (FFAs), this paper proposes new parallel FIR filter structures, which are beneficial to symmetric coefficients in terms of the hardware cost, under the condition that the number of taps is a multiple of 2 or 3. The proposed parallel FIR structures exploit the inherent nature of symmetric coefficients reducing half the number of multipliers in subfilter section at the expense of additional adders in preprocessing and postprocessing blocks. Exchanging multipliers with adders is advantageous because adders weigh less than multipliers in terms of silicon area; in addition, the overhead from the additional adders in preprocessing and postprocessing blocks stay fixed and do not increase along with the length of the FIR filter, whereas the number of reduced multipliers increases along with the length of the FIR filter. For example, for a four-parallel 72-tap filter, the proposed structure saves 27 multipliers at the expense of 11 adders, whereas for a four-parallel 576-tap filter, the proposed structure saves 216 multipliers at the expense of 11 adders still. Overall, the proposed parallel FIR structures can lead to significant hardware savings for symmetric convolutions from the existing FFA parallel FIR filter, especially when the length of the filter is large. Digital Signal Processing 2012 24 Privacy Preserving Data Analytics for Smart Homes A framework for maintaining security & preserving privacy for analysis of sensor data from smart homes, without compromising on data utility is presented. Storing the personally identifiable data as hashed values withholds identifiable information from any computing nodes. However the very nature of smart home data analytics is establishing preventive care. Data processing results should be identifiable to certain users responsible for direct care. Through a separate encrypted identifier dictionary with hashed and actual values of all unique sets of identifiers, we suggest re-identification of any data processing results. However the level of re- identification needs to be controlled, depending on the type of user accessing the results. Generalization and suppression on identifiers from the identifier dictionary before re-introduction could achieve different levels of privacy preservation. In this paper we propose an approach to achieve data security & privacy through out the complete data lifecycle:data generation/collection, transfer, storage, processing and sharing. Big data 2013 25 Integrating remotely sensed and ground observation s for modeling, analysis, and decision support Earthquake science and emergency response require integration of many data types and models that cover a broad range of scales in time and space. Timely and efficient earthquake analysis and response require automated processes and a system in which the interfaces between models and applications are established and well defined. Geodetic imaging data provide observations of crustal deformation from which strain accumulation and release associated with earthquakes can be inferred.Data products are growing and tend to be either relatively large in size, on the order of 1 GB per image with hundreds or thousands of images, or high data rate, such as from 1 second GPS solutions. The products can be computationally intensive to manipulate, analyze, or model, and are unwieldy to transfer across wide area networks. Required computing resources can be large, even for a few users, and can spike when new data are made available or when an earthquake occurs. A cloud computing environment is the natural extension for some components of QuakeSim as an increasing number ofdata products and model applications become available to users. Storing the data near the model applications improves performance for the user Big data 2013