Computer Architecture: A quantitative approach - Cap4 - Section 3

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Computer Architecture: A quantitative approach - Cap4 - Section 3

  1. 1. Multiprocessors and Thread-Level Parallelism Performance of SSM Multiprocessors “ The overall cache performance is a combination of the behavior of uniprocessor cache miss traffic and the traffic caused by communication, which results in invalidations and subsequent cache misses.” Hennessy and Patterson
  2. 2. True sharing miss X False sharing miss
  3. 3. A Commercial Workload <ul><li>AlphaServer 4100 </li></ul><ul><li>300MHz, 3 level caches </li></ul><ul><li>3 Benchmarks </li></ul>
  4. 4. Performance of the Commercial Workload
  5. 5. Performance of the Commercial Workload
  6. 6. Performance of the Commercial Workload
  7. 7. Performance of the Commercial Workload
  8. 8. Performance of the Commercial Workload
  9. 9. A Multiprogramming and OS Workload <ul><li>2 level caches </li></ul><ul><li>2 copies of Andrew benchmark </li></ul><ul><li>Execution time is broken into 4 components: Idle, User, Synchronization and Kernel </li></ul>
  10. 10. Performance of the Multiprog. And OS Workload
  11. 11. Performance of the Multiprog. And OS Workload
  12. 12. Performance of the Multiprog. And OS Workload
  13. 13. Performance of the Multiprog. And OS Workload
  14. 14. Thank you! Author: Prof. Sergio Takeo, Marcelo Arbore. Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4 th Ed. Morgan Kaufmann Publishers. “ The overall cache performance is a combination of the behavior of uniprocessor cache miss traffic and the traffic caused by communication, which results in invalidations and subsequent cache misses.” Hennessy and Patterson

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