Multiprocessors and Thread-Level Parallelism Symmetric Shared-Memory Architectures “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson

Hardware Designers Motivation The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.

The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.

Multiprocessors Cache Coherence

Basic Schemes for Enforcing Coherence Directory Based Snooping

Directory Based

Snooping

The Snooping Protocols Write Invalidate Protocol Write Broadcast Protocol

Write Invalidate Protocol

Write Broadcast Protocol

Write Invalidate Protocol

An Example Protocol

An Example Protocol

An Example Protocol

SSM and Snooping Limitations As the number of processors in a multiprocessor grows, or as the memory demands of each processor grow, any centralized resource in the system can become a bottleneck.

As the number of processors in a multiprocessor grows, or as the memory demands of each processor grow, any centralized resource in the system can become a bottleneck.

SSM and Snooping Limitations

Implementing Snoopy Cache Coherence Race Situation: Have a winner is more important than who wins. Broadcast for all misses and some basic properties of the interconnection network. Ability to restart the miss handling of the loser in a race.

Race Situation: Have a winner is more important than who wins.

Broadcast for all misses and some basic properties of the interconnection network.

Ability to restart the miss handling of the loser in a race.

Thank you! Author: Prof. Sergio Takeo, Marcelo Arbore. Bibliography: Patterson, D. A.; Hennessy, J. L. Computer Architecture: A quantitative Approach, 4 th Ed. Morgan Kaufmann Publishers. “ The use of large, multilevel caches can substantially reduce the memory bandwidth demands of a processor.” Hennessy and Patterson