digital communication,micro processor,pulse and digital circuitsDocument Transcript
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8086 is the first 16-bit microprocessor from INTEL, released in the year 1978 . It is a
40 pin DIP chip based on N-channel, depletion load silicon gate technology(HMOS).
The term 16 bit means that its ALU,its internal registers and most of the instructions are
designed to work with 16 bit binary words.8086 is available at different clock speeds Viz,
5 M.Hz(8086);8M.Hz(8086-2) and 10(8086-1) M.Hz .8086 microprocessor has a 16-bit
data bus and 20-bit address bus. So, it can address any one of 220
byte memory locations. INTEL 8088 has the same ALU ,same registers and same
instruction set as the 8086.But the only difference is 8088 has only 8-bit data bus and
20-bit address bus. Hence the 8088 can only read/write/ports of only 8-bit data at a time
.The 8088 was used as the CPU in the original IBM personal computers [ IBMPC/XT]
.The 8086 microprocessor can work in two modes of operations .They are Minimum
mode and Maximum mode. In the minimum mode of operation the microprocessor do not
associate with any co-processors and can not be used for multiprocessor systems. But
in the maximum mode the 8086 can work in multi-processor or co-processor
configuration. This minimum or maximum operations are decided by the pin MN/
MX(Active low). When this pin is high 8086 operates in minimum mode otherwise it
operates in Maximium mode.
`1. 2 ARCHTECTURE OF 8086
To improve the performance by implementing the parallel processing concept the
CPU of the 8086 is divided into two independent sections .They are
1. Bus Interface Unit (BIU)
2. Execution Unit.(EI).
The BIU sendsout addresses ,fetches instructions ,read data from ports and memory and
writes data to ports and memory.i.e the BIU handles all transfers data and addresses on
the buses required by the execution Unit . Whereas the Execution Unit decodes the
instructions and executes the instructions
1.The Execution Unit : The Execution Unit consists of a control system , a 16-bit ALU,
16-bit Flag register and four general purpose registers(AX,BX,CX,DX), pointer registers
(SP,BP) and Index registers(SI,DI) of each 16-bits .
The control circuitry controls the internal operations .The decoder in the execution unit
decodes the instructions fetched from the memory into a series of actions. The ALU can
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add ,subtract, perform operations like logical AND,OR,XOR, increment, decrement,
complement ,and shifting the binary numbers.
2.Bus Interface Unit : The BIU consists of a 6-byte long instruction register called
Queue.And four stack segment registers (ES,CS,SS,DS) , one Instruction Pointer(IP)
and an adder circuit to calculate the 20bit physical address of a location. This bus
interface unit will perform all the external bus operations. They are fetching the
instructions from the memory, read/write data from/into memory or port and also
supporting the instruction Queue etc. The BIU fetches up to six instruction bytes from
the memory and stores these pre-fetched bytes in a first –in first out register set called
Queue. When the execution unit is ready for the execution of the instruction ,instead of
fetching the byte from the memory ,it reads the byte from the Queue .This will increase
the overall speed of microprocessor .Fetching the next instruction while the current
instruction executes is called pipelining or parallel processing.
Fig.2.1.Architecture of 8086 Microprocessor
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2.1 REGISTER ORGANISATION :
The 14 registers of 8086 microprocessor are categorized into four groups. They are
general purpose data registers , Pointer & Index registers , Segment registers and Flag
register as shown in the table below
Fig:3.1 8086 Microprocessor Registers.
General purpose registers:
There are four 16-bit 4 general purpose registers namely (AH, AL);(BH,BL); (CH,CL);
(and DH,DL) which are part of Execution unit. These registers can be used individually
for storing 16-bit data temporarily .The AL register is also called the accumulator. The
pairs of registers can be used together to store 16-bit data words. It is always
advantageous to store the data in these registers because the data can be accessed much
more easily as these registers are already in the execution unit. Here L indicates the
lower byte and H indicates the higher byte. X indicates the extended register. The general
purpose data registers are used for data manipulations. The use of these registers is more
dependent on the mode of addressing also.The other four registers of EU are referred
to as index / pointer registers. They are Stack Pointer register , Base Pointer register,
Source Index register and Destination Index registers. The pointer registers contain the
offset within a particular segment.
S.No Type Register width Name of the Registers
1 General purpose Registers(4)
2 Pointer Registers 16-bit
3 Index Registers 16-bit
4 Segment Registers
5 Instruction 16-bit Instruction Pointer (IP)
6 Flag (PSW) 16-bit Flag Register
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Fig 3.2 Register Organisation
The BP & SP registers holds the offsets within the data and stack segments respectively.
The Index registers are used as general purpose registers as well as for holding the offset
in case of indexed based and relative indexed addressing modes.The source Index register
is generally used to store the offset of source data in data segment while the Destination
Index register used to store the offset of destination in data or extra segment. These index
registers are specifically used in string manipulations.
Segment Registers :
There are four 16-bit segment registers namely
1.code segment register(CS)
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2.Stack segment register(SS)
3.Data segment register(DS)
4. Extra segment register(ES).
The code segment register is used for addressing the 64kB memory location in the code
segment of the memory ,where the code of the executable program is stored. Similarly
the DS register points to the data segment of the 64kB memory where the data is stored.
The Extra segment register also refers to essentially another data segment of the memory
space. The SS register is useful for addressing stack segment of memory. So, the
CS,DS,SS and ES segment registers respectively contains the segment addresses for the
code, data, stack and extra segments of the memory.
Instruction Pointer Register:
It is a 16-bit register which always points to the next instruction to be executed within
the currently executing code segment. So, this register contains the 16-bit offset address
pointing to the next instruction code within the 64kB of the code segment area. Its
content is automatically incremented as the execution of the next instruction takes place.
This register is also called status register. It is a 16 bit register which contains six status
flags and three control flags. So, only nine bits of the 16 bit register are defined and the
remaining seven bits are undefined. Normally this status flag bits indicate the status of
the ALU after the arithmetic or logical operations. Each bit of the status register is a
flip/flop. The Flag register contains Carry flag, Parity flag, Auxiliary flag Zero flag,
Sign flag ,Trap flag, Interrupt flag, Direction flag and overflow flag as shown in the
diagram. The CF,PF,AF,ZF,SF,OF are the status flags and the TF,IF and CF are the
X X X X OF DF IF TF SF ZF X AF X PF X CF
Fig:3.3 Flag Register
CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a
borrow in case of subtraction.
PF - Parity Flag : This flag is set to 1, if the lower byte of the result contains even number
of 1‘s else (for odd number of 1s ) set to zero.
AF- Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit
three during addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.
ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed
by the previous instruction is zero
SF- Sign Flag : This flag is set, when the result of any computation is negative
TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode.
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IF- Interrupt Flag: If this flag is set, the maskable interrupt INTR of 8086 is enabled and
if it is zero ,the interrupt is disabled.It can be set by using the STI instruction and can be
cleared by executing CLI instruction.
DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‗0‘,
the string is processed beginning from the lowest address to the highest address, i.e., auto
incrementing mode. Otherwise, the string is processed from the highest address towards
the lowest address, i.e., auto incrementing mode.
OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed
operation is large enough to accommodate in a destination register. The result is of more
than 7-bits in size in case of 8-bit signed operation and more than 15-bits in size in case
of 16-bit sign operations, then the overflow will be set.
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3.1 8086 PIN DIAGRAM – PIN DESCRIPTION
Intel 8086 is a 16-bit HMOS microprocessor. It is available in 40 pin DIP chip. It uses a
5V d.c. supply for its operation. The 8086 uses 20-line address bus. It uses a 16-line data
bus. The 20 lines of the address bus operate in multiplexed mode. The 16-low order
address bus lines are multiplexed with data and 4 high-order address bus lines are
multiplexed with status signals. The pin diagram of Intel 8086 is shown in Fig.4.
AD0-AD15 (Bidirectional) : Address/Data bus. These are low order address bus. They are
multiplexed with data. When AD lines are used to transmit memory address the symbol
A is used instead of AD, for example A0-A15. When data are transmitted over AD lines
the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15.
A16-A19 (Output) : High order address bus. These are multiplexed with status signals.
Fig.4.1: Pin Diagram of 8086 Processor
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A16/S3, A17/S4, A18/S5, A19/S6 : The specified address lines are multiplexed with
corresponding status signals.
BHE (Active Low)/S7 (Output) : Bus High Enable/Status. During T1 it is low. It is used
to enable data onto the most significant half of data bus, D8-D15. 8-bit device connected
to upper half of the data bus use BHE (Active Low) signal. It is multiplexed with status
signal S7. S7 signal is available during T2, T3 and T4.
RD (Read) (Active Low) : The signal is used for read operation. It is an output signal. It
is active when low.
READY : This is the acknowledgement from the slow device or memory that they have
completed the data transfer. The signal made available by the devices is synchronized by
the 8284A clock generator to provide ready input to the 8086. the signal is active high.
INTR-Interrupt Request : This is a triggered input. This is sampled during the last
clock cycles of each instruction to determine the availability of the request. If any
interrupt request is pending, the processor enters the interrupt acknowledge cycle. This
can be internally masked by resulting the interrupt enable flag. This signal is active high
and internally synchronized.
NMI (Input) –NON-MASKABLE INTERRUPT : It is an edge triggered input which
causes a type 2 interrupt. A subroutine is vectored to via an interrupt vector lookup table
located in system memory. NMI is not maskable internally by software. A transition
from LOW to HIGH initiates the interrupt at the end of the current instruction. This input
is internally synchronized.
INTA: INTA: Interrupt acknowledge. It is active LOW during T 2 ,T 3 and T w of each
interrupt acknowledge cycle.
MN/ MX MINIMUM / MAXIMUM :This pin signal indicates what mode the processor
is to operate in.
RQ/GT RQ/GT0 : REQUEST/GRANT: These pins are used by other local bus masters
to force the processor to release the local bus at the end of the processor's current bus
cycle. Each pin is bidirectional with RQ/GT having higher priority than RQ /GT1.
LOCK: Its an active low pin. It indicates that other system bus masters are not to
allowed to gain control of the system bus while LOCK is active LOW. The LOCK
signal remains active until the completion of the next instruction.
TEST : This input is examined by a ‗WAIT‘ instruction. If the TEST pin goes low,
execution will continue, else the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.
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CLK- Clock Input : The clock input provides the basic timing for processor operation
and bus control activity. Its an asymmetric square wave with 33% duty cycle.
RESET (Input) : RESET: causes the processor to immediately terminate its present
activity. The signal must be active HIGH for at least four clock cycles.
Vcc – Power Supply ( +5V D.C.)
GND – Ground
QS1,QS0 (Queue Status): These signals indicate the status of the internal 8086
instruction queue according to the table shown below
QSI QS0 Status
First Byte of Op Code from Queue
Empty the Queue
Subsequent Byte from Queue
DT/R : DATA TRANSMIT/RECEIVE: This pin is needed in minimum system that
desires to use an 8286/8287 data bus transceiver. It is used to control the direction of
data flow through the transceiver.
DEN: DATA ENABLE .This pin is provided as an output enable for the 8286/8287 in a
minimum system which uses the transceiver. DEN is active LOW during each memory
and I/O access and for INTA cycles.
HOLD/HOLDA : HOLD indicates that another master is requesting a local bus .This is
an active HIGH. The processor receiving the ``hold'' request will issue HLDA (HIGH)
as an acknowledgement in the middle of a T 4 or T 1 clock cycle.
3.2 MEMORY ORGANIZATION
The 8086 processor provides a 20-bit address toaccess any location of the 1 MB memory
space. The memory is organized as a linear array of 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into code, data, extra data, and
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stack segments of up to 64K bytes each . Physically, the memory is organized as a high
bank (D15 - D8) and a low bank (D7 –D0) of 512 K 8-bitbytes addressed in parallel by
the processor's address lines A19 -A1. Byte data with even addresses is transferred on the
D7 – D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the D15-
D8 bus lines. The processor provides two enable signals, BHE and A0 , to selectively
allow reading from or writing into either an odd byte location, even byte location, or
both. The instruction stream is fetched from memory as words and is addressed internally
by the processor to the byte level as necessary.
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An interrupt to the microprocessor is defined as that which disturbs the normal execution
of a program . Broadly the interrupts are divided into two types. They are
1.external hardware Interrupts
2. internal (Software) Interrupts .
The hardware interrupts are classified in to two types.they are
1. non-maskable interrupts.
2. maskable interrupts
The hardware interrupt is caused by any peripheral device by sending a signal through a
specified pin to the microprocessor. Whereas internal interrupts are initiated by the state
of the CPU (e.g. divide by zero error) or by an instruction. So, the software interrupt is
one which interrupts the normal execution of a program of the microprocessor.
The 8086 has two hardware interrupt pins namely NMI and INTR.In the two ,the NMI
is a non-maskable interrupt and the INTR interrupt request is a maskable interrupt
which has lower proirity .The third pin associated with the hardware interrupts are the
INTA called interrupt acknowledge.
NMI : The processor provides a single non-maskable interrupt pin (NMI) which has
higher priority than the maskable interrupt request pin (INTR). A typical use would be to
activate a power failure routine. The NMI is edge-triggered on a LOW-to-HIGH
transition. The activation of this pin causes a type 2 interrupt.
INTR: The 8086 provides a single interrupt request input (INTR) which can be masked
internally by software with the resetting of the interrupt enable FLAG status bit. The
interrupt request signal is level triggered. It is internally synchronized during each clock
cycle on the high-going edge of CLK. To be responded to, INTR must be present (HIGH)
during the clock period preceding the end of the current instruction or the end of a whole
move for a block type instruction.
Software Interrupts: Coming to the software interrupts , 8086 can generate 256
interrupt types through the instruction INT n .Any of the 256 interrupt types can be
generated by specifying the interrupt type after INT instruction . For example INT 33
will cause type 33 interrupt.
I k Bytes of memory from 00000H to 003FF H is set aside to store
the starting address of the Interrupt service sub-routine(ISS) programs in an 8086 based
systems. To store the starting address of the each ISS , four bytes of memory space is
required.Two bytes are for storing CS value and two bytes for IP value. The starting
address of an ISS stored in 1kB of memory space is called Interrupt pointer or Interrupt
vector.The 1kB memory space acts as a table and it is called Interrupt Vector
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The 256 interrupt pointers have been numbered from 0 to 255.The
number given to an interrupt pointer denotes the type of the interrupt. For example
Type0,Type1,Type2 etc…The starting address of the ISS for type0 interrupt is
000000H.For type1 interrupt is 00004H similarly for type2 is 00008H ……In the IVT
the first five pointers are dedicated interrupt pointers. They are :
TYPE 0 :Interrupt corresponds to divide by zero situation.
TYPE 1: Interrupt corresponds to Single step execution during the debugging of a
TYPE 2: Interrupts to non-maskable NMI interrupt.
TYPE 3 :Interrupt corresponds to break point interrupt.
TYPE 4 :Interrupt corresponds to Overflow interrupt.
The Interrupts from Type 5 to Type 31 are reserved for other advanced
microprocessors,and from 32 to Type 255 are available for hardware and software
Differences between CALL and INT : In fact both the instructions CALL and INT n
will interrupt the execution of the main program. But there are certain differences
between their functioning. They are given below in the table.
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S.No CALL Instruction INTn instruction
1 Upon the execution ,the
control will jump to any one
of the 1 MB of memory
Upon execution the control
will jump to a fixed location
in the vector table.
2 The user can insert in the
sequence of instructions of a
Can occur at any time
activated by hardware
3 Once initiated it cannot be
Can be masked
4 When initiated ,it stores the
CS:IP of the next instruction
on the stack
When initiated ,it stores the
CS:IP of the next instruction
and also the flag register on
5 The last instruction of the
subroutine will be RET
The last instruction of the
ISS will be IRET
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5.1 ADDRESSING MODES
The different ways in which a source operand is denoted in an instruction are known as
the addressing modes. There are 8 different addressing modes in 8086 programming.
They are :
1. Immediate addressing mode
2. Register addressing mode
3. Direct addressing mode
4. Register indirect addressing mode
5. Based addressing mode
6. Indexed addressing mode.
7. Based indexed addressing mode
8. Based, Indexed with displacement.
1.Immediate addressing mode: The addressing mode in which the data operand is a
part of the instruction itself is called Immediate addressing mode.
For Ex: MOV CX, 4847 H
ADD AX, 2456 H
MOV AL, FFH
2.Register addressing mode : Register addressing mode means, a register is the source
of an operand for an instruction.
For Ex : MOV AX, BX copies the contents of the 16-bit BX register into the 16-bit AX
EX : ADD CX,DX
3.Direct addressing mode: The addressing mode in which the effective address of the
memory location at which the data operand is stored is given in the instruction.i.e the
effective address is just a 16-bit number is written directly in the instruction.
For Ex: MOV BX, [1354H]
. The square brackets around the 1354 H denotes the contents of the memory location.
When executed, this instruction will copy the contents of the memory location into BX
register. This addressing mode is called direct because the displacement of the operand
from the segment base is specified directly in the instruction.
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4.Register indirect addressing mode: Register indirect addressing allows data to be
addressed at any memory location through an offset address held in any of the following
registers: BP, BX, DI and SI.
Ex: MOV AX, [BX]. Suppose the register BX contains 4675H ,the contents of the
4675 H are moved to AX.
5.Based addressing mode: The offset address of the operand is given by the sum of
contents of the BX or BP registers and an 8-bit or 16-bit displacement.
Ex: MOV DX, [BX+04]
6.Indexed Addressing mode: The operands offset address is found by adding the
contents of SI or DI register and 8-bit or 16-bit displacements.
Ex: MOV BX,[SI+06]
7.Based -index addressing mode: The offset address of the operand is computed by
summing the base register to the contents of an Index register.
Ex: ADD CX,[BX+SI]
8.Based Iindexd with displacement mode: The operands offset is computed by adding
the base register contents, an Index registers contents and 8 or 16-bit displacement.
Ex : MOV AX,[BX+DI+08]
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6.1 INSTRUCTION SET OF 8086:
The 8086 microprocessor supports 6 types of Instructions. They are
1. Data transfer instructions
2. Arithmetic instructions
3. Bit manipulation instructions
4. String instructions
5. Program Execution Transfer instructions (Branch & loop Instructions)
6. Processor control instructions
1. Data Transfer instructions :
These instructions are used to transfer the data from source operand to destination
operand. All the store, move, load, exchange ,input and output instructions belong to to
General purpose byte or word transfer instructions:
MOV : This instruction copies a word or a byte of data from some source to a destination.
This destination can be a register or a memory location. The source can be a register, a
memory location or an immediate number.
Direct loading of the segment registers with immediate data is not permitted
PUSH : Push to stack
This instruction pushes the contents of the specified register/memory location on to the stack.
The stack pointer is decremented by 2, after each execution of this instruction
POP : Pop from stack. This instruction when executed, loads the specified
register/memory location with the contents of the memory location of which the address is
formed using the current stack segment and stack pointer. The stack pointer is incremented
by 2. Example
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PUSHA : Push all registers to the stack
POPA : Pop the words from stack to all registers
XCHG : Exchange byte or word
This instruction exchange the contentrs of a specified source and destination
XCHG [5000H], AX
XLAT : Translate a byte in AL using a table in memory.
LEA BX, TABLE1
MOV AL, 04H
Simple input and output port transfer instructions
IN : Reads a byte or word from specified port to the accumulator.
IN AL, 03H
IN AX, DX
OUT : Sends out a byte or word from accumulator to a specified port.
OUT 03H, AL
OUT DX, AX
Special address transfer instructions
LEA : Load effective address of operand into specified register
LEA reg, offset
LDS : Load DS register and other specified register from memory.
[DS] [mem +2]
Eg. LDS reg, mem
LES : Load ES register and other specified register from memory.
[reg] [mem +2]
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LES reg, mem
3.Flag transfer registers
LAHF : Load AH with the low byte of the flag register
[AH] <---- [Flags low byte]
SAHF : Store AH register to low byte of flag register.
[Flagslowbyte] <---- [AH]
PUSHF : Copy flag register to top of the stack .
POPF : Copy word at top of the stack to flag register.
[SP] <--- [SP+2]
2. Arithmetic instructions : These instructions are used to perform various
mathematical operations like addition, subtraction, multiplication and division etc….
1.ADD : Add specified byte to byte or word to word . The add instruction adds the
contents of the source operand to the destination operand
2.ADC : Add with carry. This instruction performs the same operation as the add
instruction, but adds the carry flag to the result.
3.INC : Increment specified byte or specified word by 1.
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4.AAA : ASCII adjust after addition. The AAA instruction is executed after an ADD
instruction that adds two ASCII coded operand to give a byte of result in AL . The AA
ADD CL,DL ; [CL] = 32H = ASCII for 2 , [DL] = 35H = ASCII for 5, Result [CL] =
MOV AL, CL ; move ASCII result into AL since AAA adjust only [ AL]
AAA ; [AL] = 07, unpacked BCD for 7
A instruction converts the resulting contents of AI to a unpacked decimal digit.
5.DAA : Decimal (BCD) adjust after addition.
SUB : Subtract byte from byte or word from word. Subtract
The subtract instructiion subtracts the source operand from the destination operand and the
result is left in the destination operand.
SUB [5000H], 0100H
SBB : Subtract with borrow. The subtract with borrow instruction subtracts the source
operand and the borrow flag (CF) which may reflect the result of the previous calculations,
from the destination operand.
SBB [5000H], 0100H
DEC : Decrement specified byte or word by 1. The decrement instruction subtract 1 from
the contents of the specified register or memory location.
NEG : Negate or invert each bit of a specified byte or word and add 1(2‘s complement).
The negate instruction forms 2's complement of the specified destination in the instruction.
The destinatiopn can be a register or a memory location . This instruction can be
implemented by inverting each bit and adding 1 to it.
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AL= 00110101 35H Replace number in AL with its 2's complement
AL = 1100 1011 = CBH
CMP : Compare two specified byte or two specified words. This instruction compares
the source operand, which may be a register or a memory location, with a destination operand
that may be a memory location.
CMP BX, CX
AAS : ASCII adjust after subtraction.
DAS : Decimal adjust after subtraction
MUL : Multiply unsigned byte by byte or unsigned word or word.
IMUL : Multiply signed bye by byte or signed word by word.
AAM : ASCII adjust after multiplication.
1.DIV : Divide unsigned word by byte or unsigned double word by word.
DIV CL ; word in AX / byte in CL ,quotient im AL , remainder in AH.
DIV CX ; Double word in DX and AX / word in CX and Quotient in AX , remainder in DX
2.IDIV : Divide signed word by byte or signed double word by word.
3.AAD : ASCII adjust after division. This instruction converts two unpacked BCD digits
in AH and AL to the equivalent binary number in AL. This adjustment must be done
before dividing the two unpacked BCD digits in AX by an unpacked BCD byte. IN the
instruction sequence , this instruction appears before DIV instruction.
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AX 05 08
AAD result in AL 00 3A; 58D= 3A h in AL
4.CBW : Fill upper byte of word with copies of sign bit of lower byte.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is
AX = 0000 0000 1001 1000 Convert signed byte in AL signed word in AX
Result in AX = 1111 1111 1001 1000then said to be sign extension of AL.
5.CWD : Fill upper word of double word with sign bit of lower word.
This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be a
signed extension of AL
Convert signed word in AX to signed double word in DX : AX
DX = 1111 1111 1111 1111
Result in AX = 1111 0000 1100 0001
3. Bit Manipulation instructions :
These instructions include logical , shift and rotate instructions in which a bit of the data
(a) Logical instructions
1.NOT :Invert each bit of a byte or word.
2AND : ANDing each bit in a byte or word with the corresponding bit in another byte or
3. OR : ORing each bit in a byte or word with the corresponding bit in another
byte or word.
4.XOR : Exclusive OR each bit in a byte or word with the corresponding bit in another
byte or word.
5.TEST :AND operands to update flags, but don‘t change operands.
(b) Shift instructions
1.SHL/SAL : Shift bits of a word or byte left, put zero(S) in LSBs.
2.SHR : Shift bits of a word or byte right, put zero(S) in MSBs.
3.SAR : Shift bits of a word or byte right, copy old MSB into new MSB.
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Conditional transfer instructions
JA/JNBE : Jump if above / jump if not below or equal
JAE/JNB : Jump if above /jump if not below.
JBE/JNA : Jump if below or equal/ Jump if not above.
JC : jump if carry flag CF=1.
JE/JZ : jump if equal/jump if zero flag ZF=1.
JG/JNLE : Jump if greater/ jump if not less than or equal.
JGE/JNL : jump if greater than or equal/ jump if not less than.
JL/JNGE : jump if less than/ jump if not greater than or equal.
JLE/JNG : jump if less than or equal/ jump if not greater than.
JNC : jump if no carry (CF=0).
JNE/JNZ : jump if not equal/ jump if not zero(ZF=0).
JNO : jump if no overflow(OF=0).
JNP/JPO : jump if not parity/ jump if parity odd(PF=0).
JNS : jump if not sign(SF=0).
JO : jump if overflow flag(OF=1).
JP/JPE : jump if parity/jump if parity even(PF=1).
JS : jump if sign(SF=1).
6.Iteration control instructions
These instructions are used to execute a series of instructions for certain number of
LOOP :Loop through a sequence of instructions until CX=0.
LOOPE/LOOPZ : Loop through a sequence of instructions while ZF=1 and CX = 0.
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LOOPNE/LOOPNZ : Loop through a sequence of instructions while ZF=0 and CX =0.
JCXZ : jump to specified address if CX=0.
7. Interrupt instructions
INT : Interrupt program execution, call service procedure.
INTO : Interrupt program execution if OF=1.
IRET : Return from interrupt service procedure to main program.
8.High level language interface instructions
ENTER : enter procedure
LEAVE :Leave procedure.
BOUND : Check if effective address within specified array bounds
9.Processor control instructions
Flag set/clear instructions
STC : Set carry flag CF to 1
CLC : Clear carry flag CF to 0
CMC : Complement the state of the carry flag CF
STD : Set direction flag DF to 1 (decrement string pointers)
CLD : Clear direction flag DF to 0
STI : Set interrupt enable flag to 1(enable INTR input)
CLI : Clear interrupt enable Flag to 0 (disable INTR input)
10. External Hardware synchronization instructions
HLT : Halt (do nothing) until interrupt or reset
WAIT : Wait (Do nothing) until signal on the test pin is low
ESC : Escape to external coprocessor such as 8087 or 8089
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LOCK : An instruction prefix. Prevents another processor from taking the bus while the
adjacent instruction executes.
11. No operation instruction
NOP : No action except fetch and decode
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7.1 ASSEMBLER DIRECTIVES :
Assembler directives are the directions to the assembler which indicate how an
operand or section of the program is to be processed. These are also called pseudo
operations which are not executable by the microprocessor.
The various directives are explained below.
1. ASSUME : The ASSUME directive is used to inform the assembler the name of the
logical segment it should use for a specified segment.
Ex: ASSUME DS: DATA tells the assembler that for any program instruction which
refers to the data segment ,it should use the logical segment called DATA.
2.DB -Define byte. It is used to declare a byte variable or set aside one or more storage
locations of type byte in memory.
For example, CURRENT_VALUE DB 36H tells the assembler to reserve 1 byte of
memory for a variable named CURRENT_ VALUE and to put the value 36 H in that
memory location when the program is loaded into RAM .
3. DW -Define word. It tells the assembler to define a variable of type word or to reserve
storage locations of type word in memory.
4. DD(define double word) :This directive is used to declare a variable of type double
word or restore memory locations which can be accessed as type double word.
5.DQ (define quadword) :This directive is used to tell the assembler to declare a variable
4 words in length or to reserve 4 words of storage in memory .
6.DT (define ten bytes):It is used to inform the assembler to define a variable which is 10
bytes in length or to reserve 10 bytes of storage in memory.
7. EQU –Equate It is used to give a name to some value or symbol. Every time the
assembler finds the given name in the program, it will replace the name with the value or
symbol we have equated with that name
8.ORG -Originate : The ORG statement changes the starting offset address of the data.
It allows to set the location counter to a desired value at any point in the program.For
example the statement ORG 3000H tells the assembler to set the location counter to
9 .PROC- Procedure: It is used to identify the start of a procedure. Or subroutine.
10. END- End program .This directive indicates the assembler that this is the end of the
program module.The assembler ignores any statements after an END directive.
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11. ENDP- End procedure: It indicates the end of the procedure (subroutine) to the
12.ENDS-End Segment: This directive is used with the name of the segment to indicate
the end of that logical segment.
Ex: CODE SEGMENT : Start of logical segment containing code
CODE ENDS : End of the segment named CODE.
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1.1 LINEAR WAVE SHAPING
Timing circuits networks composed of resistors, capacitors and inductors are called linear
network and they do not change the waveform of a sine wave when it is transmitted
through them. On the other hand when non-sinusoidal waveforms, (e.g. step, ramp,
exponential) are applied to the input of such networks the output signal may have very
little resembles with the input waveform. The action of a linear network in producing a
waveform at its output different from its input is called linear wave shaping. The wave
shaping is used to perform any one of the following functions.
1. To hold the waveform to a particular d.c. level.
2. To generate one wave form the other
3. To limit the voltage level of the waveform of some presenting value and
suppressing all other voltage levels in excess of the present level.
4. To cut-off the positive and negative portions of the input waveform.
Shaping circuits may be either series RC or series RL circuits. The series RC and RL
circuits electrically perform the mathematical operation of integration and differentiation.
Therefore, the circuits used to perform these operations are called integrators and
differentiator. The differentiator circuits are used to generate sharp narrow pulses either
from distorted pulse waveform or from rectangular wave forms. The integrator circuits
are required to generate a voltage, which are required to generate a voltage, which
increases or decreases linearly with time.
Any waveform whose shape is different from that of sinusoidal wave is called a non-
sinusoidal waveform. For example pulse square, symmetrical square triangular and saw-
tooth are non-sinusoidal waves. When one quantity is dependent upon some other
variable quantity varies with respect to others. In case of electronic circuits function
usually means that current or voltage varies with respect to time. All these waveform are
the function voltage or current with respect to time such as step, ramp and exponential are
explained as under:
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A step function shown in Fig. 1(a), makes an instantaneous jump from one steady value
to another steady value. A step means an instantaneous change in level.
Fig: step function
In such a case, voltage maintains zero value for all times t < 0 and maintains the value V
for all times t > 0 is called a step voltage.
A ramp function shown in Figure 1(b) isone that voltage increases or decreases linearly
with time. Slope of the function is constant. In such a case, voltage is zero for t < 0 and
increases linearly with time for t > 0.it is linear change in function with respect to time
called a ramp.
An exponential function is a function of voltage that increases or decreases exponentially
with time. In such a case, voltage is zero for t < 0 and increases nonlinearly with time t
called an exponential voltage. The terms used for exponential are ex
quantity gap is known as an exponential curve
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Fig: exponential function
1.2 Different Types of Waveforms
Let us now discus the pulse square, symmetrical square, Triangular and saw-tooth
Figure 2(a) shows the waveform of an ideal pulse. The pulse amplitude is V and the pulse
duration is tp. It is evident from Fig. 2(b) and (c) that the pulse may be considered as the
sum of the step voltage +V, whose discontinuity occur at t = 0 and a step voltage —V,
whose discontinuity occurs at t = tp. The pulse waveform find extensive use is almost
every field of electronics such as communication, computer, defense equipment, etc.
A waveform which maintains itself at one constant voltage level V1 for a time T1 and at
another constant level V2 for time T2 and is repetitive with a period T = T1 + T2 as shown
in Fig. 2 (a) is called a square waveform. The square waveform is used in digital
electronic circuits, radars and as synchronizing pulses in television.
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A waveform which increase linearly with time to a voltage level V for a time T/2 and
then decreases linearly to its original level for a time T/2 and is repetitive with a period T
as shown in Fig. 4(a) is called triangular waveform. It may be noted from this figure, that
a triangular wave may be considered as the sum of ramp voltage, which incre.ases at a
rate of 2V/T for a time T/2 and the ramp voltage which decreases at a rate of —2V/T for
the remaining time T/2. The triangular waveform is used in scanning circuits, where a
uniform left-to-right scan is required as in computer displays. These are also used in
timing circuit for electronics applications
A waveform increases linearly with time to a voltage level V for a time T and then
changes abruptly to its original level and is repetitive as shown in Fig. 4(b) is called
sawtooth waveform. It is also called sweep waveform or time-base waveform. The
sawtooth waveform is used in the scanning circuit of cathode ray oscilloscopes and
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Fig:Saw tooth waveform
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2.1 Clipping circuits
A clipper is a device which limits, remove or prevents some portion of the wave form
(input signal voltage) above or below a certain level In other words the circuit which
limits positive or negative amplitude ,or both is called chipping circuit. The clipper
circuits are of the following types.
1. Series positive clipper
2. Series negative clipper
3. Shunt or parallel clipper
4. Shunt or parallel positive negative
5. Clipper Dual (combination)Diode clipper
2.1.1 SERIES POSITIVE CLIPPER:
In a series positive clipper, a diode is connected
in series with the output, as shown in Fig 1(a). During the positive half of the input
voltage, the terminal A is positive with respect to B. This reverse biases the diode and it
acts as an open switch Therefore all the applied voltage drops across the diode and none
across the resistor As a result of this there is no output voltage during the positive half
cycle of the input voltage
During the negative half cycle of the input voltage the terminal B is positive with respect
to A. Therefore it forward biases the diode and it acts as a closed switch. Thus there is on
voltage drop across diode during the negative half cycle of the input voltage. All the input
voltage is dropped across the resistor as shown in the output wave form
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Clippers prevent either or both polarities of a wave form exceeding a specific amplitude
level. However a positive Clipper is that which removes or clips the positive half
completely. Hence the circuit of the Fig 2.1 is called a positive Clipper Here it may he
noted the diode acts a series switch between the source and load. Due to this reason the
circuit is called series positive clipper.
(a) SERIES-POSITIVE CLIPPER WITH BIAS:
Sometimes it is desired to remove a Small portion of positive or
apposite halt cycle of the signal voltage (input signal). For this purpose a biased clipper is
used Fig 2 shows the circuit of a biased series positive clipper
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It may be observed that the clipping takes place during the positive cycle only when the
input voltage is greater thence battery voltage (i.e. Vi > VB). The chipping level can be
shifted up or down by varying the bias voltage (VB)
2.1.2 SERIES NEGATIVE CLIPPER:
In a series negative clipper a diode is connected in a direction
appositive to that of a positive clipper Fig 3 shows the circuit of a negative clipper
During the positive half cycle pf the voltage, the terminal A is positive with respect to the
terminal B There for the diode is forward biased and it acts it as a closed switch As a
result ,all the input voltage appears across the resistor as shown in Fig 3(b). During the
negative half cycle of the input voltage, the terminal B is positive with respect to the
terminal A. Therefore the diode is reverse biased and it acts as an open switch, Thus there
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is no voltage drop across the resistor during the negative half cycle as shown in the output
It may be observed that if it is desired to remove or clip the negative half -cycle of the
input , the only thing is to be done is to reverse the polarities of the diode in the circuit
shown in Fig 1 such a clipper is then called a series negative clipper
(a) SERIES-NEGATIVE CLIPPER WITH BIAS:
Fig 4 shows the circuit of a biased series negative diver. In this circuit clipping take place
during the negative half cycle only when the input voltage Vi > VB she clipping level can
be shifted up or down by varying the bias voltage ( -VB)
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2.1.3 SHUNT OR PARALLEL POSITIVE CLIPPER:
A parallel clipper circuit uses the same diode
theory and circuit operation a resistor and diode are connected in series with the input
signal and the output signal is developed across the diode. The output is in parallel with
the diode hence the circuit name parallel clipper the parallel clipper can limit either the
positive or negative alternation of the input signal Fig 5 shows the circuit of a shunt
positive clipper In this circuit. The diode acts as a closed switch when the input voltage is
positive (i.e. Vi > 0 and as an open switch when the input voltage is negative (i.e. Vi< 0)
the output waveform is the same as that of a series positive clipper in the parallel clippers
the alp will develop when the diode is cut off
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(a) SHUNT OR PARALLEL POSITIVE CLIPPER WITH BIAS:
As is in Fig 6 (a), positive terminal of the battery is connected to the cathode of the diode.
This causes the diode to be reversed biased at all times except when the input signal is
more positive the bias voltage(i e Vi > VB). it will be interesting to know that if the
polarity of the bias voltage is reversed , the resulting circuits will be as shown in Fig 6(b)
Here the input signal lying above the voltage —VB is clipped the waveforms of the of the
output voltage are also shown with figures
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2.1.4 SHUNT OR PARALLEL NEGATIVE CLIPPER:
The negative clipper has allowed to pass the positive half cycle of the input
voltage and clipped the negative half cycle completely Fig 7 shows the shunt (parallel)
In such a circuit the diode acts as a closed switch for a negative input voltage (i.e. Vi < O)
and as an open switch for a positive input voltage (i.e. Vi O) the output waveform of the
Circuit is the same as that of series negative clipper.
(a) SHUNT OR PARALLEL NEGATIVE CLIPPER WITH BIAS
In such a circuit clipping take place during the negative half cycle only when the
input voltage (Vi < VB) the clipping level can be shifted up or down by varying the bias
voltage (—VB). It will be interesting to know that if the polarity of the bias voltage is
reversed, then the resulting circuits will be as shown in Fig 8 (b) Here the entire signal
below the voltage level VII has been clipped off
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2.1.5 DUAL (COMBINATION) DIODE CLIPPER
The type of clipper combines a parallel negative clipper with negative bias (D1 and B2)
and a parallel positive bias (D1 and B1). Hence the combination of a biased positive
clipper and a biased negative clipper is called combination or dual diode clipper. Such a
clipper circuit can clip at both two in dependent levels depending upon the bias voltages.
Fig 9(a) show the circuit of a dual (combination) clipper
Let us suppose a sinusoidal ac voltage is applied at the input terminals of the circuit.
Then during the positive half cycle, the diode D1 is forward biased, while diode D2 is
reverse. biased. Therefore the diode D1 will conduct and will acts as a short circuit. On
the other hand, diode
D2will acts as an open circuit. However, the value of output voltage cannot exceed the
voltage level of VB1 as Shown in Fig 9.
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Similarly during the negative input half cycle the diode D2 acts as a short circuit while the
diode D1 as an open circuit However the value of output voltage cannot exceed the
voltage level of VB2 It may be noted that the clipping levels of the circuit be varied by
changing the values of VB1 and VB2 If the values of VB1 and VB2 are equal, the circuit will
clip both the positive and negative half cycles at the same voltage level. Such a circuit is
known as a symmetrical clipper.
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Certain applications in electronics require that the upper or lower extremity of a wave be
fixed at a specific value In such applications ,a clamping/clamper circuits are used.
A circuit that places either the positive or negative peak of a signal at a desired D.C level
is known as a clamping circuit. A clamping circuit introduces (or restores) a D.C level to
an A.C signal. Thus a clamping circuit is also known as D.C restorer, or D.C reinserted or
a baseline stabilizer. The following are two general types of clamping.
1. Positive clamping occurs when negative peaks raised or clamped to ground or on
the zero level In other words, it pushes the signal upwards so that negative peaks
fall on the zero level.
2. Negative clamping occurs when positive peaks raised or clamped to ground or on
the zero level In other words, it pushes the signal downwards so that the positive
peaks fall on the zero level.
In both cases the shape of the original signal has not changed, only there is vertical shift
in the signal Fig. 1 shows the clamping wave form.
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3.1 Diode clampers
3.1.1 POSITIVE CLAMPER
Fig 2 shows the circuit of a positive clamper It consists of a diode and a capacitor the
clamper output is taken across the load resistance R.
During the negative half cycle of the input voltage, the diode conducts heavily and
behaves as a closed switch At the negative peak, the capacitor is charged to maximum
voltage V slightly beyond the negative peak, the diode is shunt off and the capacitor
charged to Vm behaves as a battery during the positive half cycle of the input signal. The
diode is reversed biased and the output voltage will be equal to Vm + V this gives
positive clamped voltage and is called positive clamper circuit.
Positive clamper with bias
Biased clamper circuit operates in exactly the same manner as unbiased clampers. The
different is only that a dc bias voltage is add in series with the diode and resistor. A
biased clamper means that the clamping can be done at any voltage level other than zero
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Fig 3(a) shows the circuit of positive clamper with positive biased Here a battery of
10 V is added in such a way that the clamping take place positively at 10V. Similarly, it
is possible to clamp the input wave form positively at -10V by reversing the battery
connections as shown in Fig 3(b).
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3.1.2 NEGATIVE CLAMPER
Fig 4 shows the circuit of a negative clamper during the positive half cycle of the input
signal, the capacitor is charged to Vm, with the polarity shown in Fig 4. Observe that
voltage across the capacitor is opposing the input voltage V. This gives negative clamped
voltage and is called negative clamper circuit.
Negative Clamper With bias
Fig 5 (a) shows the circuit of negative clamper with positive bias. With no input signal
the capacitor charges to the battery voltage and the output is positive because the negative
side of the batter is grounded. The output waveform is clamped to +10V, the value of the
battery. Since this is a negative clamper (cathode to ground), the top of the output wave
touch the +10V reference line
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Similarly it is possible to clamp the input waveform negatively at by reversing the
battery connections as shown in Fig 5(b)
3.2 ASYNCHRONOUS AND SYNCHRONOUS CLAMPING
Clamping circuit discussed above are example of clamping circuit in which the time
during which the clamping is effective is controlled by the signal itself is called non
synchronous or Asynchronous On the other hand, When the time of clamping is not
determined directly by the signal but is determined rather by an auxiliary voltage. Such
circuits are called synchronous clamping circuit. For example, suppose the wave form of
Fig 6(a) is to be used to displace the beam of a cathode-ray tube linearly with time, first
in one direction and then in other direction from some fixed initial point. If the signal is
transmitted through - an ac coupling network whose. low -frequency time constant is not
very large in comparison with the time interval T1, signal will distort as shown in Fig, 6
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(b). The cause defect in the waveform is that the two displacements will start for different
point A and B Also the d c level VR is lost
if however, the signal is passed through the circuit of Fig 7 and if switch S is closed
during time interval T2 and is open during time T1, the wave form will receive as in Fig
6(c) The pips which appear when the voltage returns to the level R will be reduced to'
infinitesimally narrow spikes as the resistance of the switch Rf approaches zero.
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It is needed that the switch S be open throughout the time interval T1, but it is not
necessary that thy switch be closed of the entire interval T2. It is only needed that the
switch be closed for a period long enough to allow the capacitor C to acquire or lose
enough charge to bring the output terminal to the reference level VR
3.3 TRANSISTOR CLAMPING
Let us consider an amplifier circuit in which fixed current bias is obtained by connecting
a resistor RB from the base to the supply voltage as shown in Fig 8. If the signal swing is
small then base to emitter junction always conduct. The emitter base junction voltage
remains forward -biased and the transistor behaves just like a small signal class-A
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On the other hand, it a large amplitude signal is employed. Clamping will take place at
the positive extremities of the wave form and transistor will operate below the cut-off
during a portion of each cycle If the transistor goes in to saturation in the absence of a
signal, by the combination of Vcc and RB it means that transistor is driven between cut-
off and saturation by an external signal the input and output waveform arc also shown
with the circuit.
3.4 USES OF CLAMPING CIRCUITS
Clamping circuit are used to shift any part of the input signal waveform and can be
maintained at a specified voltage level Such circuit are used in television receivers to
restore the original d.c reference signal (corresponding to the brightness level of the
picture) to the video Signal The clamping of peak (i.e. 2Vm, 3Vm, 4Vm etc.,) Such to
circuit are known as voltage multipliers These circuit are used to supply power to thigh
voltage/low current devices like cathode ray tubes used in Television receivers,
oscilloscopes and computer displays.They used in analogue video processing to define
portions of the luminance waveform (black level, sync pulses etc.) to pre-determined
voltage levels. Also previously used as a method of modulating vacuum tube AM
transmitters, e.g. a tetrode power amplifier tube being screen modulated by a triode clamp
Voltage multiplier is a circuit which produces an output d.c voltage whose value is a
multiple of peak a.c input voltage (i.e., 2Vm, 3Vm, 4Vm and so on). SILK circuits are
used as a power supply for high voltage/low current device like cathode ray tube. Voltage
multiplier is a modified capacitor filter circuit that delivers a dc voltage twice or
rnore times of the peak value (amplitude) of the input ac voltage. Such power
supplies are used for high-voltage and low-current devices such as cathode-ray tubes
(the picture tubes in TV receivers, oscilloscopes and computer display). Here we will
consider half-wave voltage doubler, full-wave voltage doubler and voltage tripler and
Half-Wave Voltage Doubler:
The circuit of a half-wave voltage doubler is given in figure shown below. During the
positive half cycle of the ac input, voltage, diode D1 being forward biased conducts
(diode D2 does not conduct because it is reverse-biased) and charges capacitor
C1 upto peak values of secondary voltage Vsmax with the polarity, as marked in figure
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During the negative half-cycle of the input voltage diode D2 gets forward biased and
conducts charging capacitor C2. For the negative half cycle, the lower end of the
transformer secondary is positive while upper end is negative. The polarity of the
capacitor C2 has also been marked in the figure. Now starting from the bottom of the
transformer secondary and moving clockwise and applying Kirchhoffs voltage law to
the outer loop
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A comparator is a device which is used to sense when an arbitrary varying signal reaches
some threshold or reference level. Comparators find application in many electronics
systems: for example, they may be used to sense when a linear ramp reaches some
defined voltage level, or to indicate whether or not a pulse has an amplitude greater than
a particular value. Provided that suitable output limiting is provided, comparator outputs
may be used to drive logic circuits.
The Schmitt trigger is an important switching circuit that is widely used in digital
systems. Its stable state is determined by the amplitude of the input voltage. For a given
circuit two finite values of input voltages, called the upper trip point (UTP) and the lower
trip point (LTP), cause the circuit to switch from one stable state to the another. Thus the
circuit may be used to discriminate between two D.C. voltage levels: in this capacity it is
known as a comparator
The non-linear circuits to perform the operation of clipping may also be used to perform
the operation of comparison. The basic difference between the two is that in comparator
there is no interest in reproducing any part of the signal waveform. For example, the
comparator output may consist of an abrupt departure from source quiescent level which
occurs at the time the signal attains the reference level but is otherwise independent of the
signal. Or the comparator output may be a sharp pulse which occurs when signal and
reference are equal.
If we assume that ramp signal is applied to the input, as shown in Figure 1(a) the output
Figure 1(b) is constant VR volts until the ramp signal reduces a value equal to VR volts
until the ramp signal reduces a value equal to VR volts then the diode conducts and the
input signal appears at the output.
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In a circuit a clipper was important that the portion of the wave form passed by the diode
was not distorted. The exact time t1 at which the diode began conducting was of
secondary importance. Now this circuit will be considered as a voltage comparator, (since
it compares the varying signal voltage with the reference voltage and hence the name
voltage comparator) and of primary concern is the time at which the input signal voltage
reaches the reference level VR. The shape of the output waveform is of secondary
importance. A diode used for this purpose called pick-off diode. Similarly with an
increasing ramp at its input the circuit of Figure 1(c) will be continue to operate as a
comparator. Its response will be same as shown in Figure 2(b). The diode of this circuit is
then referred to as a breakaway diode. The other two circuits shown in Figure 1 (a) and
(b) will act as comparators with a decreasing ramp. Their response is shown in Figure 2
(c) and (d).
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4.2 TRANSISTOR COMPARATOR
The basic differential amplifier circuit using bipolar transistor shown in Figure 3 acts as a
voltage comparator circuit, where Vo (t) is the input signal to be compared with a
reference voltage V. For good results, it is necessary that the transistors Q1 and Q2 as will
as resistors RC1 and RC2 are well matched. The circuit will offer an excellent CMRR
(defined as the ratio of common mode input voltage change and equivalent differential
input voltage), high voltage gain and optimum output stability with respct to device when
(i) RE is large (>re of Q1, Q2) and (ii) outputs is taken differentially. The former
requirement is usually met with by employing a constant current source (IE) in the
common emitter path of Q1 and Q2.
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Voltage comparators following the differential amplifier approach can be easily designed
to posses CMRR of 40-60 dB. This is helpful in increasing the range over which the two
input voltages are equal.
4.3 IC VOTAGE COMPARATOR
Comparator type circuits are used where it is desired to determine if an unknown analog
voltage equals or exceeds a known reference voltage. In addition, the comparison can be
used to convert sine wave and trigger pulses into square waves and thereby serves a pulse
The comparator makes use of an operational amplifier whose output can be fed back to
the non-inverting (positive) input in order to provide "snap action" in the output
switching. When an operational amplifier is provided whit a reference voltage at one
input and trigger or comparing voltage at its other input, the output of the amplifier will
rest at either cut-off or saturation. If the amplifier is supplied with ±15V(Vcc), the output
will be either plus or minus 15V, depending on the polarity of the trigger voltage
compared to the reference voltage.
Figure 4 shows an inverting voltage comparator. The non-inverting input is provided with
the reference voltage, and the inverting input is fed with a signal voltage to be compared
with the reference. Since the input is to the inverting terminal, the signal voltage will
result in an output pulse of opposite polarity. The input voltage must be greater than the
reference voltage before the comparator will change its state. There is no upper positive
limit so long as the inputresistor limits the current to 200 µA or less (depending on the
parameters of the operational amplifier used.)
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The output of the amplifier can be made to change states quickly (snap action) if positive
feedback is provided, as in Figure 5. The input to the amplifier at the inverting terminal
and hence the comparator is of the inverting type. In addition the feedback network here
provides the reference voltage. The reference voltage developed across R2 is determined
Vref = (R2 / (R1 + R2)) Vout
where Vout can be either positive or negative. The input signal polarity needed for
switching to occur depends on the resting state of the output.
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Communication has been one of the deepest needs of the human race throughout
recorded history. It is essential to forming social unions, to educating the young, and to
expressing a myriad of emotions and needs. Good communication is central to a civilized
The various communication disciplines in engineering have the purpose of providing
technological aids to human communication. One could view the smoke signals and drum
rolls of primitive societies as being technological aids to communication, but
communication technology as we view it today became important with telegraphy, then
telephony, then video, then computer communication, and today the amazing mixture of
all of these in inexpensive, small portable devices.
Initially these technologies were developed as separate networks and were viewed as
having little in common. As these networks grew, however, the fact that all parts of a
given network had to work together, coupled with the fact that diﬀerent components were
developed at diﬀerent times using diﬀerent design methodologies, caused an increased
focus on the underlying principles and architectural understanding required for continued
This need for basic principles was probably best understood at American Telephone and
Tele- graph (AT&T) where Bell Laboratories was created as the research and
development arm of AT&T. The Math center at Bell Labs became the predominant center
for communication re- search in the world, and held that position until quite recently. The
central core of the principles of communication technology were developed at that center.
Perhaps the greatest contribution from the math center was the creation of Information
Theory  by Claude Shannon in 1948. For perhaps the first 25 years of its existence,
Information Theory was regarded as a beautiful theory but not as a central guide to the
architecture and design of communication systems. After that time, however, both the
device technology and the engineering understanding of the theory were suﬃcient to
enable system development to follow information theoretic principles.
A number of information theoretic ideas and how they aﬀect communication system
design will be explained carefully in subsequent chapters. One pair of ideas, however, is
central to almost every topic. The first is to view all communication sources, e.g., speech
waveforms, image waveforms, and text files, as being representable by binary sequences.
The second is to design communication systems that first convert the source output into a
binary sequence and then convert that binary sequence into a form suitable for
transmission over particular physical media such as cable, twisted wire pair, optical fiber,
or electromagnetic radiation through space.
Digital communication systems, by definition, are communication systems that use such
sequence as an interface between the source and the channel input (and
similarly between the channel output and final destination)
The purpose of a Communication System is to transport an information bearing signal
from a source to a user destination via a communication channel.
1.2 MODEL OF A COMMUNICATION SYSTEM(ANALOG)
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Fig. 1.1: Block diagram of Communication System
The three basic elements of every communication systems are Transmitter, Receiver and
Channel. The Overall purpose of this system is to transfer information from one point
(called Source) to another point, the user destination, The message produced by a
source, normally, is not electrical. Hence an input transducer is used for converting the
message to a time – varying electrical quantity called message signal. Similarly, at the
destination point, another transducer converts the electrical waveform to the appropriate
The transmitter is located at one point in space, the receiver is located at some other point
separate from the transmitter, and the channel is the medium that provides the electrical
connection between them. The purpose of the transmitter is to transform the message
signal produced by the source of information into a form suitable for transmission over
The received signal is normally corrupted version of the transmitted signal, which is due
to channel imperfections, noise and interference from other sources.The receiver has the
task of operating on the received signal so as to reconstruct a recognizable form of the
original message signal and to deliver it to the user destination.
Communication Systems are divided into 3 categories:
Analog Communication Systems are designed to transmit analog information using
analog modulation methods.
Digital Communication Systems are designed for transmitting digital information using
digital modulation schemes, and
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Hybrid Systems that use digital modulation schemes for transmitting sampled and
quantized values of an analog message signal
1.3 ELEMENTS OF DIGITAL COMMUNICATION SYSTEMS:
The figure 1.2 shows the functional elements of a digital
Source of Information: 1. Analog Information Sources.
2. Digital Information Sources.
Analog Information Sources → Microphone actuated by a speech, TV Camera scanning a
scene, continuous amplitude signals
Digital Information Sources → These are teletype or the numerical output of computer
which consists of a sequence of discrete symbols or letters
An Analog information is transformed into a discrete information through the process of
sampling and quantizing.
Digital Communication System:
Fig :Block Diagram of a Digital Communication System
SOURCE ENCODER / DECODER:
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The Source encoder ( or Source coder) converts the input i.e. symbol sequence into a
binary sequence of 0‟ s and 1‟ s by assigning code words to the symbols in the input
sequence. For eg. :-If a source set is having hundred symbols, then the number of bits
used to represent each symbol will be 7 because 27
=128 unique combinations are
available. The important parameters of a source encoder are block size, code word
lengths, average data rate and the efficiency of the coder (i.e. actual output data rate
compared to the minimum achievable rate)
At the receiver, the source decoder converts the binary output of
the channel decoder into a symbol sequence. The decoder for a system using fixed –
length code words is quite simple, but the decoder for a system using variable – length
code words will be very complex. At the receiver, the source decoder converts the binary
output of the channel decoder into a symbol sequence. The decoder for a system using
fixed – length code words is quite simple, but the decoder for a system using variable –
length code words will be very complex. Ex: Huffman coding.
CHANNEL ENCODER / DECODER:
Error control is accomplished by the channel coding operation that consists of
systematically adding extra bits to the output of the source coder. These extra bits do not
convey any information but helps the receiver to detect and / or correct some of the errors
in the information bearing bits. There are two methods of channel coding:
Block Coding: The encoder takes a block of „k‟ information bits from the source
encoder and adds „r‟ error control bits, where „r‟ is dependent on „k‟ and error control
Convolution Coding: The information bearing message stream is encoded in a continuous
fashion by continuously interleaving information bits and error control bits. The Channel
decoder recovers the information bearing bits from the coded binary stream. Error
detection and possible correction is also performed by the channel decoder. The
important parameters of coder decoder are: Method of coding, efficiency, error control
capabilities and complexity of the circuit.
The Modulator converts the input bit stream into an electrical waveform
suitable for transmission over the communication channel. Modulator can be effectively
used to minimize the effects of channel noise, to match the frequency spectrum of
transmitted signal with channel characteristics, to provide the capability to multiplex
The extraction of the message from the information bearing
waveform produced by the modulation is accomplished by the demodulator. The output
of the demodulator is bit stream. The important parameter is the method of demodulation
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The Channel provides the electrical connection between the
source and destination. The different channels are: Pair of wires, Coaxial cable, Optical
fibre, Radio channel, Satellite channel or combination of any of these The
communication channels have only finite Bandwidth, non-ideal frequency response, the
signal often suffers amplitude and phase distortion as it travels over the channel. Also the
signal power decreases due to the attenuation of the channel. The signal is corrupted by
unwanted, unpredictable electrical signals referred to as noise.
The important parameters of the channel are Signal to Noise power Ratio (SNR), usable
bandwidth, amplitude and phase response and the statistical properties of noise
1.4 Advantages of Digital Communication:
The following are the advantages of the digital communication system:
The effect of distortion, noise and interference is less in a digital communication
system. This is because the disturbance must be large enough to change the pulse
from one state to the other.
Regenerative repeaters can be used at fixed distance along the link, to identify and
regenerate a pulse before it is degraded to an ambiguous state.
Digital circuits are more reliable and cheaper compared to analog circuits.
The Hardware implementation is more flexible than analog hardware because of
the use of microprocessors, VLSI chips etc.
Signal processing functions like encryption, compression can be employed to
maintain the secrecy of the information.
Error detecting and Error correcting codes improve the system performance by
reducing the probability of error.
Combining digital signals using TDM is simpler than combining analog signals
using FDM. The different types of signals such as data, telephone, TV can be
treated as identical signals in transmission and switching in a digital
We can avoid signal jamming using spread spectrum technique.
1.5 Disadvantages of Digital Communication:
The following are the disadvantages of the digital communication system:
Large System Bandwidth:- Digital transmission requires a large system
bandwidth to communicate the same information in a digital format as compared
to analog format.
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System Synchronization:- Digital detection requires system synchronization
whereas the analog signals generally have no such requirement.
1.6 Channels for Digital Communications:
The modulation and coding used in a digital communication system depend on the
characteristics of the channel. The two main characteristics of the channel are
BANDWIDTH and POWER. In addition the other characteristics are whether the channel
is linear or nonlinear, and how free the channel is free from the external interference.
Five channels are considered in the digital communication, namely: telephone channels,
coaxial cables, optical fibers, microwave radio, and satellite channels.
Telephone channel: It is designed to provide voice grade communication. Also good for
data communication over long distances. The channel has a band-pass characteristic
occupying the frequency range 300Hz to 3400hz, a high SNR of about 30db, and
approximately linear response.
For the transmission of voice signals the channel provides flat amplitude response. But
for the transmission of data and image transmissions, since the phase delay variations are
important an equalizer is used to maintain the flat amplitude response and a linear phase
response over the required frequency band. Transmission rates upto16.8 kilobits per
second have been achieved over the telephone lines.
Coaxial Cable: The coaxial cable consists of a single wire conductor centered inside an
outer conductor, which is insulated from each other by a dielectric. The main advantages
of the coaxial cable are wide bandwidth and low external interference. But closely spaced
repeaters are required. With repeaters spaced at 1km intervals the data rates of 274
megabits per second have been achieved.
Optical Fibers: An optical fiber consists of a very fine inner core made of silica glass,
surrounded by a concentric layer called cladding that is also made of glass. The refractive
index of the glass in the core is slightly higher than refractive index of the glass in the
cladding. Hence if a ray of light is launched into an optical fiber at the right oblique
acceptance angle, it is continually refracted into the core by the cladding. That means the
difference between the refractive indices of the core and cladding helps guide the
propagation of the ray of light inside the core of the fiber from one end to the other.
Compared to coaxial cables, optical fibers are smaller in size and they offer higher
transmission bandwidths and longer repeater separations.
Microwave radio: A microwave radio, operating on the line-of-sight link, consists
basically of a transmitter and a receiver that are equipped with antennas. The antennas are
placed on towers at sufficient height to have the transmitter and receiver in line-of-sight
of each other. The operating frequencies range from 1 to 30 GHz. Under normal
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atmospheric conditions, a microwave radio channel is very reliable and provides path for
high-speed digital transmission. But during meteorological variations, a severe
degradation occurs in the system performance.
Satellite Channel: A Satellite channel consists of a satellite in geostationary orbit, an
uplink from ground station, and a down link to another ground station. Both link operate
at microwave frequencies, with uplink the uplink frequency higher than the down link
frequency. In general, Satellite can be viewed as repeater in the sky. It permits
communication over long distances at higher bandwidths and relatively low cost.
Bandwidth is simply a measure of frequency range. The range of frequencies contained in
a composite signal is its bandwidth. The bandwidth is normally a difference between two
numbers. For example, if a composite signal contains frequencies between 1000 and
5000, its bandwidth is 5000 - 1000, or 4000. If a range of 2.40 GHz to 2.48 GHz is used
by a device, then the bandwidth would be 0.08 GHz (or more commonly stated as
80MHz).It is easy to see that the bandwidth we define here is closely related to the
amount of data you can transmit within it - the more room in frequency space, the more
data you can fit in at a given moment. The term bandwidth is often used for something
we should rather call a data rate, as in ―my Internet connection has 1 Mbps of
bandwidth‖, meaning it can transmit data at 1 megabit per second.
1.7 Geometric representation of Signals:
1.Analog signal: If the magnitudes of a real signal s(t) over its range of definition, T1≤ t
≤ T2, are real numbers (there are infinite such values) within a finite range, say, Smin ≤
S(t) ≤ Smax, the signal is analog. A digital signal s(t), on the contrary, can assume only
any of a finite number of values. Usually, a digital signal implies a discrete-time,
2.Energy signal: If, for a signal s(t),
i.e. the energy of the signal is finite,the signal is called an energy signal. However, the
same signal may have large power.The voltage generated by lightning (which is of short
duration) is a close example of physical equivalent of a signal with finite energy but very
3.Power signal: A power signal, on the contrary, will have a finite power but may have
finite or infinite energy. Mathematically,
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While electrical signals, derived from physical processes are mostly energy
signals,several mathematical functions, usually deterministic, represent power signals.
4.Deterministic and random signals: If a signal s(t), described at t = t1 is sufficient for
determining the signal at t = t2 at which the signal also exists, then s(t) represents a
5.Continuous time signal: Assuming the independent variable „t‟ to represent time, if
s(t) is defined for all possible values of t between its interval of definition (or existence),
T1≤ t ≤ T2. Then the signal s(t) is a continuous time signal.If a signal s(t) is defined only
for certain values of t over an interval T1≤ t ≤ T2, it is a discrete-time signal. A set of
sample values represent a discrete time signal
6.Periodic signal: If s(t) = s(t + T), for entire range of t over which the signal s(t) is
defined and T is a constant, s(t) is said to be periodic or repetitive. „T‟ indicates the
period of the signal and 1/T is its frequency of repetition
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A message signal may originate from a digital or analog source. If the message
signal is analog in nature, then it has to be converted into digital form before it can
transmitted by digital means. The process by which the continuous-time signal is
converted into a discrete–time signal is called Sampling Sampling operation is performed
in accordance with the sampling theorem.
Fig: 2.1 Natural Sampling – Waveforms
SAMPLING THEOREM FOR LOW-PASS SIGNALS
Statement:- ―If a band –limited signal g(t) contains no frequency components for ׀f׀ > W,
then it is completely described by instantaneous values g(kTs) uniformly spaced in time
with period Ts ≤ 1/2W. If the sampling rate, fs is equal to the Nyquist rate or greater (fs
≥2W), the signal g(t) can be exactly reconstructed.
The process of transforming Sampled amplitude values of a
message signal into a discrete amplitude value is referred to as Quantization.
The quantization Process has a two-fold effect:
1. the peak-to-peak range of the input sample values is subdivided into a finite set of
decision levels or decision thresholds that are aligned with the risers of the
the output is assigned a discrete value selected from a finite set of representation levels
that are aligned with the treads of the staircase
A quantizer is memory less in that the quantizer output is determined only by the value of
a corresponding input sample, independently of earlier analog samples applied to the
Types of Quantizers:
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1. Uniform Quantizer
2. Non- Uniform Quantizer
In Uniform type, the quantization levels are uniformly spaced, whereas in non-
uniform type the spacing between the levels will be unequal and mostly the relation is
0 Ts 2Ts 3Ts Time
Fig:2.2 Typical Quantization process.
Types of Uniform Quantizers: ( based on I/P - O/P Characteristics)
1. Mid-Rise type Quantizer
2. Mid-Tread type Quantizer
In the stair case like graph, the origin lies the middle of the tread portion in Mid –Tread
type where as the origin lies in the middle of the rise portion in the Mid-Rise type.
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Mid – tread type: Quantization levels – odd number.
Mid – Rise type: Quantization levels – even number.
Fig:2.4 Input-Output Characteristics of a Mid-Rise type Quantizer
Fig:2.5 Input-Output Characteristics of a Mid-Tread type Quantizer
Quantization Noise and Signal-to-Noise:
―The Quantization process introduces an error defined as the difference between the
input signal, x(t) and the output signal, yt). This error is called the Quantization Noise.‖
q(t) = x(t) – y(t)
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Quantization noise is produced in the transmitter end of a PCM system by
rounding off sample values of an analog base-band signal to the nearest permissible
representation levels of the quantizer. As such quantization noise differs from channel
noise in that it is signal dependent.
Let „Δ‟ be the step size of a quantizer and L be the total number of quantization levels.
Quantization levels are 0, ± ., ± 2 ., ±3 . . . . . . .
The Quantization error, Q is a random variable and will have its sample values bounded
by [-(Δ/2) < q < (Δ/2)]. If is small, the quantization error can be assumed to a uniformly
distributed random variable.
Consider a memory less quantizer that is both uniform and
symmetric. L = Number of quantization levels
X = Quantizer input
Y = Quantizer output
The output y is given by
which is a staircase function that befits the type of mid tread or mid riser quantizer of
Non – Uniform Quantizer:
In Non – Uniform Quantizer the step size varies. The use of a non – uniform quantizer is
equivalent to passing the baseband signal through a compressor and then applying the
compressed signal to a uniform quantizer. The resultant signal is then transmitted.
At the receiver, a device with a characteristic complementary to the compressor
called Expander is used to restore the signal samples to their correct relative level.
The Compressor and expander take together constitute a Compander.
Compander = Compressor + Expander
Advantages of Non – Uniform Quantization :
1. Higher average signal to quantization noise power ratio than the uniform quantizer
when the signal pdf is non uniform which is the case in many practical situation.
2.RMS value of the quantizer noise power of a non – uniform quantizer is substantially
proportional to the sampled value and hence the effect of the quantizer noise is reduced.
Encoding is the final step in what we call analog-to-digital (A/D) conversion.Sometimes,
encoding is considered as a separate stage that follows the A/D stage. The encoding stage
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3.1 Pulse Code Modulation:
Pulse code Modulation: The pulse code modulator technique
samples the input signal x(t) at a sampling frequency. This sampled
variable amplitude pulse is then digitalized by the analog to digital
converter. Figure.(1) shows the PCM generator.
x(t) x(nTS) q(nTs) pcm
Figure.(1): PCM modulator
In the PCM generator, the signal is first passed through sampler
which is sampled at a rate of (fs) where:
The output of the sampler x(nTs) which is discrete in time is fed to a q-
level quantizer. The quantizer compares the input x(nTs) with it's fixed
levels. It assigns any one of the digital level to x(nTs) that results in
minimum distortion or error. The error is called quantization error, thus
the output of the quantizer is a digital level called q(nTs). The
signal level q(nTs) is binary encode. The encoder converts the input
signal to v digits binary word.
the block diagram of the PCM receiver. The receiver starts by
reshaping the received pulses, removes the noise and then converts the
binary bits to analog. The received samples are then filtered by a low
pass filter; the cut off frequency is at fc.
fc= fm (2)
where fm: is the highest frequency component in the original signal.
PCM + Noise q(nTs) x(nTS) x(t)
Figure.(3): PCM demodulator
Sampling process Q level
Binary encoder D/A
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It is impossible to reconstruct the original signal x(t)
because of the permanent quantization error introduced
during quantization at the transmitter. The quantization error
can be reduced by the increasing quantization levels. This
corresponds to the increase of bits per sample(more
information). But increasing bits (v) increases the signaling
rate and requires a large transmission bandwidth. The choice of the
parameter for the number of quantization levels must be acceptable with
the quantization noise (quantization error). Figure.(4) shows the
1.1.1 Signaling Rate in PCM
Let the quantizer use 'v' number of binary digits to represent each
level. Then the number of levels that can be represented by v digits will
The number of bits per second is given by :
(Number of bits per second)=(Number of bits per samples)x(number
of samples per
= v (bits per sample) x fs (samples per second)
The number of bits per second is also called signaling rate of PCM and
is denoted by 'r':
Signaling rate= v fs (4)
1.1.2 Quantization Noise in PCM System
Errors are introduced in the signal because of the quantization
process. This error is called "quantization error". We define the
quantization error as:
ε= xq (nTs)- x(nTs)
Let an input signal x(nTs) have an amplitude in the range of xmax to -
xmax The total amplitude range is :
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Total amplitude = xmax-(- xmax)
If the amplitude range is divided into 'q' levels of quantizer, then the step
If the minimum and maximum values are equal to 1, xmax,=1, - xmax=-1,
then the equation (6)will be:
If ∆ is small it can be assumed that the quantization error is
uniformly distributed. The quantization noise is uniformly distributed in
the interval [-∆/2, ∆/2 ]. The figure.(5) shows the uniform distribution of
Fig.(5) The uniform distribution of quantization error
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The noise power is given by:
Noise power =Vnoise
/ R (8)
: is the mean square value of noise voltage, since noise is defined
by random variable "ε" and PDF fε(ε).
1.1.3 Signal to Quantization Noise ratio in PCM
The signal to quantization noise ratio is given as:
S Normalized signal power
Normalized noise powerNq
The number of quantization value is equal to:
1.1.4 Advantages of PCM
1. Effect of noise is reduced.
2. PCM permits the use of pulse regeneration.
Multiplexing of various PCM signals is
3.2 Differential Pulse Code Modulation (DPCM)
For the signals which does not change rapidly from one sample to next sample,
the PCM scheme is not preferred. When such highly correlated samples are
encoded the resulting encoded signal contains redundant information. By
removing this redundancy before encoding an efficient coded signal can be
obtained. One of such scheme is the DPCM technique. By knowing the past
behavior of a signal up to a certain point in time, it is possible to make some
inference about the future values.
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Fig:3.1DPCM Transmitter and Receiver
The transmitter and receiver of the DPCM scheme is shown above.
Transmitter: Let x(t) be the signal to be sampled and x(nTs) be it‟ s samples. In this
scheme the input to the quantizer is a signal
e(nTs) = x(nTs) - x^(nTs) ----- (3.31)
where x^(nTs) is the prediction for unquantized sample x(nTs). This predicted value is
produced by using a predictor whose input, consists of a quantized versions of the input
signal x(nTs). The signal e(nTs) is called the prediction error.
By encoding the quantizer output, in this method, we obtain a modified version of the
PCM called differential pulse code modulation (DPCM).
Quantizer output, v(nTs) = Q[e(nTs)]
= e(nTs) + q(nTs) ---- (3.32)
where q(nTs) is the quantization error.
Predictor input is the sum of quantizer output and predictor output,
u(nTs) = x^(nTs) + v(nTs)
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The receiver consists of a decoder to reconstruct the quantized error signal. The quantized
version of the original input is reconstructed from the decoder output using the same
predictor as used in the transmitter. In the absence of noise the encoded signal at the
receiver input is identical to the encoded signal at the transmitter output. Correspondingly
the receive output is equal to u(nTs), which differs from the input x(nts) only by the
quantizing error q(nTs).
Advantages of dpcm:
1. Eliminating the problem of accumulation of quantization noise:
2. Reducing the effect of transmission errors: as mentioned before,
transmission errors result in errors in all the reconstructed samples of the input signal that
come after the transmission error. The best method to combat this problem is to divide
data into sets of samples and resent the transmitter and receiver after the transmission of
each set of samples. This way, a transmission error that occurs will affect only the
of that part of the data. Once the system is reset, the effect of that error will stop.
Using 3.32 in 3.33, u(nTs) = x^(nTs) + e(nTs) + q(nTs) ----(3.34)
u(nTs) = x(nTs) + q(nTs) ----(3.35)
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3.3 Delta Modulation (DM)
Delta Modulation is a special case of DPCM. In DPCM scheme if the base band
signal is sampled at a rate much higher than the Nyquist rate purposely to
increase the correlation between adjacent samples of the signal, so as to permit
the use of a simple quantizing strategy for constructing the encoded signal, Delta
modulation (DM) is precisely such as scheme. Delta Modulation is the one-bit
(or two-level) versions of DPCM.
DM provides a staircase approximation to the over sampled version of an input base
band signal. The difference between the input and the approximation is quantized
into only two levels, namely, ±δ corresponding to positive and negative differences,
respectively, Thus, if the approximation falls below the signal at any sampling
epoch, it is increased by δ.
Provided that the signal does not change too rapidly from sample to sample, we
find that the stair case approximation remains within ±δ of the input signal. The
symbol δ denotes the absolute value of the two representation levels of the one-
bit quantizer used in the DM. Let the input signal be x(t) and the staircase
approximation to it is u(t).
In the receiver the stair case approximation u(t) is reconstructed by passing the
incoming sequence of positive and negative pulses through an accumulator in a
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manner similar to that used in the transmitter. The out-of –band quantization
noise in the high frequency staircase waveform u(t) is rejected by passing it
through a low-pass filter with a band-width equal to the original signal
Delta modulation offers two unique features:
1. No need for Word Framing because of one-bit code word.
2. Simple design for both Transmitter and Receiver
Disadvantage of DM:
Delta modulation systems are subject to two types of quantization error:
(1) slope –overload distortion, and (2) granular noise.
3.4 Adaptive Delta Modulation:
The performance of a delta modulator can be improved significantly by making
the step size of the modulator assume a time-varying form. In particular, during
a steep segment of the input signal the step size is increased. Conversely, when
the input signal is varying slowly, the step size is reduced. In this way, the size is
adapted to the level of the input signal. The resulting method is called adaptive
delta modulation (ADM).
There are several types of ADM, depending on the type of scheme used for
adjusting the step size. In this ADM, a discrete set of values is provided for the
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Block Diagram of ADM Transmitter.
Block Diagram of ADM Receiver
Adaptive Sub-band Coding:
PCM and ADPCM are both time-domain coders in that the speech signal is
processed in the time-domain as a single full band signal. Adaptive sub-band
coding is a frequency domain coder, in which the speech signal is divided into a
number of sub-bands and each one is encoded separately. The coder is capable
of digitizing speech at a rate of 16 kb/s with a quality comparable to that of 64
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kb/s PCM. To accomplish this performance, it exploits the quasi-periodic nature
of voiced speech and a characteristic of the hearing mechanism known as noise
Periodicity of voiced speech manifests itself in the fact that people speak
with a characteristic pitch frequency. This periodicity permits pitch prediction,
and therefore a further reduction in the level of the prediction error that requires
quantization, compared to differential pulse code modulation without pitch
prediction. The number of bits per sample that needs to be transmitted is thereby
greatly reduced, without a serious degradation in speech quality.
In adaptive sub band coding (ASBC), noise shaping is accomplished by
adaptive bit assignment. In particular, the number of bits used to encode each
sub-band is varied dynamically and shared with other sub-bands, such that the
encoding accuracy is always placed where it is needed in the frequency –
domain characterization of the signal. Indeed, sub-bands with little or no energy
may not be encoded at all.
1. Hierarchy of Digital Multiplexers
2. Light wave Transmission Link
There are two major advantages of adaptive delta modulation:
1. Slope overload distortion: occurs when modulating signal varies faster than
counter recovered signal.
2. Granular noise: occurs when variation in modulating signal is smaller than step
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4.1 Memory less modulation techniques:
Modulation is defined as the process by which some characteristics of a carrier
is varied in accordance with a modulating wave. In digital communications, the
modulating wave consists of binary data or an M-ary encoded version of it and the carrier
is sinusoidal wave.
Different Shift keying methods that are used in digital modulation techniques are
1.Amplitude shift keying [ASK]
2.Frequency shift keying [FSK]
3.Phase shift keying [PSK]
Fig shows different modulations
Fig:Hierarchy of digital modulation technique
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4.2 Amplitude-shift keying (ASK) :
Amplitude shift keying is a kind of digital modulation that represents digital data as
variations in the amplitude of a carrier wave.The amplitude of an analog carrier signal
varies in accordance with the bit stream (modulating signal) where frequency and phase
are keeping constant. The level of amplitude can be used to represent binary logic 0s and
1s. We can think of a carrier signal as an ON or OFF switch. In the modulated signal,
logic 0 is represented by the absence of a carrier, thus giving OFF/ON keying operation
and hence the name given.
Here is a diagram showing the ideal model for a transmission system using an ASK
It can be divided into three blocks. The first one represents the transmitter, the second
one is a linear model of the effects of the channel, the third one shows the structure of the
The following notation is used:
ht(t) is the carrier signal for the transmission
hc(t) is the impulse response of the channel
n(t) is the noise introduced by the channel
hr(t) is the filter at the receiver
L is the number of levels that are used for transmission
Ts is the time between the generation of two symbols.
Implementation of binary ASK:
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BINARY AMPLITUDE SHIFT KEYING, BANDWIDTH:
• d ≥ 0-related to the condition of the line
B = (1+d) x S = (1+d) x N x 1/r
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Advantages of Amplitude-shift keying (ASK):
The main advantage of ASK modulation is
generation of ASK is very much easy. Both ASK modulation and demodulation
processes are relatively inexpensive. The ASK technique is also commonly used to
transmit digital data over optical fiber. There are many other advantages of ASK, Such
as Amplitude-shift keying transmitters are very simple and transmitter current is lower than
FSK. One important advantage of ASK is it need lees bandwidth than FSK.
Disadvantages of Amplitude shift keying(ASK):
Unfortunately, ASK is linear and sensitive to
atmospheric noise, distortion, propagation condition on different routes in PSTN.It
requires excessive bandwidth and is therefore a waste of power.
4.3 Frequency shift keying:
A binary FSK Transmitter is as shown ,the incoming binary data sequence is applied to
on-off level encoder. The output of encoder is Eb volts for symbol 1 and 0 volts for
symbol „0‟ . When we have symbol 1 the upper channel is switched on with oscillator
frequency f1, for symbol „0‟ , because of inverter the lower channel is switched on with
oscillator frequency f2. These two frequencies are combined using an adder circuit and
then transmitted. The transmitted signal is nothing but required BFSK signal.
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The detector consists of two correlators. The incoming noisy BFSK signal x(t) is
common to both correlator. The Coherent reference signal ᶲ1(t) & ᶲ2(t) are supplied
to upper and lower correlators respectively.
The correlator outputs are then subtracted one from the other and resulting a
random vector „l‟ (l=x1 - x2). The output „l‟ is compared with threshold of zero volts.
If l > 0, the receiver decides in favour of symbol 1.
l < 0, the receiver decides in favour of symbol 0
• Limiting factor: Physical capabilities of the carrier
Not susceptible to noise as much as ASK
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– On voice-grade lines, used up to 1200bps
– Used for high-frequency (3 to 30 MHz) radio transmission
– used at higher frequencies on LANs that use coaxial cable.
4.4 PHASE SHIFT KEYING(PSK):
Fig(a) Block diagram of BPSK transmitter
Fig (b) Coherent binary PSK receiver
In a Coherent binary PSK system the pair of signals S1(t) and S2(t) are used to
represent binary symbol „1‟ and „0‟ respectively To generate a binary PSK signal we
have to represent the input binary sequence in polar form with symbol „1‟ and „0‟
represented by constant amplitude levels
To detect the original binary sequence of 1‟ s and 0‟ s we apply the noisy PSK signal x(t)
to a Correlator, which is also supplied with a locally generated coherent reference signal
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The correlator output x1 is compared with a threshold of zero volt.
If x1 > 0, the receiver decides in favour of symbol 1.
If x1 < 0, the receiver decides in favour of symbol
4.5 QUADRATURE PHASE – SHIFT KEYING(QPSK)
In a sense, QPSK is an expanded version from binary PSK where in a symbol consists of
two bits and two orthonormal basis functions are used. A group of two bits is often called
a „dibit‟ . So, four dibits are possible. Each symbol carries same energy.
Let, E: Energy per Symbol and T: SymbolDuration = 2.* Tb, where Tb: duration of 1 bit
Fig. (a) QPSK Transmitter
Fig. (b) QPSK Receiver
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Fig. QPSK Waveform
In QPSK system the information carried by the transmitted signal is contained in
The QPSK receiver consists of a pair of correlators with a common input and supplied
with a locally generated pair of coherent reference signals ᶲ1(t) & ᶲ2(t)as shown in
fig(b).The correlator outputs x1 and x2 produced in response to the received signal x(t)
are each compared with a threshold value of zero.
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The in-phase channel output :
If x1 > 0 a decision is made in favour of symbol 1 x1
< 0 a decision is made in favour of symbol 0
Similarly quadrature channel output:
If x2 >0 a decision is made in favour of symbol 1 and
x2 <0 a decision is made in favour of symbol 0