Published on

a neural network recognition module

Published in: Technology
  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide


  1. 1. Hardware Implementation of a Neural-Network Recognition module for Visual Servoing in a Mobile RobotGuided by: Presented by:Mrs . Anusree L S Vidya.G.SLecturer Roll no:18Dept .of ECE Semester:2TKM Institute of Technology M Tech (Electronics)with specialization In VLSI & Embedded Systems TKM Institute of Technology
  3. 3. INTRODUCTION Visual Servoing involves moving a robot or some part of a robot to a desired position using visual feedback The basic building block for Manipulation Foraging Target pursuit Landmark based navigation 3
  4. 4. AIM Implementation of an object recognition system in an FPGA based on ANN and some image processing modules The design is based on a SoPC. The neural network module is implemented as a specific hardware pre-processing modules together with the control of the whole system are implemented as software in the embedded processor core. 4
  7. 7. RECOGNITION SYSTEMA. IMAGE PRE-PROCESSING: A pre-processing algorithm handles the image provided by the camera , filters the desired colour and outlines the object of this colourB. NEURAL CLASSIFICATION Neural Network checks if any of the obtained shapes correspond to the target object 7
  8. 8. A.IMAGE PRE-PROCESSINGThis includes two steps  Colour filtering : ◦ The colour camera provides the RGB values. ◦ Image is then passed through a colour filter ◦ The original images are converted to binary images where the objects of the target colour are white and the background is black. 8
  9. 9. Edge Extraction Algorithm:◦ An edge extraction technique grounded on the chain-code algorithm has been chosen.◦ A lossless compression algorithm for binary images◦ Chain-codes are used to represent the contour of an object◦ The 4-connected set of directions called external chain code or crack code is used 9
  10. 10. Chain Code:00303000101033032322221222121101 10
  11. 11. Image Pre-Processing stages 11
  12. 12. B.NEURAL CLASSIFICATION A multilayer perceptron architecture, consisting of an input layer, a hidden layer and an output layer 12
  13. 13. Back-propogation algorithm usinggradient descendant method 13
  14. 14. HARDWARE/SOFTWAREIMPLEMENTATION Consists of i. Software partition ii. Hardware partition iii.Communication interface Software partition is built on a microblaze and includes control of complete system 14
  15. 15. Internal Architecture of theSoPC 15
  16. 16. ii. Interface Between Hardware and Software Partitions The interface between both partitions is based on the FSL (Fast Simplex Link) bus A unidirectional point-to-point communication channel available in the Micro Blaze, a FIFO-based communication FSL1 sends data from the software partition to the hardware partition (FSL2) performs data transfer in the opposite way. The depth of FSL1 is set to 16 elements & FSL2 contains just one element Both buses have a width of 8 bits 16
  17. 17. Structure of FSL Buses 17
  18. 18. iii. HARDWARE PARTITION• A two-layer processing module: the hidden layer and the output layer• Three ROM modules, which store the network parameters for the hidden layer, the output layer and the sigmoid function, respectively.• Additional components, such as a multiplexer and a block that calculates the maximum of its inputs.• A circuit controller that governs the whole operation of 18
  19. 19. •-The main component of processing module is theneuron- a MAC unit- A total of 36 MAC blocks-32 for hidden layer and 4 foroutput layer 19
  20. 20. 20
  21. 21.  ROM1(first layer) has a size of 512 weights with a wordlength of 12 bits which is organized in 16 blocks of 32 weights ROM2(second layer) c ontains 128 weights of a word length of 8 bits which is divided into 32 blocks of 4 weights each. ROM3 is the memory that stores the precomputed sigmoid function and contains 256 values with a word length of 8 bits. 21
  22. 22.  The system controller, whose main component is a six-bit counter, provides the control signals like reset , enable , address signals for ROM1 and ROM2 selection signal for the multiplexer. 22
  23. 23. System Performance and ResourceUsage The recognition process requires a total of 52 clock cycles , i.e. with a clock frequency of 100 MHz, it will only take 0.52s. The hardware exploits the parallelism and performs several operations simultaneously. With respect to the chip occupation, the system takes up only the 2% of the available slices of the device, the 1% of the LUT blocks and the 28% of the DSP block system. 23
  24. 24. CONCLUSION An FPGA module for embedding the object recognition module within a robotic mobile platform is being developed. FPGA module includes the implementation of the neural network. The control and the image processing modules are built on a Microblaze 24
  25. 25. FUTURE ENHANCEMENTS The image processing algorithms should also be implemented on the chip. They would be included preferably on the hardware partition of the SoPC this option. In addition, the whole system has to be integrated with the robotic platform 25
  26. 26. REFERENCES[1] Introduction to Artificial Neural Networks -S N SIVANANDAN & M PAULRAJ[2] Fundamentals of Neural Networks - LAURENE FAUSETT[3] Fundamentals of Digital Image Processing - S ANNADURAI & R SHANMUGALAKSHMI 26
  27. 27. Thank you 27