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74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
74hc373 data sheet
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74hc373 data sheet

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  • 1. INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT373 Octal D-type transparent latch; 3-stateProduct specification September 1993File under Integrated Circuits, IC06
  • 2. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373FEATURES input and an output enable (OE) input are common to all latches.• 3-state non-inverting outputs for bus oriented applications The “373” consists of eight D-type transparent latches with• Common 3-state output enable input 3-state true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are• Functionally identical to the “563”, “573” and “533” transparent, i.e. a latch output will change state each time• Output capability: bus driver its corresponding D-input changes.• ICC category: MSI When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding theGENERAL DESCRIPTION HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs.The 74HC/HCT373 are high-speed Si-gate CMOS devices When OE is HIGH, the outputs go to the high impedanceand are pin compatible with low power Schottky TTL OFF-state. Operation of the OE input does not affect the(LSTTL). They are specified in compliance with JEDEC state of the latches.standard no. 7A. The “373” is functionally identical to the “533”, “563” andThe 74HC/HCT373 are octal D-type transparent latches “573”, but the “563” and “533” have inverted outputs andfeaturing separate D-type inputs for each latch and 3-state the “563” and “573” have a different pin arrangement.outputs for bus oriented applications. A latch enable (LE)QUICK REFERENCE DATAGND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCTtPHL/ tPLH propagation delay CL = 15 pF; VCC = 5 V Dn to Qn 12 14 ns LE to Qn 15 13 nsCI input capacitance 3.5 3.5 pFCPD power dissipation capacitance per latch notes 1 and 2 45 41 pFNotes1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V2. For HC the condition is VI = GND to VCC. For HCT the condition is VI = GND to VCC − 1.5 VORDERING INFORMATIONSee “74HC/HCT/HCU/HCMOS Logic Package Information”.September 1993 2
  • 3. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373PIN DESCRIPTIONPIN NO. SYMBOL NAME AND FUNCTION1 OE 3-state output enable input (active LOW)2, 5, 6, 9, 12, 15, 16, 19 Q0 to Q7 3-state latch outputs3, 4, 7, 8, 13, 14, 17, 18 D0 to D7 data inputs10 GND ground (0 V)11 LE latch enable input (active HIGH)20 VCC positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.September 1993 3
  • 4. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373 FUNCTION TABLE OPERATING INPUTS INTERNAL OUTPUTS MODES OE LE Dn LATCHES Q0 to Q7 enable and L H L L L read register L H H H H (transparent mode) latch and L L l L L read register L L h H H latch register H X X X Z and disable H X X X Z outputs Notes Fig.4 Functional diagram. 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition X = don’t care Z = high impedance OFF-state Fig.5 Logic diagram (one latch). Fig.6 Logic diagram.September 1993 4
  • 5. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373DC CHARACTERISTICS FOR 74HCFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: bus driverICC category: MSIAC CHARACTERISTICS FOR 74HCGND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HC SYMBOL PARAMETER UNIT V WAVEFORMS +25 −40 to +85 −40 to +125 CC (V) min. typ. max. min. max. min. max.tPHL/ tPLH propagation delay 41 150 190 225 ns 2.0 Fig.7 Dn to Qn 15 30 38 45 4.5 12 26 33 38 6.0tPHL/ tPLH propagation delay 50 175 220 265 ns 2.0 Fig.8 LE to Qn 18 35 44 53 4.5 14 30 37 45 6.0tPZH/ tPZL 3-state output enable time 44 150 190 225 ns 2.0 Fig.9 OE to Qn 16 30 38 45 4.5 13 26 33 38 6.0tPHZ/ tPLZ 3-state output disable time 47 150 190 225 ns 2.0 Fig.9 OE to Qn 17 30 38 45 4.5 14 26 33 38 6.0tTHL/ tTLH output transition time 14 60 75 90 ns 2.0 Fig.7 5 12 15 18 4.5 4 10 13 15 6.0tW LE pulse width 80 17 100 120 ns 2.0 Fig.8 HIGH 16 6 20 24 4.5 14 5 17 20 6.0tsu set-up time 50 14 65 75 ns 2.0 Fig.10 Dn to LE 10 5 13 15 4.5 9 4 11 13 6.0th hold time 5 −8 5 5 ns 2.0 Fig.10 Dn to LE 5 −3 5 5 4.5 5 −2 5 5 6.0September 1993 5
  • 6. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373DC CHARACTERISTICS FOR 74HCTFor the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications”.Output capability: bus driverICC category: MSINote to HCT typesThe value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.INPUT UNIT LOAD COEFFICIENTDn 0.30LE 1.50OE 1.00AC CHARACTERISTICS FOR 74HCTGND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (°C) TEST CONDITIONS 74HCT SYMBOL PARAMETER UNIT V WAVEFORMS +25 −40 to +85 −40 to +125 CC (V) min. typ. max. min. max. min. max.tPHL/ tPLH propagation delay 17 30 38 45 ns 4.5 Fig.7 Dn to QntPHL/ tPLH propagation delay 16 32 40 48 ns 4.5 Fig.8 LE to QntPZH/ tPZL 3-state output enable time 19 32 40 48 ns 4.5 Fig.9 OE to QntPHZ/ tPLZ 3-state output disable time 18 30 38 45 ns 4.5 Fig.9 OE to QntTHL/ tTLH output transition time 5 12 15 18 ns 4.5 Fig.7tW LE pulse width 16 4 20 24 ns 4.5 Fig.8 HIGHtsu set-up time 12 6 15 18 ns 4.5 Fig.10 Dn to LEth hold time 4 −1 4 4 ns 4.5 Fig.10 Dn to LESeptember 1993 6
  • 7. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373AC WAVEFORMS (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the latch enable input Fig.7 Waveforms showing the input (Dn) to output (LE) pulse width, the latch enable input to (Qn) propagation delays and the output output (Qn) propagation delays and the transition times. output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.9 Waveforms showing the 3-state enable and disable times. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT : VM = 1.3 V; VI = GND to 3 V. Fig.10 Waveforms showing the data set-up and hold times for Dn input to LE input.September 1993 7
  • 8. Philips Semiconductors Product specification Octal D-type transparent latch; 3-state 74HC/HCT373PACKAGE OUTLINESSee “74HC/HCT/HCU/HCMOS Logic Package Outlines”.September 1993 8
  • 9. This datasheet has been download from: www.datasheetcatalog.comDatasheets for electronics components.

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