Presented By Adam Corbin and Michael Hughes
Outline Introduction Energy-Aware Processors OS Energy Management Power Reduction through Architectural  Design Reduc...
Introduction   Mobile devices have limited battery    power     Remote areas to charge batteries Battery life is only e...
Energy-Aware Processors Dynamic Voltage/Frequency Scaling  (DVFS) Scheduling Algorithms Computational Offloading     M...
Dynamic Voltage/FrequencyScaling   One of the more popular power    management schemes     Easy implementation     Perf...
Scheduling Algorithms   Classic computer science problem     Mobile devices add to the complexity when     battery energ...
Computational Offloading Resource-limited computing device defers  computation to a more capable device A solution for M...
OS Energy Management Dynamic Software Management (DSM)  Frameworks Constrained Power Management (CPM)
Dynamic SoftwareManagement Frameworks   Goals     Improve battery utilization     Avoid competition for limited energy ...
Constrained PowerManagement (CPM)   Goals     Manage both system resources and power of      an entire platform     Can...
Power Reduction throughArchitectural Design   Caches     Typically 30-60% of total processor area     20-50% of process...
Filter Caches & On-demandSelective Cache   Filter Caches     Reduce dynamic and static power      consumption     Shrin...
Speculative Activation   Attempt to make a prediction of where    the required data may be located     If prediction is ...
On-chip Memory   Minimize external data communication     Eliminates external frame buffers   No off-chip memory suppor...
Reducing Power though Circuitry Near-Threshold Computing Razor-Thin Margins Smaller Transistors All-Digital Phase Lock...
Near-Threshold Computing Lower voltage Pros: Energy consumption Cons: performance loss, memory and  logic failures Moo...
Razor-Thin Margins Run processors at the threshold voltage Reasons why chips run at higher voltages     Incorporate err...
Smaller Transistors   2-D vs. 3-D Transistor
Smaller Transistors Cont. 37% increase in  performance Moore’s law Lower voltage     50% less power   Less leakage
All-Digital Phase Locking   Phase-locked loops     Lock in and track input signal     Pace car analogy Used for synchr...
Smart Converters The analog to digital converts use a  switched capacitor Oregon State University     Loop of inverters...
Next Generation of Dynamic Ram   Samsung and Hynix on DDR4 ram     Drop voltage from 1.5V to 1.2V Includes better clock...
Smart Batteries   Background Info     Memory effect      ○ Solution: lithium ion   Advanced Power Management(APM)     ...
SmartReflix power and performance   Static Techniques     Power-gating   Dynamic Techniques     Dynamic power switchin...
SimpleScalar (Tools) Tool set Simulator to compare two different  machines Extended to the Power Analyzer     For the ...
PowerScope (Tools)   Step 1. Gathers information based on    processes
PowerScope Cont   Step 2. Of- Line Analysis
PowerScope Cont.   Output
Conclusions
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  • By adding parallel processing this could help in preformance
  • The one side vs 3 side Tri gate transistor
  • http://www.treehugger.com/gadgets/intel-announces-revolutionary-3d-transistors-50-more-energy-efficient-than-previous-generation.html - ideal for use in small handheld devices, which operate using less energy to "switch" back and forth between states. -200 mV lower voltage compared to the -the lower the voltage the higher the leakage but in this design there is less leakage at lower voltages compared to the 2d http://news.cnet.com/8301-13924_3-20059431-64.html http://www.anandtech.com/show/4333/intels-silvermont-a-new-atom-architecture
  • Pace car analagy- http://en.wikipedia.org/wiki/Phase-locked_loop The All-digital phase locking are easier to make Paper- http://web.mit.edu/~bdaya/www/All%20Digital%20Phase%20Locked%20Loop%20Design%20and%20Implementation.pdf
  • Power gating: “The basic strategy of power gating is to provide two power modes: a low power mode and an active mode. The goal is to switch between these modes at the appropriate time and in the appropriate manner to maximize power savings while minimizing the impact to performance.” http://nanocad.ee.ucla.edu/pub/Main/SnippetTutorial/PG.pdf Dynamic power switching- basically the same as power gating as it determines when a device has completed its current computational tasks and, if it's not needed at the moment, then puts the device into a low power state  Adaptive voltage scaling-by reducing the voltage you can gain up to 60% less energy consumption but you need to understand the performance at each voltage level. Once this information is gained then the voltage and be scaled based on what the device is doing http://www.ti.com/lit/ml/slyb186/slyb186.pdf Dynamic Vol/Freq Scaling- Similar to the past examples they will be scaled based on the activity of the device
  • http://www.ecs.umass.edu/ece/koren/architecture/Simplescalar/SimpleScalar_introduction.htm Has high-level function and low –level detailed simulator   users can build modeling applications that simulate real programs running on a range of modern processors and systems. Power Analyzer- University of Michigan and University of Colorado Wattch project- Princeton University- would connect to the system and estimate power that the system had consumed. Also has multi meter results from the CPU
  • http://notrump.eecs.umich.edu/papers/pscope99.pdf http://web.cs.wpi.edu/~emmanuel/courses/cs525m/S06/slides/powerscope_wk4.pdf The data collection phase uses a multi-meter [34] connected by a Hewlett-Packard interface bus (HPIB) connection to a data collection computer running an energy monitor component. A profiling computer running an application and a system monitor component are getting power by being connected to the multi-meter for measurement. The profiling computer also provides the trigger for the multi-meter to start measuring.
  • The offline analysis phase uses a third component called the energy analyzer, which will take the results produced in the data collection phase by the system monitor and the energy monitor and correlate the two to produce the energy profile of the application.
  • With this information the user can focus on the process that are consuming the most amount of power. In some cases there were 50% power reduction with minimal loss of performance
  • Mobile computing edited

    1. 1. Presented By Adam Corbin and Michael Hughes
    2. 2. Outline Introduction Energy-Aware Processors OS Energy Management Power Reduction through Architectural Design Reducing Power through Circuitry Smart Batteries Tools and Packages for Low-Power Design
    3. 3. Introduction Mobile devices have limited battery power  Remote areas to charge batteries Battery life is only expected to grow 10-20% over the next 10 years Software solutions Hardware solutions  Batteries  Circuitry
    4. 4. Energy-Aware Processors Dynamic Voltage/Frequency Scaling (DVFS) Scheduling Algorithms Computational Offloading  Mobile Wireless Ad-Hoc Networks (MANETs)
    5. 5. Dynamic Voltage/FrequencyScaling One of the more popular power management schemes  Easy implementation  Performance suffers  Most effective when hardware is more than adequate for the tasks being run  In resource-constrained mobile computing systems with slower processors there may not be much room DVFS techniques to save energy
    6. 6. Scheduling Algorithms Classic computer science problem  Mobile devices add to the complexity when battery energy utilization is considered Algorithms are tailored to the specific needs of the device  Energy saving vs. processing performance or a combination of the two
    7. 7. Computational Offloading Resource-limited computing device defers computation to a more capable device A solution for Mobile Wireless Ad-Hoc Networks (MANETs)  Distribute computational tasks amongst devices  Improvement in both energy saving and processing performance
    8. 8. OS Energy Management Dynamic Software Management (DSM) Frameworks Constrained Power Management (CPM)
    9. 9. Dynamic SoftwareManagement Frameworks Goals  Improve battery utilization  Avoid competition for limited energy resources from multiple applications Energy demand prediction  Critical component of framework  Uses energy models for prediction of application energy demand
    10. 10. Constrained PowerManagement (CPM) Goals  Manage both system resources and power of an entire platform  Can optimize energy or performance Quality of Service (QoS)  CPM collects QoS requirements from applications and coordinates device drivers to support requested QoS
    11. 11. Power Reduction throughArchitectural Design Caches  Typically 30-60% of total processor area  20-50% of processor power consumption Filter Caches & On-demand Selective Cache Speculative Activation On-chip Memory
    12. 12. Filter Caches & On-demandSelective Cache Filter Caches  Reduce dynamic and static power consumption  Shrink the size of L1 and L2 cache  Significant decrease in performance On-demand Selective Cache  Shuts down parts of the cache according to demand  Suffers from same decrease in peformance
    13. 13. Speculative Activation Attempt to make a prediction of where the required data may be located  If prediction is correct, latency and dynamic power consumption become similar to direct- mapped cache  If prediction is incorrect, cache is accessed twice and results in additional latency
    14. 14. On-chip Memory Minimize external data communication  Eliminates external frame buffers No off-chip memory support allows for high-quality processing at a minimal power level
    15. 15. Reducing Power though Circuitry Near-Threshold Computing Razor-Thin Margins Smaller Transistors All-Digital Phase Locking Smart Converters Next-Generation Dynamic Ram SmartReflix power and performance
    16. 16. Near-Threshold Computing Lower voltage Pros: Energy consumption Cons: performance loss, memory and logic failures Moore’s law  Energy efficiency problem 32nm chip example  Solution to improve performance
    17. 17. Razor-Thin Margins Run processors at the threshold voltage Reasons why chips run at higher voltages  Incorporate error detection Research from U. Of Michigan  Arm Cortex –M3 ○ 60% more energy efficient
    18. 18. Smaller Transistors 2-D vs. 3-D Transistor
    19. 19. Smaller Transistors Cont. 37% increase in performance Moore’s law Lower voltage  50% less power Less leakage
    20. 20. All-Digital Phase Locking Phase-locked loops  Lock in and track input signal  Pace car analogy Used for synchronize the processor and the clock Converting from analog to digital saves power
    21. 21. Smart Converters The analog to digital converts use a switched capacitor Oregon State University  Loop of inverters Chiao Tung University in Taiwan  Separate signal in 2 stages ○ 1 simple processing ○ 2 fine tuning
    22. 22. Next Generation of Dynamic Ram Samsung and Hynix on DDR4 ram  Drop voltage from 1.5V to 1.2V Includes better clocking Faster algorithms for encoding data End result  Consume less energy  Higher bandwidth
    23. 23. Smart Batteries Background Info  Memory effect ○ Solution: lithium ion Advanced Power Management(APM)  Mobile device uses information Polling for suspicious activity  Avoid stalling of devices and wasted energy
    24. 24. SmartReflix power and performance Static Techniques  Power-gating Dynamic Techniques  Dynamic power switching  Adaptive voltage scaling  Dynamic voltage/frequency scaling
    25. 25. SimpleScalar (Tools) Tool set Simulator to compare two different machines Extended to the Power Analyzer  For the ARM platform  Exam the performance/power trade-offs Extended to the Wattch Project  Web app
    26. 26. PowerScope (Tools) Step 1. Gathers information based on processes
    27. 27. PowerScope Cont Step 2. Of- Line Analysis
    28. 28. PowerScope Cont. Output
    29. 29. Conclusions

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