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Pad Cratering

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  • 1. SMTA Pad Cratering Webtorial Cheryl Tulkoff ctulkoff@dfrsolutions.com SMTA Pad Cratering Webtorial April 19, 2012 1
  • 2. Pad Cratering Course Abstract Pad cratering is defined as cracking which initiates within the laminate during a dynamic mechanical event such as In Circuit Testing (ICT), board depanelization, connector insertion, and other shock and vibration inducing activities. During this webtorial, you'll learn about the key drivers, measurement and detection protocols, and preventive tactics for this serious but prevalent failure. Pad cratering was first recognized in BGA packages but newer leadless, bottom termination components are also vulnerable. o o 2
  • 3. Biography o Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with an emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no clean and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs. o Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer. o She has a strong passion for pre-college STEM (Science, Technology, Engineering, and Math) outreach and volunteers with several organizations that specialize in encouraging pre-college students to pursue careers in these fields. 3
  • 4. Cheryl’s Background o 22 years in Electronics o o o IBM, Cypress Semiconductor, National Instruments SRAM and PLD Fab (silicon level) Printed Circuit Board Fabrication, Assembly, Test, Failure Analysis, Reliability Testing and Management ISO audit trained, ASQ CRE, Senior ASQ & IEEE Member, SMTA, iMAPS o Random facts: o o o o o o 4 Rambling Wreck from Georgia Tech 14 year old son David, Husband Mike, Chocolate Lab Buddy Marathoner & Ultra Runner Ran Boston 2009 in 3:15 Ran 100 miles in 24:52 on 2/4-2/5, 2012 Triathlete – Sprint, Olympic, and Half. Ironman finisher in CDA, Idaho in June ‘10
  • 5. Webtorial Outline MODULE 1: INTRODUCTION o o o o o Pad Cratering Defined Pad Cratering History Pad Cratering Drivers Is Pad Cratering a Pb-Free Issue? At Risk components MODULE 5: Mitigation Techniques o o o o MODULE 2: Testing Methodologies o o Overview of IPC Industry Test Standards Alternative Test Methods o o o MODULE 3: Detection Methods o o o ICT & Functional Test Electrical Characterization Alternative Test Methods o o o o o Failure Analysis Overview Electrical Characterization Cross-Sectioning Dye-N-Pry X-ray 5 o Acoustic Microscopy MODULE 4: Failure Analysis Techniques o o Corner Glue Component Practices Pad Design & Layout ICT Fixture Evaluation Assembly Process Evaluation Process Specifications More compliant solder New acceptance criteria for laminate materials Require reporting of fracture toughness and elastic modulus MODULE 6: Prevention Methods & Future Work o Zeta Cap
  • 6. Module 1: Introduction Pad Cratering Defined 6
  • 7. Strain & Flexure: Pad Cratering o Cracking initiating within the laminate during a dynamic mechanical event o In circuit testing (ICT), board depanelization, connector insertion, shock and vibration, etc. G. Shade, Intel (2006) 7 7 7
  • 8. Laminate Cracking Leads to Trace Fracture Trace routed externally Functional failure will occur Bending Force 8
  • 9. Pad Cratering Intel (2006) o Drivers o o o o o o o o o Difficult to detect using standard procedures o 9 Finer pitch components More brittle laminates Stiffer solders (SAC vs. SnPb) Presence of a large heat sink Location PCB thickness Component size & rigidity Temperatures & cooling rates X-ray, dye-n-pry, ball shear, and ball pull 9 9
  • 10. Is Pad Cratering a Pb-Free Issue? No, but… 35x35mm, 388 I/O BGA; 0.76 mm/min Average Fracture Paste Solder Ball Std Dev (N) Load (N) SnPb SnPb 692 93 Sn4.0Ag0.5Cu SnPb 656 102 Sn4.0Ag0.5Cu 935 190 Roubaud, HP APEX 2001 10 10
  • 11. Pad cratering has been around for a while…… 11
  • 12. Module 2:Testing Methodologies Industry Standards Alternative Testing Methodologies 12
  • 13. IPC-9708 Pad Cratering Test Methods Standard o Documents 3 test methods o o o o o Each test has pros /cons No pass or fail criteria o 13 Pin Pull Ball pull Ball shear User must define what is acceptable based on design and reliability requirements
  • 14. BGA Mechanical Loading Failure Modes o Many ways in which a BGA failure can manifest itself o 14 Weakest link in the system fails first
  • 15. IPC 9708 – SMD versus NSMD Structures Defined o Choice of pad geometry affects failure rate & location o 15 Each has advantages & disadvantage
  • 16. IPC 9708 Pin Pull Test o o o 17 Good for any pad geometry – no balls required Most sensitive to board material and design variables Requires pins to be soldered to pads
  • 17. IPC 9708 Ball Pull Test o o o Quick test after BGA ball attach No expensive pins required Almost as sensitive as pin pull o o 18 BGAs only Highly dependent on solder ball so process control is critical
  • 18. IPC 9708 Ball Shear Test o o Quick test after BGA ball attach Less control needed than ball pull test o o 19 BGAs only Least sensitive to design and material variables
  • 19. Testing Practice Recommendations o Coupon-based testing o o o o 20 Allows direct comparison between design, materials and process changes Pin pull & ball pull characterize tensile loading Ball shear characterizes shear loading Best practice is to use at least 2 of the 3 tests so that both tensile & shear are covered
  • 20. IPC 9708 Failure Modes Defined 21
  • 21. Cisco’s Summary of Impact of Variables on Test Results 22
  • 22. Universal Instruments Area Consortium Test Method Comparison Results 23
  • 23. Universal Instruments Test Method Comparison Results 24
  • 24. IPC-9704 – Strain Gage Testing o Details how to perform strain gage tests o o o o 25 Test & equipment required Measurement & reporting for both strain & strain rate SMT devices excluding discretes covered Measure all BGA devices with a package body size =/> than 27 mm x 27 mm o Measure 3 largest otherwise Strain induced failures include ball cracking, trace damage, pad lifting and substrate damage.
  • 25. Rosette Strain Gages o o Measures strain on several axes at the same time Pre-Wired with either o o o o For Determining the Magnitude and Angle of Unknown Stress Strain Gages for Static and Dynamic Applications o o o o 26 Two 3-ft. (1 m) Leads or Three 9-ft. (3 m) Leads Broad Temperature Range Encapsulated for Added Durability Clear Alignment Marks http://www.omega.com/ppt/pptsc.asp?ref=Rosettes _Prewired_Strain_KFG&nav=
  • 26. Strain Gage Placement o o o 27 Grid strains e1 and e3 in should be oriented parallel to the edges of the package. Grid strain e2 ishould be oriented diagonally away from package with respect to the edges of the package. Consistent and precise placement of gages is critical to correlation of data between test location and samples.
  • 27. IPC 9704 o o No pass / fails limits 3 strain limit approaches o o o 28 Component supplier provided Customer specified Rate limited o Maximum allowable strain versus rate and PCB thickness o Not strict guidance
  • 28. IPC 9702 4 Point Bent Test o o Used to characterize fracture strength of board level interconnects Failure modes from this test are not easily differentiated o o o 29 High speed test Short duration Failures in quick succession
  • 29. Module 3: Detection Methods 30
  • 30. Detection Methods o Limited visual inspection options o o Electrical Characterization o o o o o Critical for both detection & failure analysis A known good or reference component is often required for comparison Functional and in circuit testing (ICT) Acoustic Microscopy Highly Accelerated Life Testing (HALT) o 31 Will cover more in failure analysis techniques Design & production phases
  • 31. Electrical Characterization: PCB Assembly Level o o o Narrowing scope is critical to identifying the issue A known good or reference component is often required. Functional testing o o JTAG (joint task action group) boundary scan o o o o o o o Attempt to perform as much electrical characterization without component removal Consider trace isolation Environmental stresses o 32 Measures voltage fluctuations as a function of time (passive) Useful in probing operational circuitry Digital capture provides better documentation capability Available stand alone or PC-based Isolation of attached components o o Allows for testing ICs and their interconnections using four I/O pins (clock, input data, output data, and state machine mode control) Allows for relatively accurate identification of failure site, but rarely performed on failed units (primarily replacement for In Circuit Test-ICT) Oscilloscope o o Most valuable, if product is experiencing ‘partial’, permanent failure Approach similar to bare board 32
  • 32. Dremel Tool – Induce Vibrations o o o 33 A Dremel tool can be used to induce local vibration during debugging Can “force” intermittent failures out of hiding at benchtop debug http://www.dremel.com
  • 33. In Circuit Test o In Circuit Testing (ICT) is performed using vacuum and probe force o Can “compress” the components & laminates into making contact o High rate of escapes from this process o Depends on test coverage and access o Best at capturing complete fracture – small cracks not found Image Courtesy of Rematek 34 34
  • 34. Pad Cratering & Electrical Test Detection o CalPoly Study showing failure of electrical testing to capture Board Level Failure Analysis of Chip Scale Package Drop Test all defects Assemblies, 2008 International Microelectronics And Packaging Society. 35
  • 35. Electrical Failure Pareto from CalPoly Study o Majority of failure occur at corner of packages – locations of most stress & strain Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies, 2008 International Microelectronics And Packaging Society. 36
  • 36. Alternative Test Methodology proposed by Cisco o Cisco has developed a detection method based on Acoustic Microscopy referred to as Acoustic Emissions (AE) o o o o Appears to detect onset earlier and with greater capture rate than electrical methods Modified 4 point bend test Full assembly based test Intent is to capture partial/small cracks which could propagate to failure o Some studies show 20% crack growth during thermal cycling “A New Approach for Early Detection of PCB Pad Cratering Failures,” AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS”, 37 “COMPREHENSIVE METHODOLOGY TO CHARACTERIZE
  • 37. Acoustic Microscopy Overview    Method for inspecting internal structures through the application of high frequency (>20 kHz) sound waves Requires immersion in water (acoustic signals reflected by air)  Allows for very accurate detection of voids and delaminations Options  Frequency Transducer  Transmission mode H2O or other  Imaging fluids Receive 38 38
  • 38. Acoustic Microscopy: Transducer Frequency High frequency Short focus Low frequency Long focus 1. Higher resolution 1. Lower resolution 2. Shorter focal lengths 2. Longer focal lengths 3. Less penetration 3. Greater penetration (Thinner packages) (Thicker packages) General rules: • Ultra High Frequency (200+ MHz) for flip chips and wafers. • High Frequency (50-75 MHz) for thin plastic packages. (110MHz-UHF) for flip chips. • Low Frequency (15-30 MHz) for thicker plastic packages. 39 39
  • 39. Acoustic Microscopy: Transmission Mode Pulse-Echo Through Transmission Transmit Transmit & Receive Receive Pulse-Echo: One Transducer • Uses ultrasound reflected from the sample • Can determine which interface is delaminated • Requires scanning from both sides to inspect all interfaces • Provides images with high degree of spatial detail • Peak amplitude, time of flight (TOF), and phase inversion measurement 40 Through Transmission: Two Transducers • Uses ultrasound transmitted through the sample • One scan reveals delamination at all interfaces • No way to determine which interface is delaminated • Less spatial resolution than pulse-echo • Commonly used to verify pulse-echo results 40
  • 40. Acoustic Microscopy o Used when delamination or voiding is suspected o o o o Some value for ceramic BGAs o 41 Electrical shorting within the package (delamination, electro-chemical migration) Electrical opens (delamination, wire bond failure) Insufficient thermal performance detected (i.e. die attach) Attenuation due to multiple interfaces prevents imaging of interconnects under PBGAs 41
  • 41. Example Acoustic Microscopy Equipment Acoustic Microscopy Equipment – PCBA is immersed in fluid bath, usually DI water, can be non destructive if no sensitive components are present. 42
  • 42. Cisco Acoustic Emissions (AE) Test Setup o 43 10 MHz Data Acq Rate
  • 43. Cisco Acoustic Emissions (AE) Test Setup o o 44 HSBGA Test Vehicle Low speed and high speed testing performed to look at influence of strain rates along with total strain
  • 44. Cisco Bend Test Parameters 45
  • 45. Cisco Bend Test Parameters 46
  • 46. Cisco Acoustic Emissions & Electrical Failures 47
  • 47. Cisco Acoustic Emission Study Conclusions o o Pad cratering identified at much lower strain levels than those detected electrically in other studies This test method does not require custom daisy chained test vehicles o o Other failure mechanisms could potentially be detectable o o 48 Potentially cheaper method for evaluating joints and laminates Ceramic cracks Thermal cycling, shock, or vibration failures
  • 48. Highly Accelerated Life Testing (HALT) o A series of environmental stress tests designed to understand the limitations of the design (discover your margins) o o o What HALT is not o o 49 Theory 1: The greater the margin between the limits of the design and the operating environment, the lower the probability of failure if defects are introduced during manufacturing Theory 2: Not all field failures are due to wearout (motivation for accelerated life testing). Many failures due to introduction of “energy” into the system from multiple environmental stresses (thermal, vibration, power, humidity, etc.) It can not be used to determine long-term reliability It is not an optimum process to identify defective material (defective design, yes)
  • 49. HALT (cont.) o Phase One: Step Stress Testing o o Phase Two: Cyclic and Combinatorial Stress Testing o o o o Thermal cycling (increasing ramp rates) Thermal cycling + vibration Etc. Requires understanding and analysis o o 50 Increases the environmental stress (temperature, vibration, electrical, etc.) until recoverable and non-recoverable failures occur You can not “pass” HALT Actions based upon failure mechanism and cost of fix
  • 50. How To Use HALT Lower Destruct Limit Lower Oper. Limit Upper Oper. Limit Upper Destruct Limit Storage Specs Operational Specs Stress o Critical for understanding product limitations o o Benefits o o 51 If you spec to 50C and the product fails at 52C, how confident are you in the robustness considering nominal variations in component performance? Identifies potential weak points in design before field release Pass/Fail: Three sigma or statistical-demonstration of sufficient margin; electronics must operate from 0C to 50C. 51
  • 51. Step Stress Testing Recommendations o Perform Voltage Step Stress Test o o o Perform Temperature Step Stress Test o o o o o o High and low temperatures with 10 or 15C step Dwell only long enough to test functionality Pull max. and min. specified voltage at max. and min. specified temperatures (“paint the corners”) Perform for both hot and cold temperatures Test to recoverable and permanent failure Perform Vibration Step Stress Test o o 52 Both high and low voltage Test to recoverable and permanent failure Starting at 5g and increasing in 5g increments Finish at 30 or 40g’s
  • 52. RoHS HALT Failure Analysis Examples o Cracked Solder Joint: BGA ball to BGA substrate 53 o PCB Laminate Cracks – BGA, also called “pad cratering”
  • 53. RoHS HALT Failure Analysis o Cracked traces to BGA pads – outer rows 54 o BGA pads separated from PCB
  • 54. RoHS HALT Failure Analysis Cracks in BGA Laminate o 55 o Laminate Cracks - Repair
  • 55. Pb-Free Reliability Failure Example Trace fracture in HALT Testing Fracture occurred here. This only occurred on traces leading outward of outermost balls (on daisy chain board). Design modification made to resolve issue. 56
  • 56. SMTA Pad Cratering Webtorial Cheryl Tulkoff ctulkoff@dfrsolutions.com SMTA Pad Cratering Webtorial April 19, 2012 57
  • 57. Contact Information o Questions? o o o o 58 Contact Cheryl Tulkoff, ctulkoff@dfrsolutions.com, 512-913-8624 askdfr@dfrsolutions.com www.dfrsolutions.com Connect with me in LinkedIn as well!
  • 58. Webtorial Outline MODULE 1: INTRODUCTION o o o o o Pad Cratering Defined Pad Cratering History Pad Cratering Drivers Is Pad Cratering a Pb-Free Issue? At Risk components MODULE 5: Mitigation Techniques o o o o MODULE 2: Testing Methodologies o o Overview of IPC Industry Test Standards Alternative Test Methods o o o MODULE 3: Detection Methods o o o ICT & Functional Test Electrical Characterization Alternative Test Methods o o o o o Failure Analysis Overview Electrical Characterization Cross-Sectioning Dye-N-Pry X-ray 59 o Acoustic Microscopy MODULE 4: Failure Analysis Techniques o o Corner Glue Component Practices Pad Design & Layout ICT Fixture Evaluation Assembly Process Evaluation Process Specifications More compliant solder New acceptance criteria for laminate materials Require reporting of fracture toughness and elastic modulus MODULE 6: Prevention Methods & Future Work o Zeta Cap o Sherlock
  • 59. Module 4: Failure Analysis (FA) Techniques 60
  • 60. Pad Cratering Failure Analysis o Pad Cratering is difficult to detect using standard procedures o o o Unfortunately many companies are unaware of pad cratering until failure happens Recalls have been common and painful! Potential warning signs: o o o Beware of excessive BGA repair rate High percentage of “defective” BGAs High rate of “retest to pass” at in circuit test (ICT) o Monitor retest rate o In Circuit Testing (ICT) is performed using vacuum and pressure o o o 61 Can “compress” the components & laminates into making contact X-ray and Dye-n-pry provide a limited look o New work at Dage with 3D m-CT Inspection Option3D m-CT Inspection Option Precision cross-sections are required to confirm
  • 61. General Words of Wisdom on FA o Before spending time and money on Failure Analysis, consider the following: o o o o o o 62 Consider FA “order” carefully. Some actions you take will limit or eliminate the ability to perform follow on tests. Understand the limitations and output of the tests you select. Use partner labs who can help you select and interpret tests for capabilities you don’t have. Be careful of requesting a specific test. Describe the problem and define the data and output you need first. Pursue multiple courses of action. There is rarely one test or one root cause that will solve your problem. Don’t put other activities on hold while waiting for FA results. Understand how long it will take to get results Consider how you will use the data. How will it help you? o Information? o Change course, process, supplier? o Don’t pursue FA data if it won’t help you or you have no control over the path it might take you down. Some FA is just not worth doing
  • 62. Failure Analysis Techniques     63 Failure analysis always starts with Non-Destructive Evaluation (NDE)  Designed to obtain maximum information with minimal risk of damaging or destroying physical evidence Emphasize the use of simple tools first (Generally) non-destructive techniques:  Visual Inspection  Electrical Characterization  Time Domain Reflectometry  Acoustic Microscopy  X-ray Microscopy  Thermal Imaging (Infra-red camera)  SQUID Microscopy A known good or reference component is often required. 63
  • 63. Failure Analysis Techniques o Destructive evaluation techniques o o o o o o o o o o Other characterization methods o o o o 64 Decapsulation Plasma etching Cross-sectioning Thermal imaging (liquid crystal; SQUID and IR also good after decap) SEM/EDX – Scanning Electron Microscope / Energy dispersive X-ray Spectroscopy Surface/depth profiling techniques: SIMS-Secondary Ion Mass Spectroscopy, Auger OBIC/EBIC FIB - Focused Ion Beam Mechanical testing: wire pull, wire shear, solder ball shear, die shear FTIR- Fourier Transform Infra-Red Spectroscopy Ion chromatography DSC – Differential Scanning Calorimetry DMA/TMA – Thermo-mechanical analysis 64
  • 64. Pad Cratering Failure Analysis o 65 Pad Cratering is difficult to detect using standard procedures o In Circuit Testing (ICT) is performed using vacuum and pressure o Can “compress” the components & laminates into making contact o Beware of high component failure rate o Monitor retest rate o X-ray and Dye-n-pry provide a limited look o Precision cross-sections are required
  • 65. BGA Visual Inspection  BGA (Ball Grid Array) Perimeter Inspection    66 Use of optical fiber to inspect solder balls on the perimeter of the package Most common failure site under BGAs Magnification: 200x 66
  • 66. Electrical Characterization  Most critical step in the failure analysis process  Can the reported failure mode be replicated?        Component Bare board PCB assembly Sometimes performed in combination with environmental exposure     67 Least utilized to its fullest extent Equipment often shared with production and R&D Approach dependent upon the product   Persistent or intermittent? Intermittent failures often incorrectly diagnosed as no trouble found (NTF) Characterization over specified temperature range Characterization over expected temperature range Humidity environment (re-introduction of moisture) Not designed to induce damage! 67
  • 67. Electrical Characterization: Component Level  Parametric characterization   Curve tracer     Release and return of electrical signal along a given path Measurement of phase shift of return signal indicates potential location of electrical open Other characterization equipment     Applies alternating voltage; provides plot of voltage vs. current response Valuable in characterizing diode, transistor, and resistance behavior Time domain reflectometry (TDR)   Comparison of performance to datasheet specifications Inductance/capacitance/resistance (LCR) meter High resistance meter (leakage current < nA) Low resistance meter (four wire; < milliohms) Use of additional environmental stresses  Semiconductor-based devices   68 Temperature rise or temperature/humidity could trigger elevated leakage current Passive components 68
  • 68. Electrical Characterization: PCB Assembly Level  Functional   JTAG (joint task action group) boundary scan        Attempt to perform as much electrical characterization without component removal Consider trace isolation (knife, low speed saw) Environmental stresses  69 Measures voltage fluctuations as a function of time (passive) Useful in probing operational circuitry Digital capture provides better documentation capability Available stand alone or PC-based Isolation of attached components   Allows for testing ICs and their interconnections using four I/O pins (clock, input data, output data, and state machine mode control) Allows for relatively accurate identification of failure site, but rarely performed on failed units (primarily replacement for In Circuit Test-ICT) Oscilloscope   Most valuable, if product is experiencing ‘partial’, permanent failure Approach similar to bare board 69
  • 69. Dye N Pry o o 70 Allows for quick (destructive) inspection for cracked or fractured solder joints under leadless components (BGAs, BTCs) http://www.electroiq.com/inde x/display/packaging-articledisplay/165957/articles/adva nced-packaging/volume12/issue-1/features/solderjoint-failure-analysis.html
  • 70. Dye N Pry o o o o 71 Step 1: Apply dye along the package edge so that it can flow into defective solder joints. Step 2: Cure the dye Step 3: Remove the component Where dye is, solder/contact was not…
  • 71. Cross-Sectioning o o Standard method for destructive subsurface evaluation Method: o o o o o o 72 Sawing to approximate area of interest Potting in epoxy resins to aid polishing Polishing medium dependent upon materials: typically diamond, SiC, or alumina suspensions & embedded polishing cloths Coarse to fine (600 grit to 0.05 um) grinding sequence to eliminate damage from previous step Final etch often used for microstructural relief Optical/electron microscopy techniques used for inspection thereafter 72
  • 72. Typical Cross Sectioning Equipment Polishing & Grinding Disks Precision Saw Inverted Microscope Polishing and Grinding Equipment Specimen Mounting 73 Polishing Compounds, Epoxies
  • 73. Nordson Dage X-Ray with 3D m-CT Inspection Option Dage m-CT inspection option provides Computerised Tomography (CT) functionality to compliment the 2D X-ray Produces the CT models for 3D sample analysis, virtual microsectioning and internal dimensional measurements for o o o o crack, void and reverse engineering Potentially reduce the number of time-consuming micro-section analyses that are needed Or assist in identifying on where micro-section preparation and investigation Non-destructive o o o o 74
  • 74. Module 5: Mitigation Techniques 75
  • 75. Potential Mitigations to Pad Cratering o Board Redesign o o o o Solder mask defined vs. non-solder mask defined Pad Geometry Layout & PCB thickness Limitations on board flexure o o 750 to 500 microstrain, component and layout dependent Process Control & Validation o Corner Glue o More compliant solder o SAC305 is relatively rigid, SAC105 and SNC are possible alternatives o New laminate structures and component techniques o New acceptance criteria for laminate materials o o Alternative approach o 76 Attempting to characterize laminate material using high-speed ball pull and shear testing Require reporting of fracture toughness and elastic modulus 76 76
  • 76. Component Supplier Practices Intel Example 77
  • 77. Pad Geometry o Pad design influences failure o o Solder mask defined pads can provide additional strength o o 78 Smaller pads result in higher stress under a given load Increases tolerable strain Moves failure location from pad crater to intermetallic fracture
  • 78. BGA CORNER BALL LAYOUT ENHANCEMENT BGA BALL LAYOUT IN SHAPE AREA The trace width is enlarged to the width of the BGA pad for a length of 1-2 diameters of the BGA pad. Connections to conductive shape areas should have relief to avoid solder mask defined pads, allowing better adhesion from ball to pad The BGA pads enhanced by wide traces are in the 3 x 3 corner array. Electrical consideration may take priority over trace widening where necessary. Blue – BGA Pad Green – Trace Routing Pink – Solder Mask Clearance (2 mils) Yellow - Via 79
  • 79. Cisco Recommended Pad Modifications 80
  • 80. Universal Consortium Pad Geometry Results in Drop Tests o Optimized results with “bullet” geometry found o o o 81 Largest solderable area Best lifetime in drop Failure shifted to intermetallic region
  • 81. Process Control is Key! o Some key areas of risk o o o o o o o 82 In Circuit Test Mechanical Assembly Depanelization Connector Insertion Heat sink attach Module assembly Look for ways to assess and minimize flexure and strain throughout the process
  • 82. Corner Glue o o o o 83 Excessive shock, vibration, or bending will cause PCB pad cratering. When design rules are not sufficient, corner glue is the second line of defense to combat this failure mechanism. Pre-Reflow Post-Reflow
  • 83. Pre-Reflow Adhesive Process * * * - For LF reflow use CNB951 adhesive 84
  • 84. Corner Glue – Post Reflow Process To be most effective, length of bead should be 4-6 solder balls in length. BGA Too Little Too Much Correct Target approximately 50% of BGA substrate height 85
  • 85. Corner Glue – Mechanical Improvement Ref: M. Kochenowski et. al., Improved Shock and Bend with Corner Glue, SMTA, Chicago, 2006. Post-Reflow Glue 86 Failure mech
  • 86. ICT Strain: Fixture & Process Analysis o o o o 87 87 Review/perform ICT strain evaluation at fixture supplier and in process: 500 us, critical for QFN, CSP, and BGA http://www.rematek.com/download_center/board_stress_analysis.pdf To reduce the pressures exerted on a PCB, the first and simplest solution is to reduce the probes forces, when this is possible. Secondly, the positioning of the fingers/stoppers must be optimized to control the probe forces. But this is often very difficult to achieve. Mechanically, the stoppers must be located exactly under the pressure fingers to avoid the creation of shear points
  • 87. ICT Strain: Fixture & Process Analysis o 88 88 Fixture revalidation should be periodically performed o When probes are replaced o When fixture is altered o Supports are moved o Rewiring is done
  • 88. Example of Failure in Test Fixture at 32G, 270ips A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 89 1 X 3 3 4 4 4 4 2 3 3 3 4 4 3 4 3 3 4 4 4 4 4 4 5 4 4 6 4 4 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 4 3 3 X 3 3 4 Brd 001X ICH Dye and Pry fracture indications 3 4 X 3 4 4 4 4 4 4 4 4 4 4 4 4 3 3 4 4 4 3 3 3 4 4 4 4 4 3 3 X
  • 89. M. Ahmad, et al., Cisco, Apex, 2009. Laminate Relationship to Cratering 90
  • 90. Module 6: Prevention & Future Work 91
  • 91. Integral Technology “Zeta Cap” 92
  • 92. Zeta Cap – What is it? o o 93 Copper clad high Tg, CTE Z axis of 19 ppm/deg C. Fully cured dielectric. Used with standard prepregs or Zeta® Bond.
  • 93. 94
  • 94. 95
  • 95. 96
  • 96. Zeta Cap 97
  • 97. Zeta Pad Strength Failure Modes 98
  • 98. US PCB Shops Familiar with Zeta Cap o Western Region o o o o o o o o o o Midwest o o o o Global Innovation – Texas Minco – Minneapolis Holaday Circuits – Minnetonka East o o o o 99 Streamline Circuits Gorilla Circuits Via Systems – San Jose TTM – Santa Ana, Santa Clara DDI – Milpitas, Anaheim, Toronto Sanmina SCI – Costa Mesa, San Jose Hallmark – San Diego MEI - Anaheim HEI – Tempe, AZ Endicott Interconnect – New York Moog Printed Circuit Boards – Virginia Tech Circuits – Connecticut Compunetix – Penn
  • 99. Sherlock – Automated Design Analysis Tool o 100 With Sherlock Automated Design Analysis™ Software, by DfR Solutions, designers can identify potential bed of nails damage early in the layout process, before a bed of nails tester is ever designed, allowing for tradeoff analyses, saving costly board damage and redesign.
  • 100. Sherlock o Sherlock eliminates potential bed of nails damage by: o o o o 101 Automatically identifying any and all components on the circuit card that could experience cracking or failure during bed of nails testing. Prior to the ICT, the designer can: o Change test points o Change pogo pin pressure, or o Add /move board supports Optimize ICT process and reduce the likelihood of solder joint cracking or pad cratering caused by the bed of nails fixture. A Sherlock analysis is component-specific, allowing for more precise identification of at-risk areas whether you are testing a large BGA or simple chip resistor.
  • 101. Pad Cratering Conclusions o Pad Cratering is an increasingly common failure mode o o Easy to avoid detection and difficult to diagnose o o o Partial cracks riskiest since they escape and expand in the field Multiple paths for mitigation but few for true prevention No hard, fast rules for avoidance o 102 Catastrophic and non-reworkable Dependent on design, component, layout, process…
  • 102. Pad Cratering Recommendations o o Maintain awareness in design & manufacturing Evaluate each design o o o Test & Control are key o 103 No one size fits all criteria but some “rules of thumb” Validate results with destructive cross-sections Use multiple testing strategies to maximize success at finding and preventing failures
  • 103. References o Boundary Scan: A Practical Approach o o o o o o o o o o o 104 http://www.ems007.com/pages/zone.cgi?a=83457 Impact Performance of Microvia and Buildup Layer Materials and Its Contribution to Drop Test Failures, Dongji Xie*, Jonathan Wang**, Him Yu+, Dennis Lau+ and Dongkai Shangguan* *Flextronics International METHODOLOGY TO CHARACTERIZE PAD CRATERING UNDER BGA PADS IN PRINTED CIRCUIT BOARDS, Originally published in the Proceedings of the Pan Pacific Microelectronics Symposium, Kauai, Hawaii, January 22 – 24, 2008. COMPREHENSIVE METHODOLOGY TO CHARACTERIZE AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS, Originally published in SMTAnews & Journal of Surface Mount Technology, January – March 2009, Vol. 22, Issue 1. VALIDATED TEST METHOD TO CHARACTERIZE AND QUANTIFY PAD CRATERING UNDER BGA PADS ON PRINTED CIRCUIT BOARDS Originally published at the IPC/APEX 2009 Conference held in Las Vegas, NV, April 2009. Board Level Failure Analysis of Chip Scale Package Drop Test Assemblies, Nicholas Vickers, Kyle Rauen, Andrew Farris, Jianbiao Pan, Cal Poly State University. Assessment of PCB Pad Cratering Resistance by Joint Level Testing Brian Roggeman1, Peter Borgesen1Assessment of PCB Pad Cratering Resistance by Joint Level Testing Brian Roggeman1, Peter Borgesen1, Jing Li2, Guarav Godbole2, Pushkraj Tumne2, K. Srihari2, Tim Levo3, James Pitarresi3 1Unovis-Solutions, Binghamton, NY 13902, Jing Li2, Guarav Godbole2, Pushkraj Tumne2, K. Srihari2, Tim Levo3, James Pitarresi3 1Unovis-Solutions, Binghamton, NY 13902 MANUFACTURING QUALIFICATION FOR THE LATEST GAMING DEVICE WITH Pb-FREE ASSEMBLY PROCESS Ding Wang Chen, Ph.D., Alex Leung, and Alex Chen Celestica China and Celestica Corporate Technology Suzhou, China; Dongguan, China; and Toronto, Canada
  • 104. References o o o o o o o o o o o o 105 Pad Cratering Evaluation of PCB Dongji Xie*, Ph.D., Dongkai Shangguan*, Ph.D. and Helmut Kroener**, *FLEXTRONICS, San Jose, CA, ** Multek, Schongau, Germany Pad Cratering: Assessing Long Term Reliability Risks, Denis Barbini, Ph.D., AREA Consortium A New Approach for Early Detection of PCB Pad Cratering Failures, Anurag Bansal, Gnyaneshwar Ramakrishna and Kuo-Chuan Liu, Cisco Systems, Inc., San Jose, CA Validated Test Method to Characterize and Quantify Pad Cratering Under Bga Pads on Printed Circuit Boards, Mudasir Ahmad, Jennifer Burlingame, Cherif Guirguis, Technology and Quality Group, Cisco Systems, Inc. COMPREHENSIVE METHODOLOGY TO CHARACTERIZE AND MITIGATE BGA PAD CRATERING IN PRINTED CIRCUIT BOARDS Mudasir Ahmad, Jennifer Burlingame, and Cherif Guirguis, Technology and Quality Group, Cisco Systems, Inc. A New Method to Evaluate BGA Pad Cratering in Lead-Free Soldering, Dongji Xie, Ph.D.*, Clavius Chin, Ph.D.**, KarHwee Ang**, Dennis Lau+ and Dongkai Shangguan, Ph.D. *Flextronics International. The Application of Spherical Bend Testing to Predict Safe Working Manufacturing Process Strains, John McMahon P.Eng, Brian Gray P.Eng, Celestica. Investigation of Pad Cratering in Large Flip-Chip BGA using Acoustic Emission, Anurag Bansal, Cherif Guirguis and Kuo-Chuan Liu, Cisco Systems, Inc.,. PAD CRATERING: THE INVISIBLE THREAT TO THE ELECTRONICS INDUSTRY, Presented by Jim Griffin, OEM Sales & Marketing Manage, Integral Technology Pad Cratering Test Methods: AComparative Look Brian Roggeman & Wayne Jones, AREA Consortium VALIDATED TEST METHOD TO CHARACTERIZE AND QUANTIFY PAD CRATERING UNDER BGA PADS ON PRINTED CIRCUIT BOARD, Mudasir Ahmad, Jennifer Burlingame, Cherif Guirguis Component Quality and Technology Group, Cisco Systems, Inc
  • 105. Contact Information o Questions? o o o o 106 Contact Cheryl Tulkoff, ctulkoff@dfrsolutions.com, 512-913-8624 askdfr@dfrsolutions.com www.dfrsolutions.com Connect with me in LinkedIn as well!