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    Next_Generation_Packaging_AND_Qualification_Programs_2pp_ Next_Generation_Packaging_AND_Qualification_Programs_2pp_ Document Transcript

    • Next Generation Packaging andNext Generation Packaging and Qualification Programs ILTAM - December 4, 2011 Cheryl Tulkoff Senior Member of the Technical Staff ctulkoff@dfrsolutions com 1 ctulkoff@dfrsolutions.com Instructor Biography o Cheryl Tulkoff has over 22 years of experience in electronics manufacturing with any y p g emphasis on failure analysis and reliability. She has worked throughout the electronics manufacturing life cycle beginning with semiconductor fabrication processes, into printed circuit board fabrication and assembly, through functional and reliability testing, and culminating in the analysis and evaluation of field returns. She has also managed no cleang y g and RoHS-compliant conversion programs and has developed and managed comprehensive reliability programs. Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech She iso Cheryl earned her Bachelor of Mechanical Engineering degree from Georgia Tech. She is a published author, experienced public speaker and trainer and a Senior member of both ASQ and IEEE. She holds leadership positions in the IEEE Central Texas Chapter, IEEE WIE (Women In Engineering), and IEEE ASTR (Accelerated Stress Testing and Reliability) sections She chaired the annual IEEE ASTR workshop for four years and is also an ASQsections. She chaired the annual IEEE ASTR workshop for four years and is also an ASQ Certified Reliability Engineer. o She has a strong passion for pre-college STEM (Science, Technology, Engineering, and Math) outreach and volunteers with several organizations that specialize in encouraging pre-college students to pursue careers in these fields. 2
    • Next Generation Packaging Course Topics o Next Generation Packaging o PCB Supply Chain Best Practices: Selection and Qualification of Contract Manufacturers o Comprehensive Product Qualification Plan Development o PCBA Case Studyo PCBA Case Study 3 Agenda o 08:45-09:00 Welcome 09 00 10 00 Introduction to the Next Generation Packagingo 09:00-10:00 Introduction to the Next Generation Packaging o 10:00-11:00 3D Packaging Overview o 11:00-11:15 Coffee Break 11 15 12 00 3D P k B f & R ko 11:15-12:00 3D Packaging Benefits & Risks o 12:00-12:45 3D Packaging Implementation o 12:45-13:45 Lunch Break o 13:45-14:30 Selection and Qualification of Contract Manufacturers for PCBs o 14:30-15:15 Selection and Qualification of Contract Manufacturers for PCBAPCBAs o 15:15-15:30 Refreshments o 15:30-16:15 Test Plan Development Strategies o 16:15-17:00 Assessments, Virtual Qualification, and Case Studies o 17:00-17:15 Q&A 4
    • Introduction o What is ‘Next Generation’ Technology? o Materials or designs currently being used, but not widely adopted ( i ll hi h li bilit f t )(especially among high reliability manufacturers) o Carbon nanotubes are not ‘Next Generation’ o Not used in electronic applications o Ball grid array is not ‘Next Generation’Next Generation o Widely adopted 5 5 Introduction (cont.) o Why is knowing about ‘Next Generation’ Technologies important? o These are the technologies that youg y or your supply chain will use to improve your product o Cheaper, Faster, Stronger, ‘Environmentally-Friendly’, etc. o And sooner then you think! 6 6
    • Reliability and Next Gen Technologies o One of the most common drivers for failure is i i t d ti f t h l iinappropriate adoption of new technologies o The path from consumer (high volume, short lifetime) to high rel is not always clear o Obtaining relevant information can be difficult o Information is often segmented o Focus on opportunity, not risks o Sources are either marketing mush or confusing, scientific studiesstudies o Where is the practical advice? 7 7 Course Purpose o This course will provide you insight into next generation technologies at every level of packaging and production o Understand o Timelines (when is it coming?) o Benefits and Weaknesses (what are my risks?)( y ) o Implementation (how to be successful) 8 8
    • Challenges With 3D P k iPackaging ILTAM 9 3D Package Types o Many 3D Packaging Options o Package in Package (PiP) o Package on Package (PoP), PoP with Embedded CComponents o SiP – System in Package SoC System on Chipo SoC – System on Chip o Stacked die with wire bonds, some flip chip o Stacked die with edge connectionso Stacked die with edge connections o Stacked packages o Chip on Chip (CoC)o Chip on Chip (CoC) o 3D IC with Through Silicon Vias (TSV) 10
    • Stacked Packaging 11 11 Stacked Die o What is ‘stacked die’ packaging? o Also known as system in package (SiP) or 3D packagingpackage (SiP) or 3D packaging o Consists of two or more dice stacked in a chip scale package (CSP) using wire bonding, flip chip or a combination o One of the first patents filed by Micron Technology in 1993 (5291061) o Others by Toshiba in 1989 (4807021) and IBM in 1992 (5270261)(5270261) o Commercial interest started to accelerate in 1998 through 2000 12 12
    • Stacked Die (cont.) o Allows for efficient use of board real estate P i il d f d i ith dio Primarily used for memory devices or with memory die o Can also be used to combine custom chips with commercial off-the-shelf devices o Can potentially reduce system-level cost o Reduction in board complexity; reduction in size and weight o Most appropriate for portable commercial electronics o Standard ‘unground’ wafer thicknesses are 750 to 800 microns o 300 and 450 microns also available o Wafer thinning is necessary 13 13 Stacked Die (cont.) o Wafer thinning: Backgrinding with polishing step to remove stresses o Minimum thickness from 75 to 125 microns, depending upon vendor and wafer sizewafer size o Thinning tends to be performed by contract packaging manufacturers (Amkor, ChipPAC, ASE, Carsem, etc.) o Maintains maximum package heights of 1.2mm to 1.4mm o Next generation includes wafers down to 30 - 50μmo Next generation includes wafers down to 30 50μm o Handling technology becomes critical 14 14
    • Stacked Die Configuration o Die stacking technologies have been demonstrated up to 9 high stacks o Most stack ups are limited to 4 devices o Driven by complex test, yield and logistic limitations o Stacked die packaging comes in three flavorso Stacked die packaging comes in three flavors o All driven by need to provide ledges for wire bonding P id ‘ k ’o Pyramid or ‘cake’ configuration Smaller die areo Smaller die are placed on larger die 15 15 Stacked Die Configuration (cont.) o Silicon Spacers o SDP: Stacked Die Packageo SDP: Stacked Die Package o Same size die with spacer in-between S dd l fo Spacers add clearance for wire bonding o Not common o Overhango Overhang o Die are rotated orthogonally R i dd lo Rotation adds clearance for wire bonding 16 16
    • Stacked Die Case Study: 4GB Memory Card o Five stacked die fo One micro; four 1GB Flash o Wire bond interconnects o Pyramid stackingo Pyramid stacking o Total thickness o 50 mil (1.25 mm) o Die thickness o Flash: 62 micron Mi 75 io Micro: 75 micron 17 17 Stacked Die (cont.) o Why is stacked die considered ‘Next Generation’ for this presentation?presentation? o Limited market penetration outside ofp few consumer products o Increasing concerns over cost and reliability of Moore’s Law ill l i k iwill greatly increase market size o Introduction of through-silicon vias will radically change interconnect technologyinterconnect technology 18 18
    • Limited Market Penetration o There is still a pitched battle between stacked die, multi- chip modules (MCM), and system on a chip (SoC) o Question of economics, performance, and reliability o Economic example: Known Good Die (KGD) KGD can be assessed at wafer level for lower capacity deviceso KGD can be assessed at wafer level for lower-capacity devices, like NOR flash memory o For other chips, such as DSP and baseband processors, KGD is notp , p , readily available o Can greatly reduce yield after value-added activities, such as k ( 2 % f h f d )packaging (up to 25% of the cost of a device) 19 19 Apple 3G iPhone (July 2008)Apple 3G iPhone (July 2008) Samsung device is package-on-package (ARM + SDRAM)[with some SoC](ARM + SDRAM)[with some SoC] Numonyx device is two stacked die (NOR Flash + PSRAM)(NOR Flash + PSRAM) Toshiba device is four stacked die (8 GB Flash) - 16 GB Flash has eight stacked die (two stacks of four?) 20 20
    • Xilinx Vertex 7 o Virtex-7 2000T FPGA Device First to Use 2.5- D IC Stacked Silicon Interconnect Technology to Deliver More than Moore and 6.8 Billion Transistors, 2X the Size of Competing Devices 21 Images Courtesy of Xilinx Moore’s Law o Subscribing to Moore’s Law is becoming increasingly expensive and unreliable o $3.5 billion for Intel’s 45nm plant A t ti l i t t i i b 2009 d t RC d l do A potential interconnect crisis by 2009 due to RC delays and increased risk of IC wearout mechanisms Th i ht ki d f t k d k i id t ito The right kind of stacked packaging provides opportunity to ‘short-circuit’ this process o Double the transistors by simply mechanically joining two dieo Double the transistors by simply mechanically joining two die o What is the right kind of stacked packaging? Wi b d li i d i h l io Wirebonds are limited to peripheral connections http://www.physorg.com/news8649.html 22 22
    • Through Silicon Vias (TSV) o Subset of Stacked Die Package o Vertical holes through die o Wafer-Level Assembly o Wafer Thinning o Via drilling/filling o Wafer bonding 23 Through Silicon Vias (TSVs) o TSVs are very similar to their PCB counterparts o The hole tends to be plasma etchedplasma etched o Very high aspect ratios (10:1 to 15:1) o Concept mentioned in patent by Harris in 1995 (5682062)y ( ) o First patent mentioning TSV is with Micron in 2002 (6800930) C i l l h i do Commercial launch is expected between 2010 and 2014 24 24
    • TSV (cont.) o TSV is rarely justified by just miniaturization alone o More cost-effective to thin, stack and wire bond o TSV will be justified by performancej y p o Increase in inter-die I/O o Increase in bandwidth o Decrease in interconnect length http://www.intel.com/technology/itj/2007/v11i3/3- bandwidth/6-architectures.htm (August 22, 2007) 25 25 TSV Example: Micron Osmium 26 26
    • Additional Market Drivers o SoC provides the optimum performance, but futurep p p , generations face severe limitations o Large die size will reduce yieldg y o Test coverage and capability will be limited o Design cycles will be extended (9 to 18 months)g y ( ) o Issues with integrating analog (90nm features) and digital (45nm features) functions 27 27 Risks with Stacked Packaging o Mechanical damage (die cracking) o From the wafer thinning process o From the die stacking process o From injection molding process o Lot-specific increases in moisture sensitivity levelo Lot-specific increases in moisture sensitivity level o Due to excessive backside roughness from wafer thinning process o Inter-die delamination o Non-optimized curing process for die attach o Contamination from wafer thinning 28 28
    • Risks (cont.) o On-die contamination M bil io Mobile ion o Tends to be memory-specific (Flash, PSRAM, DRAM, etc.) o Mobile ions (e.g., metals, anions) on wafer surfaces cause degradation when depletion area in transistor wells becomes contaminated creating a chargedepletion area in transistor wells becomes contaminated, creating a charge loss o Increases refresh interval (tREF) or induces single bit failures o Backside o Diffusion of trace elements o Can increase likelihood of punch-through by changing b lk h t i tbulk sheet resistance o Likelihood of on-die contamination driven byy wafer thickness and junction temperature 29 29 Risks (cont.) o Stacking traps heat (high power dissipation) o Higher junction temperatures o Increase in upset events and degradation rates o Cracking of fragile low-k dielectric in low-compliance package architecture (TSV could make this worse) o Already seeing issues with underfill and flip chip devices o Increase in die-to-package volume ratiosp g o Higher stress on 2nd level interconnects Reduction in test coverageo Reduction in test coverage o Lower likelihood of successful root-cause analysis 30 30
    • Solutions o Stacked die must be qualified like any other technology o Most stacked die packaging has limited life expectations o Consumer electronics o ‘Consumable’ device (i.e., flash memory modules) o Qualification testing is currently focused on theseo Qualification testing is currently focused on these applications 31 31 Solutions (cont.) o You must initiate comprehensive testing if o Lifetimes are longer than 5 years o Environment is ‘non-commercial’ (elevated temperatures,( p , elevated humidity, vibration, temperature cycling) o Example concern o What is the vibration behavior of ledges when the epoxy or die attach is at elevated temperatures? o Physics of failure approach will be crucial 32 32
    • Future of Stacked Die o Akita Elpida Memory recently d t t d k ithdemonstrated a package with 20 stacked dies o Is this the future of stacked die? o Unlikely o Limitations on known die and reliability will likely prevent thisreliability will likely prevent this extreme example o The future lies in the ability to mix and match die as necessary o Power with logic, RF with memory, etc. o Reduction in commodity? Increase in customization? o Expect to see extensive penetration within three to six yearso Expect to see extensive penetration within three to six years 33 33 Package on Package (PoP) R t Co PoP Background o Configurations and Examples • Root Cause • Next Generation PoP • Through Mold Via o PoP compared to SiP o Assembly Through Mold Via o Warpage Issues o Drop Testing Impact o Thermal Cycles o Reliability o Underfill o Low-k dielectric 34
    • Benefits of PoP – Package on Package o The benefits of PoP are well known. They include: o Less board real estate o Better performance (shorter communication paths between the micro and memory) o Lower junction temperatures (at least compared to stacked die) G t t l th l h i ( t it t do Greater control over the supply chain (opportunity to upgrade memory and multiple vendors) o Easier to debug and perform F/A (again, compared to stackedo Easier to debug and perform F/A (again, compared to stacked die or multi-chip module or system in package) o Ownership is clearly defined: Bottom package is the logic manufacturer, the top package is the memory manufacturer, and the two connections (at least for one-pass) are the OEM 35 Package on Package (PoP) o A configuration where two packaged integrated circuits are placed directly on top of each otherare placed directly on top of each other o Rather than bare die Can also be known as stacked packageso Can also be known as stacked packages I b h k d ho Interconnects are between the top package and the bottom package and the bottom and the PCB T k di i ll i l i l k d dio Top package traditionally contains multiple or stacked die o Bottom package traditionally contains smaller / thinner didie 36 36
    • Stacked Packageg o The concept of stackedp packages has been around since the 1980’s o Patent 5,625,221 (1994) o Stackable BGAs first proposed i Miin Micron patent o Patent 6,072,233 (1998) 37 37 PoP Chronology o More recent terminology of package-on-package (PoP) can be traced back to ECTC 2003 (Nokia / Amkor) o Refers almost exclusively to stackable BGAs o Broad implementation in industry by 2005p y y o Standardized in 2006o Standardized in 2006 o JEDEC JEP95 Section 4.22 MO 266A Bottom MO 273A Topo MO-266A: Bottom; MO-273A: Top 38 38
    • PoP (Stacked BGAs) o Bottom Package H l d d t i to Has land pads on top perimeter to allow for top PoP attach o Molded using special process to keep perimeter clearkeep perimeter clear o Requires thin die and mold cap to allow for top package clearance o Top Package o Based on conventional stacked die BGA but larger ball size and thinner mold bodythinner mold body o Ball pitch and size constrained by need to clear bottom package P k b bl f b i l d h i d i io Packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board 39 39 PoP Stacked BGAs (cont.) o Both packages are relatively thin o Maximum height typically 1.4 to 1.6 mm o Focus tends to be on slimming top package o Thinning of bottom package can be difficult o Thinner substrate can increase warpage o Smaller ball size can impact drop testing and temp cycle S d d k io Standard package sizes o 15x15 mm, with 14x14 and 12x12 also available o 0.65mm pitch, with 0.5mm and 0.4mm availableo 0.65mm pitch, with 0.5mm and 0.4mm available o Ball size can vary from 0.45 to 0.35mm 40 40
    • Reuse of Technology for uP / Memoryfor uP / Memory Interface Flexible Processor & Memory Architectures: Bband Modem, Apps uP, DDR and NVM 41 Source: Mario Bolanos “Packaging Trends Applied Research Opptys at U. of Binghampton CAMM PoP Forecast 42
    • Smartphone advancements aided by PoP technology d f h b f PoP addresses integration challenges to enable and cost of ownership benefits. PoP addresses integration challenges to enable semiconductor advancements . . . . . . to cost affectively deliver physical world benefits. 43 PoP Configurationsg 44 44
    • PoP Examplesp o Stacked Package on Package (PoP): The placement is often arranged through a soldering operation, but can also be performed with other interconnectg p , p technology Example ofExample of package on package device from Samsung Example of package on package devices, with stacked die in h k feach package, from Mitsubishi 45 45 PoP Examples (cont.) 46 46 Texas Instruments
    • Why PoP? o Yield / Flexibility / Ownership o Package Test & Burn In before final assembly o No issues with known good die (KGD) o Memory can be easily upgraded o Also allows for multiple sourcing o Ownership is clearly definedo Ownership is clearly defined o Bottom package: Logic manuf. o Top package: Memory manuf. 47 o Board level connection: OEM 47 Die vs. Package Stack Analysis (Business model has huge impact on Cost of Ownership)(Business model has huge impact on Cost of Ownership) PoP100% % of Applications 3D SiP (Dominant for Applications processor + (Dominant f C b V i l Di Q 2 3 4 5 processor + complex memory stacking) 0% for Combo Memory & Digital + analog) Vertical Die Qty 2 3 4 5 Cumulative Die Yield High Low Die / Test Costs Low High stacking) Die / Test Costs Low High Require burn-in No Yes Die/Memory Sourcing Simple Complex 48 Sourcing flexibility No Yes Design flexibility No Yes
    • Thermal Comparisonp 49 49 PoP Uses o Dominant use o Integration of digital logic device in bottom package with combination memory devices (i.e. DRAM and flash) in top packagepackage o Top package typically stacked die o Some pure memory PoP solutions also available o Cameras / mobile devices are main users o Increasing interest from high rel industrieso Increasing interest from high rel industries 50 50
    • PoP Assembly Process o Assembly of PoP can be through one or two reflows o Most commonly single reflow (aka, one-pass)( , p ) T k i t i llo Top package is typically dipped before placement o Flux (sticky) or solder paste 51 51 PoP Assembly (cont.) o PoP can also be offered as a two-pass assembly o IDM assembles top and bottom package and places them in a carrier for board- l l bllevel assembly o Other assembly options include use of solder on pad (SoP) on bottom package 52 52
    • Solder on Pad (SoP) o Consists of solder balls h id f hon the topside of the bottom package o Designed to induce a larger solder joint collapse to absorb package warpageto absorb package warpage o Difficulties o Balls must be well aligned (limited self-alignment) T k lid ff th b llo Top package can slide off the balls during placement or reflow, leading to a poor solder joint or bridging 53 53 1st Generation PoP – Infrastructure Development OEMs Architecture stacking 12 major OEMs in Handset and DSC market adopting PoP I d tIndustry Standards JEDEC – JC.11.2 Design guide, JC11.11 POD, JC-63 pin outs Equipment Panasonic, Siemens, Fuji, Unovis, Assembléon, HitachiEquipment Panasonic, Siemens, Fuji, Unovis, Assembléon, Hitachi EMS / ODM 5 major EMS providers in production or development Logic IDM 15 major IDMs adopted PoP M IDM 8 j M li d t d P PMemory IDM 8 major Memory suppliers adopted PoP Full service – Develop, Design, Model, Standards, bottom, Amkor Full service Develop, Design, Model, Standards, bottom, top PoP, Modules, pre-stacked engineering samples, BLR Practical Components – stocks Amkor 12 14 & 15mm bottom / top DC samples 54 Practical Components – stocks Amkor 12, 14 & 15mm bottom / top DC samples www.amkor.com Design, stacking, test and Brd level reliability (joint study papers)
    • Design Factors Impacting Warpage o Mold o Material property • Die – Die size p p y o Shrinkage o Thickness Die size – Die Thickness • Laminate Substrate• Die attach – Properties – Thickness – Cu ratio – Material property – Thickness 55 – Routing Warpage o Many technical challenges present in PoP assembly Improper reflow profiles can lead to solder balls dislodging oro Improper reflow profiles can lead to solder balls dislodging or migrating off the pad o Excessive warpage can lead to solder ball bridging, solder slumping, head and pillow defects, or open jointshead and pillow defects, or open joints o Number one challenge in assembly is controlling and matching warpage of top and bottom packagesof top and bottom packages o More than 90% of the defects in PoP assembly are due to package warpage (cit. KIC) o Minimizing warpage is a trade off between materials, temperature control and time The extent and degree of warpage is increasing as substrates becomeo The extent and degree of warpage is increasing as substrates become thinner 56 56
    • Package Warpage o Due to mismatch in CTE between the substrate, mold compound, p and die o Die attach can also play a role o High Tg mold compounds are used to balance CTE mismatch between die and substratebetween die and substrate o Effect of mold compound becomes negligible at reflow temperatures 57 57 Warpage (cont.) o General warpage trend at room temp. o Inconclusive o Some claim bottom is smiling (positive, concave) while top is crying (negative, convex)convex) o Others claim the reverse o Partially dependent if CTE of mold compoundo Partially dependent if CTE of mold compound is more / less than substrate o Example: Periphery of bottom package is devoid of mold compound o At reflow temperature, exposed substrate could expand more compared to substrate under the mold compoundunder the mold compound o Desirable to have matching warpage 58 58
    • Warpage and Yields 59 59 Warpage and Yields (cont.) 60 60
    • Warpage Drivers: Die o Thinner die and smaller die tend to minimize warpage L / thi k di t d t d i i t RTo Larger / thicker die tend to drive crying at RT 61 61 Warpage and Reflow Profile Ramkumar 2008 European Electronic Assembly Reliability Summit 62 62 Ramkumar, 2008 European Electronic Assembly Reliability Summit
    • Recommendations for improving SMT and Stacking yield o Warpage data processing methods A BA Package corner to package corner B Array corner to array corner C Inner and outer D Inner and outer corners of ball matrix (diagonal) Ball matrix corner to corner (sides) o Appropriate methods Top Pkg Use Methods Bot Pkg Top Pkg C & D Use Methods * Method B to check for interference 63 Top Pkg Bot Pkg Use Methods B*, C & D Method B to check for interference of warped packages at the center Reliability: Drop Testing / Warpage E h b d d d 200o Each board was dropped 200 times per JEDEC JESD11-B22 o 1500g for 0.5ms o The bottom package was always first to fail o Inline with other studies N i ifi t diff i to No significant differences in top package reliability o Reliability seemed to be i d d f i ld dindependent of yields and warpage 64 64
    • Reliability: Drop Testing / Warpage Test vehicle was a mechanical dummy of a cell phone Process Development and Reliability Evaluation for Inline Package-on-Package (PoP) Assembly (Flextronics) Test vehicle was a mechanical dummy of a cell phone The drop-test was 3 cycles on six sides = 18 drops from 1.5m 65 65 Drop Testing (Results) 66 66
    • Drop Testing / Warpage (cont.) F diff t f il d Four different failure modes observed during drop testing  Failure mode 4 was only found on combination B  Combination B  Low yield with ENIG surface finish 67 67  Poor warpage alignment Underfill o Typically a filled epoxy o High modulus (>10 GPa) o Range of coefficient of thermal expansion (CTE) values (16 30 )(16ppm – 30ppm) I d t t fo Improves drop test performance o Reduces stress on interconnect due to substrate bending o Improves thermal cycling robustness o Reduce shear stress on solder o Links die and substrate to reduce thermal expansion i t h 68 mismatch 68
    • Underfill Design Considerations o Design Considerations for Package on Package Underfill o In PoP, the top and bottom packages are usually the isame size. o Both levels must be underfilled for good reliability. They also must be filled simultaneouslyThey also must be filled simultaneously. o The top layer underfills more slowly than the bottom layer because of the thermal delta between the top andlayer because of the thermal delta between the top and bottom levels. o In order to underfill both levels simultaneously, they, fluid must reach the top of the second level gap. 69 69 Reliability:Reliability: UnderfillUnderfill and Thermal Cyclingand Thermal Cycling • Temp cycle 70 70
    • UnderfillUnderfill and Thermal Cycling (cont.)and Thermal Cycling (cont.)UU Cy g ( )Cy g ( ) 71 71 Underfill and Temperature Cycling • Rapid time to failure for underfills D / F / G • Best reliability o No underfill or underfill with Tg > 110C (A and C) 72 72
    • ReliabilityReliabilityReliabilityReliability • Underfill is increasingly being considered for PoPg y g o Improves 2nd level reliability under drop testing • However, increasing indications that use of underfill may greatly reduce reliability under temperaturemay greatly reduce reliability under temperature cycling • Case Study (-40 to 125C) o With underfill: 300 cycleso e cyc e o Without underfill: >1000 cycles 73 73 Reliability o From this study, it was understood that underfill material improves the stress distribution in solder joints during temperature cycling test andstress distribution in solder joints during temperature cycling test and drop test. o Lower CTE & higher Tg in underfill were more effective than other factors in the temperature cycle performance.p y p o Temperature cycling test results show that the filler type underfills provides substantially improved temperature cycling performance over non filler type underfills. o Underfill A passed 2500 cycles under the JEDEC JESD22-A104C Condition G (– 40 ~ 125’C, 1cycle/hour). Additionally, it exceeded 400 drops as well. N fill t d fill hi h d th t bilit it i f 500o Non filler type underfills which passed the acceptability criteria of 500 temperature cycles and underfill G was shown good drop performances as well. Low modulus materials are more rubbery as to absorb the drop impacto Low modulus materials are more rubbery as to absorb the drop impact by way of deformation. o Non filler type underfill provides process benefits. It was easier to apply the rework process than filler type underfill. 74 the rework process than filler type underfill. 74
    • PoP Reliability – Drop Test o Package and board level reliability (drop test) o –Package level reliability is generally robust and leverages enabling technology developed for stack package o •Materials technology continues to improvegy p o –Board level reliability is key issue o •Drop test is most important for mobile application N d fill f b d i d i do –No underfill after board mount is desired o –Correct ball land finish, ball alloy, and design rule for each interface need to be used o –Package construction and warpagecontrol to allow for robust reflow and joint formation –Development of improved board mount equipment and processo –Development of improved board mount equipment and process o –Good board level reliability and drop test has been demonstrated even for large POP size 75 75 ReliabilityReliabilityReliabilityReliability • Underfill with optimum temperature cycling and drop performance o A (high Tg and high filler) • Important note o Low modulus materials are more rubbery as to absorb the drop impact by way of deformation o Non filler type underfill provides process benefits; easier to apply than filler type underfill 76 76 type underfill
    • Consumer Electronics o Drivers of technology improvement o 90nm  65nm  45nm o Demanded by their customersy (especially users of graphic intensive applications) o What has changed in IC technology with smaller feature sizes?sizes? o Introduction of Low-k Dielectric 77 77 Low-k Dielectric o Defined as dielectric constant < 3.0 i i i SiO2 Metal HM o Initiated at 90nm, common in 65nm o Provides improvement in performance o Shortens RC delay Low-k SiONo Shortens RC delay o Reduces power consumption (CV2f) SiON Copper o To lower the dielectric constant below ~2.7, porosity is increased o Reduces fracture toughness o Reduces modulus o Greatly increases likelihood of cracking LowK g (especially with certain underfills) 78 LowK Crack 78
    • Industry Response to Low-k Cracking Prevent Bump Crack L K Tg Prevent Bump Crack LowK Crack Prevent LowK Crack Optimum Underfill Properties Bump NVIDIA Confidential Modulus Crack o IC performance requirements drive all other aspects of electronic packaging o Improvement in low k dielectric? No Change in underfill? Yes 79 79 o Improvement in low-k dielectric? No. Change in underfill? Yes. Industry Response (cont.) o A number of IC manufacturers switched from high Tg (>130C) to low Tg (<80C) underfills Drivers: Bottleneck in Electronic Supply Chaino Drivers: Bottleneck in Electronic Supply Chain o Die foundry material limitations Contract packaging supplier recommendationso Contract packaging supplier recommendations o 1st Problem: Violated a cardinal rule of electronic packaging design o Never use material that has a transition temperature (Tg, lid ) i hi h d isolidus, etc.) within the expected operating range 80 80
    • Product Qualification o Flip chip devices with this new, low Tg underfill, passed all industry standard product qualification tests o -55C or -40C to 125C, 1000 to 3000 cycles o 2nd problem: Testing through a transition temperaturep g g p will not necessarily induce relevant failure mechanisms o Result: High rate of field failures o Relatively short period of time (within 2-10 months)o Relatively short period of time (within 2-10 months) o Relatively benign environment 81 81 Root Cause of Failure (No. 1) o If an underfill is used around its glass transitiong temperature o CTE typically changes more rapidly than Moduluso CTE typically changes more rapidly than Modulus o This can lead to a large increase in the expansion with a negligible change in the moduluswith a negligible change in the modulus o Can be demonstrated using compatibility equations 82 82
    • Results o Thin die (50 micron vs. 100 micron) Thick mold on top package (0 45 vs 0 35 or 0 25 mm)o Thick mold on top package (0.45 vs. 0.35 or 0.25 mm) o Thick substrate o Top package (0.21 vs. 0.16 or 0.12 mm)p p g o Bottom package (0.36 vs. 0.26 or 0.21 mm) o Large standoff on top package (0.45 vs. 0.40 or 0.35 mm) M di d ff b k (0 23 0 28 0 18 )o Medium standoff on bottom package (0.23 vs. 0.28 or 0.18 mm) Almost all of these parameters move towardso Almost all of these parameters move towards minimizing package warpage o Problem: Except for thin die, PoP design is moving in thep , g g opposite direction 83 83 PoP and Temp/Power Cycling (cont.)p/ y g ( ) o There are concerns regarding the insufficiency of uniform temperature cycling in PoPcycling in PoP o Especially since warpage can be sensitive to localized temperature gradients o To overcome this limitation JESD22-A105Co To overcome this limitation, JESD22-A105C has been developed o Applies temperature excursions and power cycling ASE modeled this effecto ASE modeled this effect o PoP test vehicle: VFBGA on SPBGA o Solder: SnPb o Temp cycle: -40C to 125C o Results: Minimal difference between temp cycling and temp + power cycling o High thermal conductivity likely minimizes temperature differentialp o Note: Modeling did not take into consideration the influence of tensile and compressive stresses Wang, 2007 EPTC 84 84 g, Very-thin profile fine-pitch ball grid array (VFBGA) Stacked package ball grid array (SPBGA)
    • Warpage Resolution o High Density PoP (Package-on- Package) and Package Stacking Development o Ways around package warpage o Solder on pad (SOP) o While previous PoP BLR investigations showed a tendency to failure at the bottom joints e see that the finer pitchjoints we see that the finer pitch resulted in numerous failures on the top joints early in the testing in leg 3. For this reason a betterg composition of top package ball and bottom package SOP was selected in leg4 which improved the BLR reliabilitythe BLR reliability 85 85 Typical Test to Spec Resultsyp p o Test condition, sample size, and pass/fail criteria should be shown. 86 86
    • Next Gen PoP: Increased - Integration, Miniaturization Performance & CollaborationMiniaturization, Performance & Collaborationmics Signal processing µP integration Bband + applications - increased pin counts µP core speed 2 – 3X w/ each node (1GHz @ 45nm) emDynam µP core speed 2 3X w/ each node (1GHz @ 45nm) Transition to FC accelerates from 65nm Memory Interface Higher speed memory interface SDRAM – DDR –> LP DDR2 Wid b 16 32 ngSyste ges Wider memory bus 16 – 32 Shared to split bus to (2 channel) architectures Increased pin counts with size reduction requires 0.4mm pitch top and bottom Packagin Challeng c e sed p cou s w s e educ o equ es 0. p c op d bo o Warpage control with thinner / higher density PoP stacks Signal integrity optimization, decoupling cap integration Power efficiency and thermal mngmt Si / k d i f P P t ti i f t / f 400Processor I/O 600 800 Si / pkg co-design for PoP to optimize for cost / performance Device Dynamics 65nm 400mW 64mm² CMOS Node Peak Power Ave. Die Size 45nm 800mW 50mm² 28nm 1.2 W 50mm² 87 D 2008 2010 2012 1st Gen PoP Technologies limit PoP I/O and Bottom Stacked Di D i R i i N T h lDie Density – Requiring New Technology o Die stacking in bottom package requires thicker mold cap o New memory architectures require higher I/O interfaceso New memory architectures require higher I/O interfaces o Higher Semiconductor density requires package size reduction o Thin form factors and increased battery size require thinner PoP stacks Improved warpage control required when go thinner with higher densityo Improved warpage control required when go thinner with higher density o A new bottom PoP technology is needed to continue growth 88 Multiple die in bottom package0.50mm pitch
    • Thru Mold Via Technology (TMV®) o Enabling technology for next generation PoP reqmts o Improves warpage control and PoP thickness reduction TMV removes bottlenecks for fine pitch memory interfaceso TMV removes bottlenecks for fine pitch memory interfaces o Increases die to package size ratio (30%) o Improves fine pitch board level reliability o Supports Wirebond, FC, stacked die and passive integration 89 Construction and package stack-up for the TMV PoP T t V hi l t d t SMTAI 2008Test Vehicle reported at SMTAI 2008 Reference : "Surface Mount Assembly and Board Level Reliability for High Density PoP (Package on Package) Utilizing Through Mold Via 90 Interconnect Technology - Joint Amkor and Sony Ericsson", Paper
    • TMV® Memory Interface Scaling Benefit 91 TMV® Interface Pitch Considerations o 0.5mm TMV pitch o 12mm 168 2 row In HVM with 0.35mm mold cap (2+0 wirebond stack) o 14mm 240 3 row In HVM with 0.28mm mold cap (single die FC die) o 0.4mm TMV pitch o In HVM with 0.25mm mold cap (single die FC) o TMV solder ball size and hole size is selected for SMT yield while avoiding solder bridging 92
    • Recommendations for improving TMV® PoP SMT Stacking Yield o Reflow o Reflow peak temperature: 235 – 245C Ti b Li id 45 75 Good Joint Non-wet 245C, Time above Liquidus: 45 – 75 sec o Avoid long soak time at flux activation k l 180’C Flux temperature, excessive soak time results in flux burn off/dry off causing Head- in-Pillow joints for top to bottom k i t t Temp 150’C Long prehea t Short preheat Dried flux package interconnects: o Recommendation: Choose flux with recommended pre-heat time of 60 to 75C b 150 180C Time (sec) 150’C 0 11062 75C between 150 – 180C o Additional Recommendations o Process development on flux or paste ( ) p p material and dip depth o Increasing top package ball size to compensate for excessive warpage of 93 compensate for excessive warpage of top package Viking RAMStack 94
    • Summary o 390million PoP components shipped in 2010 up from < 5 million in 2005. Forecasted to grow at same high rate as Smartphones o DDR2 2 channel and other new memory architectures driving higher density PoP memory interfaces Amkor pioneered 1st Generation PoP (PSvfBGA) and nowo Amkor pioneered 1st Generation PoP (PSvfBGA) and now leading in Next Gen high density PoP with TMV® technology shipping in HVM o One pass SMT PoP stacking enables optimization of supply / logistics and lowest total cost of ownership o Amkor and Universal Instruments planning 14mm 620 / 200 TMVo Amkor and Universal Instruments planning 14mm 620 / 200 TMV PoP SMT stacking study and industry report to facilitate SMT yield / quality optimization 95 Copper Wire Bonds 96
    • Copper Wire Bonding – Market Status o Initial marketing activities for fine pitched applications initiated in mid-2000’s o Replacement of gold wire bonding initiated in 2007-2008 due to gold pricing, but stunted due to Current state of suppliers but stunted due to economic recession o Rapid implementation and replacement ofp gold wire bonding staring in 2009 97 Market Status (cont.) o As usual with new technologies, significant lag between supplier implementation and OEM awareness C t t t f OEMCurrent state of OEMs 98
    • OEM Status 99 Quality and Reliability Concerns o Current issues are quality driven (i.e., ball lift), while concerns regarding longer-term reliability performance remain 100
    • Design Changes in Response to Copper Wire Bonding o The major issues in regards to copper wire bonding are bonding force (and risk of silicon damage) and red cedbonding force (and risk of silicon damage) and reduced nobility (greater risk of corrosion) o In response, some suppliers have been forced to o Redesign the bond pad and underlying structure Modified the molding compound (lower pH reduced halogeno Modified the molding compound (lower pH, reduced halogen content) o Still unresolved o Preferred bond pad material (Al and Pd) o The need for Pd coating over copper wire bondo The need for Pd coating over copper wire bond o Type of forming gas used in process (N2 or N2H2) 101 Current Status - Reliability o Review of qualification results from suppliers have not identified any long term reliability issues at this time o Note: High motivation to obscure these results 102
    • Major concerns identified by DfR o Palladium (Pd) coating creates galvanic couple with copper o Studies have demonstrated thinning or loss of Pd coating during bonding o Uncertain if JEDEC test with acceleration factor based on Peck’s equation (based on aluminum/gold galvanic couple) is still valid o Push out of aluminum pad Could result in subsurfaceo Could result in subsurface cracking (metal migration?) o Uncertain if existing JEDECg temp cycling test is sufficient to drive crack growth 103 Physics-of-Failure Approach to Integrated Circuit Reliability 104
    • Integrated Circuit Reliability – The Concerng y 1000 Process Variability fi 100 Mean Airplanes confidence bounds 1 0 10 Mean Service life, yrs. Computers laptop/palm 0.1 1.0 cell phones 0.5 m 0.25 m 130 nm 65 nm 35 nm Technology 1995 2005 2015 Year produced Known trends for TDDB, EM and HCI degradation (ref: extrapolated from ITRS roadmap) 105 IC Wearout: Background Guaranteeing the conventional 10-year life of ICs is going to become increasingly difficult….the progressive degradation of the electrical characteristics of transistors and wires will start dominating over abrupt functional failures. Furthermore, the mean-time-to-first-soft- break will significantly diminish." Antonis Papanikolaou, IMEC, Leuven, Belgium, 2007 …the progress of Moore's Law means that transistor wear-out and statistical performance issues are beginning to cross over from the realm of academic and hypothetical discussion to real-world R&D engineering. EE Times Europe 2007EE Times Europe, 2007 ”The notion that a transistor ages is a new concept for circuit designers,” says Chris Kim (U of Minnesota) Transistor aging has traditionall been the baili ick of engineers ho design theMinnesota). Transistor aging has traditionally been the bailiwick of engineers who design the processes that make transistors; they also formulate recipes that guarantee the transistors will operate within a certain frequency and other parameters typically for 10 years or so…But as transistors are scaled down further and operated with thinner voltage margins, it’s becomingp g g , g harder to make those guarantees… transistor aging is emerging as a circuit designer’s problem. IEEE Spectrum, June 2009 106
    • IC Reliability (Example) - Microprocessors o 90nm Microprocessors o 150-200 FIT over 5 years (0.11% AFR) Part Number Description Node Field Return Failure Rate (FIT) MT16LSDF3264HG-10EE4 Micron 2GB SDRAM 130nm 689 M470L6524DU0-CB3 Samsung 512MB SDRAM 130nm 415 HYMD512M646BF8-J Hynix 1GB DDRAM 130nm 821 MC68HC908SR12CFA Freescale Microcontroller 90nm 221 RH80536GC0332MSL7EN Intel 1.8GHz Pentium 90nm 144 o 65nm Microprocessor RH80536GC0332MSL7EN Intel 1.8GHz Pentium 90nm 144 3X increase in o 422 FIT over 5 years (0.37% AFR) AFR with each decrease in node size 107 10 Future Performance (45 and 32nm) o Introduction of new technology corresponds to projections of 10 Dielectric breakdown corresponds to projections of Moore’s Law o 70% feature scaling every 2-3 years 8 0) Future… In breakdown failure rate vs. feature size years o Smaller and Faster circuits cause o Higher current densities L lt t l 4 6 FIT(000 In production design Estimated o Lower voltage tolerances o Higher electric fields 2 production Measured o Inherent Si-based failure mechanisms are manifested at these minute feature sizes 180 130 90 65 45 0 Feature size, nm Figure adapted from industry published data, 2008 108
    • Industry Testing Falls Short o Limited degree of mechanism-appropriate testingg pp p g o Only at transition to new technology nodes o Mechanism-specific coupons (not real devices)p p ( ) o Test data is hidden from end-users o Questionable JEDEC tests are promoted to OEMs Li i d d i (1000 h ) hid b h io Limited duration (1000 hrs) hides wearout behavior o Use of simple activation energy, with incorrect assumption that all mechanisms are thermally activated can result inthat all mechanisms are thermally activated, can result in overestimation of FIT by 100X or more 109 Issues Inherent to CMOS Design Electro- i ti Gate oxide G t Conducting channel Gate oxide G t Conducting channel Trench isolation migration oxide Gate Source Drain Gate Drain Source channel P+ P+ P-well N+ N+ N-substrate Oxide breakdown Hot carrier Negative biasbreakdown injection Negative bias temperature instability Artist depiction of CMOS transistors 110 p
    • Mitigation Through Design? TDDB o Time Dependent Dielectric Breakdown (TDDB) N t ti d d t ft llo Not so time dependent after all o During feature scaling, the gate oxide thickness is scaled down o Power supply voltage is approximately the same as previous node o Increase in electric field on gate dielectric due to smaller thickness o What does this mean? o Instead of cumulative degradation from multiple breakdown siteso Instead of cumulative degradation from multiple breakdown sites causing failure after an undefined interval, one (1) breakdown site may cause immediate failure o Mitigated by:M g y o Doping the dielectric (however, each dopant causes other issues) o High-k and Low-k dielectrics (scaling issue remains) Ch i h / h f i fo Changing the geometry/topography of transistor features (expensive) 111 Mitigation Through Design? EM o Electromigration (EM) o Dependent on conductor materials o Effects have already been mitigated a few times, but not solved o Black’s equation predicts time-to-failureo Black s equation predicts time to failure o Latest conductor change to a better Al + Cu alloy (~0.13 micron) o Mitigated by: °o Changes in trace geometries, polygons versus 90° angles, and trace width o Drastic change in materials, i.e. carbon nanotubes or grapheneo as c c a ge a e a s, e ca b a ubes g ap e e o Additions of more copper, silver, gold, etc. Damaging effects of EM on conductors 112
    • Intrinsic Behavior and Wearout o Wearout because of transistor design o MOSFETs operate using electric fields (“field effect”) o BTI and HCI are driven by electric fields o New architectures experience these modes, i.e. FLASH memoriesp , o Floating gate transistor makes use of forced HCI and Fowler- Nordheim tunneling to store charge on the floating gate Ph f l d h l ( i ) i i ffi io Phenomenon of electrons and holes (carriers) gaining sufficient energy to overcome the direction of induced current and become injected in the gate oxide Depiction of hot carrier effects on MOSFET 113 Intrinsic Behavior: HCI and BTI o Hot Carrier Effects or Injection (HCI) Characteristics o Caused by a single carrier gains sufficient kinetic energy, or o Multiple carriers undergoing collisions that force them out of the directional path of electric field (the conducting channel) o HCI has inverse Arrhenius relationship o Activation energy -0.2 to -0.1 eV o Lower temperatures ( ~35 to ~55°C) increase vulnerability o Bias Temperature Instability o Combined bias & temperature stresses are required for activation o Fluctuations in temperature (overall device + self heating property) o High temperatures cause molecular instability o Requires lower electric fields than HCI o Trap formation from electric fields are worse under negative bias (positive bias is ~90%+ recoverable) Transistor stress states relating to HCI/NBTI damage (V /V curve) 114 HCI/NBTI damage (Vin/Vout curve)
    • Generic, Industry Accepted Models o Parameters that drive failure T t EM o Temperature o Current and Current Density o Voltages HCI o Voltages o Extrapolate from test to field TDDB NBTI 115 Modeling a Solution o Create an easy to use software tool that can be used by l l d l fmultiple disciplines of engineers o Accessible component data (datasheet limitations) A ti i t d fi ld diti d t to Anticipated field conditions and component stresses o With minimal access to manufacturer data o Sometimes only censored data is availableo Sometimes only censored data is available o Back to the fundamentalso Back to the fundamentals o Transistor theory and circuit analysis o Physics-of-Failure (PoF) degradation modelsy ( ) g 116
    • IC Lifetime Prediction Methodology o Models the simultaneous degradation behaviors ofg multiple failure mechanisms on integrated circuit devices d f bl h d ho Devised from published research literature, technological publications, and accepted degradation models from: o NASAJPL o University of Marylando University of Maryland o Semiconductor Reliability Community 117 What Influences Failure Rate? o Integrated circuit materials and complexity o Information gathered from component documentationo Information gathered from component documentation o Technology node or feature size (i.e. 90nm) o Corresponding material set (e.g. Si, GaAs, SiGe, GaN and SOI) o Functional complexityo Functional complexity o Identified as functional groups within a circuit o Operating conditions o Voltages frequencies currents and temperatureo Voltages, frequencies, currents, and temperature o Degradation mechanisms P F k wl d d l io PoF knowledge and analysis o Transistor stress states o Functional group susceptibility o Electrical and thermal conditions 118
    • Transistor Stress States o Establish relevancy of failure mechanisms and inputs into PoF algorithms based on o Quantity and location of transistors within circuit o Probabilistic likelihood of applied operation conditions through background simulation of each functional groupbackground simulation of each functional group Track (sample) & Hold Transistor stress state analysis on Track and Hold functional group 119 Mathematical Theory o Model of a device failure rate considering the tiers of system and device level inputs λ i h f il f h d i d l io λT is the failure rate of the device under analysis o λi is the normalized failure rate of a failure mechanism within a given functional group K i t t d fi d b th i ht t f f ti l F it io Ki,F is a constant defined by the weight percentage of functional group F as it is affected by the ith failure mechanism o PF is the probability of functional group failure from one functional group cell N i th t t l b f ll i h f ti lo NF is the total number of cells in each functional group o N is the total number of functional groups across all types o Acceleration factors can be applied at the transistor level to extrapolate from known device test conditions to a known system field environment         iFiFFT KPNNN  , 120
    • Snapshot of the Software Tool o Inputs: o Component information o Feature size o Complexity o Test data o Operating modes o Electrical conditions o System Information T t filo Temperature profiles o Duty cycle o Confidence level Outputs:o Outputs: o Device reliability o Device failure rate 121 Example: National Semi 12-bit ADC System Duty Cycle Peak Temperature (°C) Percentage of Calendar Year 31.25% 40 4.1% 45 17.8% 50 21.9% 55 12.6% 60 20.8% 70 22.7% System Temperature Profile Failure rate graph from calculator Part Number Process Field Voltage Test Voltage Field Temperature Test TemperaturePart Number Technology Voltage (V) Voltage (V) Temperature (°C) Temperature (°C) ADC124S021 350nm 3.3 3.6 Profile 85.0 Functional group Breakdown Device characterization 122 The resultant failure rate is based on full utilization of device features under these specific conditions
    • Validation Study CAP 1% TRANSISTOR o Motorola field return data was gathered from a family of TRANSISTOR 19% gathered from a family of telecommunication products o 56 different ICs comprised 41.5% of the failed part population CARD 44% RESISTOR 8% RESONATOR 6% the failed part population o The validation activity was utilized failure data from 5 integrated circuits IC 8% INDUCTOR 0.07% failure data from 5 integrated circuits IC 21% DIODE 0.13% FILTER 0.02% FUSE 0.54% 123 Statistical Analysis on Field Returnsy o Failure rate was calculated from raw data o Environmental conditions to determine in field operating temperatureo Environmental conditions to determine in-field operating temperature o Thermal measurements to determine power dissipation o Cumulative failure distributions o Weibull o Exponential 18 20 600 000 700,000 8 10 12 14 16 nthlyFailedICs 300,000 400,000 500,000 600,000 eWorkingMonths Cumulative Working Months Monthly Failed ICs 0 2 4 6 8 03 03 04 05 06 07 08 08 Mon 0 100,000 200,000 Cumulative Extracted graphs from statistical 124 Feb-0 Dec-0 Oct-0 Aug-0 Jun-0 Apr-0 Feb-0 Dec-0 Extracted graphs from statistical analysis of field returns
    • Lifetime Prediction P t N b D i ti V d Node Field Calculated Test Vdd Field Vdd Test Component Information: Part Number Description Vendor Technology Temp. (C) Temp. (C) (V) (V) MT16LSDF3264HG-10EE4 256MB DRAM Micron 150 nm 42 62.28 3 3.3 M470L6524DU0-CB3 512MB DRAM Samsung 100 nm 42 70.00 2.5 2.7 HYMD512M646BF8-J 1GB DRAM Hynix 110 nm 42 66.68 2.6 2.7 MC68HC908SR12CFA Microcontroller Motorola/ Freescale 90 nm 40 77.40 5 5.5 RH80536GC0332MSL7EN Pentium Processor Intel 90 nm 58 99.70 1.276 1.34 1,000 1,200 Simulation FR Field FR, Rough Estimtaion 600 800 ureRate[FIT] Point Estimation of FR According to Weibull Analysis Upper/Lower Limits of FR According to Weibull Analysis Failure rates and limits 200 400 Failu 125 0 256MB DRAM 512MB DRAM 1G DRAM Microcontroller Pentium Processor Comparison of Results – JEDEC 47D HTOL o Typical High Temperature Operating Life (HTOL) Test o Stated purpose is to simulate many years of operation at ambient, by testing at elevated temperatures and voltages o Test 77 pieces/qualification lot for 1000 hrs at 125˚C (junction) o Zero failures A l i Fo Acceleration Factor o Accelerate via Arrhenius model with Ea=0.7 eV o Result 3 (23 ) f C fo For 3 lots (231 pcs) and operating temp of 55˚C, the field operating time is ~18 million hours. At 60% confidence, the failure rate is 51 FITs 51730689256MB DRAM HTOLCalculatedFieldP/N 51249220microcontroller 511012821IGB DRAM 51418415512MB DRAM 126 51291144microprocessor
    • Validation Study o Multi-mechanism approach is far more accurate than other existing methodologies and does not require any field data D i i Failure in Time (FIT) (failures per billion operating hours) Description ( p p g ) Field Sherlock JEDEC (Ea = 0.7eV) SR-332 MIL-HDBK- 217F DRAM (256MB) 689 730 51 15 18DRAM (256MB) 689 730 51 15 18 DRAM (512MB) 415 418 51 15 18 DRAM (1GB) 821 1012 51 15 18M ( G ) 8 0 5 Microcontroller 220 249 51 27 18 Microprocessor 144 291 51 67 2691 127 Application of Results o Industry Standards o VITA 51.2, Physics of Failure Reliability Predictions o MIL-HDBK-217J, Reliability Prediction of Electronic Systems Addition of Physics of Failure requirementso Addition of Physics-of-Failure requirements o IEC TS 62239, Preparation of an Electronic Component Management Plan o Addition of a wearout requiremento Addition of a wearout requirement o Certification requirements o ARP 4761o ARP 4761 o ARP 5890 o Platform customer requirementsq 128
    • Where Can We Go From Here? o Future roadmap of existing features: 65 45 32 22 h l io 65nm, 45nm, 32nm, 22nm technologies o Additional functional groups o Digital including logic and conditioners (e.g. gates)g g g ( g g ) o Analog for signal processing (e.g. opamps) o Processor based (DSP, FPGA, etc) C bl l d d f lo Customizable equivalent circuits and automated functional group analysis for ASIC design “Expert mode”o Expert mode” o Modification of all default parameters o Tradeoff analysiso Tradeoff analysis o Performance vs. Reliability 129 Case Study: The Challenges of Co- D i Wh Sili P hDesign: When Silicon Pushes Packaging Too FarPackaging Too Far 130
    • Packaging Revolution Embedded Devices Stacked Packages Stacked Die Through-Silicon Vias New Substrate Materials Moore’s Law will be dependent on Packaging! 131 p g g Nature of Component Industry o Silicon Drives Packaging o Packaging must respond to Silicon o Silicon does not respond to Packagingp g g o Acceptance of materials is driven by supplier activitieso Acceptance of materials is driven by supplier activities and menu-driven stress testing o Will co-design work in this environment? 132
    • Case Study: Low-k Dielectric o Defined as dielectric constant < 3.0 SiO2 Metal HM o Initiated at 90nm, common in 65nm Low-k o Provides improvement in performance o Shortens resistance-capacitance (RC) delay Reduces power consumption (CV2f) SiON Copper o Reduces power consumption (CV f) o To lower the dielectric constant below ~2.7, it i i dporosity is increased o Reduces fracture toughness o Reduces moduluso Reduces modulus o Greatly increases likelihood of cracking (especially with certain underfills) LowK Crack 133 Underfill o Typically a filled epoxy o High modulus (>10 GPa) o Range of coefficient of thermal expansion (CTE) values (16ppm – 30ppm)30ppm) o Improves drop test performanceo Improves drop test performance o Reduces stress on interconnect due to substrate bending o Improves thermal cycling robustness o Reduce shear stress on solder o Links die and substrate to reduce thermal expansion mismatch 134
    • Industry Response to Low-k Cracking Prevent Tg Prevent Prevent Bump Cracks Prevent Dielectric Cracks Optimized Underfill Properties (?) Modulus o IC performance requirements drive all other aspects of electronic packagingp g g o Improve in low-k dielectric? No. o Change in underfill? Yes. 135 Industry Response (cont.) o Most IC manufacturers switched underfills o From: Glass transition temperature (Tg) > 130C o To: Tg < 80Cg o Driven by Electronic Supply Chaino Driven by Electronic Supply Chain o Classic bottleneck; little diversification o Die foundry material limitationso Die foundry material limitations o Contract packaging supplier recommendations 136
    • Root-Cause of Failure: #1 o Violation of a cardinal rule of electronic packaging design Never use material that has a transition temperature (Tg solidus etc ) withintemperature (Tg, solidus, etc.) within the expected operating range 137 Root-Cause of Failure (cont.) 10.00 120 140 1.00 lus(MPa) 80 100 CTE 0.10 orageModu 40 60 (ppm/o C) 0 01 Sto 0 20 40 Storage Modulus CTE o Near the Tg CTE changes more rapidly than modulus 0.01 35 45 55 65 75 85 95 105 Temperature (o C) 0 o Near the Tg, CTE changes more rapidly than modulus o Large increase in the expansion with negligible change in the modulus can result in significant solder tensile stresses 138
    • Rise in Tensile Stress  T High stresses generated            2211 12 11 EAEA T F in the solder due to CTE increase before modulus decrease  2211 139 Effect of Mean Tensile StressEffect of Mean Tensile Stress  As mean tensile stress increases, fatigue lifetime drops due to diminished recovery of accumulated damage  Example: stress-controlled fatigue at 42 MPa amplitude 0 MP lif ti f 15K t 35K l mean = 0 MPa: lifetimes of 15K to 35K cycles  mean = 7 MPa: lifetimes of 100 to 1K cycles  For mean compressive stress or strain, recovery processes dominate; fatigue life is effectively infinite  At comparable stress amplitudes, lifetime in tension is up to 100X less than that in shearthan that in shear 140
    • Influence of Temperature o At temperatures below room temperature, mean stress trends compressive o At temperatures above Tg, the max principal stress in the solder bump transitions to shear Temps far above TgTemps near Tg 141 Product Qualification o Devices with this low Tg underfill passed all industry standard product qualification tests o JEDEC JESD47 Nonhermetic Package Qualification o Perform temperature cycling and then extrapolate lifetime using Coffin-Manson (CM) or Norris-Landsberg (NL) 142
    • JESD47 (Coffin-Manson) 143 Root-Cause of Failure: #2 o Assuming that industry standard testing is appropriate for new materials o Red Phosphorus is classic example T ti th h th t itiTesting through the transition temperature did not induce relevant failure mechanisms 144
    • End Result 1,000,000 Cycles to 100,000 y Failure 25C / Peak Temp (1x) 10,000 25C / Peak Temp (1x) Tg  3C (10x) 1,000 Tg  3C (10x) 100 Tg Numerous temperature transitions through the critical temperature range decreases the life by an order of magnitude Peak Temperature (oC) Tg 145 Moving Forward o Packaging Industry must demand equality with Silicon o Packaging Industry must reduce overreliance on material l h isupply chain o Visco-elastic and visco-plastic behavior of underfill crucial to understanding tensile stress driven failuresunderstanding tensile stress driven failures o Still not adequately characterized by suppliers o Packaging Industry must transition to best-in-class reliability assurance o Toyota Mizenboushi Method 146
    • Toyota Mizenboushi Method o Good Design o Good Discussion – Design Review Based on Failure Modeo Good Discussion Design Review Based on Failure Mode (DRBFM) o Good Dissection – Design Review Based on Test Results (DRBTF)(DRBTF) 147 Good Design o Recognize and reuse successful aspects and techniques of past products o Identify, minimize and manage disruptive influences of changes and new technologies M l d h do May include changes in usage conditions or environments. o Minimize the number of changes in a single product o Comprehend the impact of interface where different materials or parts are connected together o Design in features that can make the presence of budding problems visible or what would be called prognostics 148
    • DRBFM o Similar to a Failure Mode and Effect Analysis (FMEA), but… o DRBFM like everything else at Toyota was designed as ao DRBFM, like everything else at Toyota, was designed as a “lean” process o Focuses only on areas of change, interfaces, and risk managementy g , , g in a new design o Documents concerns, effects, detailed causes and control features based on the knowledge of e perienced prod ct engineersbased on the knowledge of experienced product engineers o Purpose: To make risks related to the changes visiblep g 149 DRBTF o Test result analysis process that goes beyond pass/fail o Re-assess test conditions based on DRBFM o Test to failure is default o Evaluate test results for inconsistent performance o Parts from life tests are closely examined for signs ofy g degradation o Drive communication o Document observations o Consider effect on customer D t i if ti ti i i do Determine if corrective action is required o Provide feedback to suppliers and design team 150
    • Conclusion o Future is very bright for Packaging Industry o Success of Moore’s Law depends on it! o Component industry must undergo a radical change for the co-design of complex packaging to succeedg p p g g o Lessons of Red Phosphorus were NOT learned 151 PCB Supply Chain Best Practices 152
    • Executive Summary o PCBs should be considered critical components or a critical commodity. Without stringent controls in place for PCB supplier selection, qualification, and management, long term product quality and reliability is simply not achievable. This section will cover some common best i d d i f fpractices and recommendations for management of your PCB suppliers. 153 Why Do We Care About PCBs?Why Do We Care About PCBs? o Printed Circuit Boards provide the foundation upon which electronic devices are buildelectronic devices are build o Solder is the mortar that holds it together A poor foundation produces a problematic houseo A poor foundation produces a problematic house o A weak or incorrectly specified PCB or poor soldering willp g produce an unreliable electronic device. 154
    • Why Do We Care About PCBs? o Summary of PCBA root-cause analyses.y o Industry wide o Failures during qualification or t t itat a customer site were reviewed o Failure sites located within capacitors and printed boards comprise the majority of field failuresfailures o Provides guidance for the focus of quality and reliability assurance activities 155 How Do PCBs Fail? o Conductive anodic filaments (CAF)( ) o Laminate / Prepreg issues o Plated through holes (PTHs) o Drilling / Plating issues o Electrochemical migration (ECM) Contamination / Cleanliness issueso Contamination / Cleanliness issues o Solderability / Solder Embrittlement o Final Finish issues o Contamination / Cleanliness issues o Delamination o Cratering o Pad Lifting . . . 156
    • PTH Via Barrel Cracking Fatigue Life Based On IPC TR-579 o Determine applied stress applied (σ) o Determine strain range (∆ε) o Apply calibration constantso Apply calibration constants o Strain distribution factor, Kd(2.5 –5.0) o PTH & Cu quality factor KQ(0 –10) o Iteratively calculate cycles-to-failure (Nf50) 157 15 Effect of 4 PCB Materials on PCB VIA Life & Reliability - ISOLA 410, 415 Nelco N4000-29 & ISOLA 370HR 158 15
    • Elastic Modulus – Used for CTE, Vib. & Shock Analysis y x & Solving for Em Consider Positive value of Em as solution. 159 Effect of Glass Weave Pattern Style on Modulus o Modulus decreases as resin content increases o CTE increases as resin content increaseso CTE increases as resin content increases o Copper content plays a significant role o These values can be now used to predict solder joint fatigue 160
    • Surface Finishes - Post Pb-Free o Multiple Pb-Free Surface Finish Options Now Exists. o No clear winner, no ideal solution). Surface Finishes, Worldwide o Each PCB surface has different advantages and disadvantages that affects fabrication, solderability, testability, reliability, or shelf life. 2003 shelf life. o The 5 most popular Pb-Free Surface Finishes are: o Electroless nickel/immersion gold (ENIG)/ g ( ) o Immersion silver (ImAg) o Immersion tin (ImSn) o Organic solderability preservative (OSP) 2007 o Pb-free HASL. o These finishes (except for Pb-free HASL) have been in use for several years 18% have been in use for several years. o Pre Pb-Free usage was mostly when very thin, or consistently flat finish were required. Ref: J. Beers Gold Circuits 161 Gold Circuits Contents o Background o Quality Issues o Quality Testing o Printed Circuit Board (PCB) Analysis o Printed Circuit Assembly (PCA) Analysis o Discussion o Reliability Testingy g o Solder Joint Reliability Analysis o Tin Whisker Evaluationo Tin Whisker Evaluation 162 162
    • Background o Legislation (RoHS, WEEE, etc.) is the main issue fueling h h f h l f Pb f l ithe current push for the removal of Pb from electronics o The strength, durability, and reliability of solder joints i i f Pb i i ld d fi i h hconsisting of Pb-containing solders and finishes have been well studied…however the same data is not available for newly developed Pb free solders andavailable for newly developed Pb-free solders and finishes 163 163 Background o The switch to “Pb-free” production affects… o Solders and Fluxes o Plating finishes o Processing o High temperatures o Longer times o “Pb-free” testing focuses on… o Board (PCB) Level Quality Evaluations o Assembly (PCA) Level Quality Evaluations o Reliability Analysis 164 164
    • Quality vs. Reliability o Reliability information for Pb-free products is l i l k i h ld hrelatively unknown so testing should start at the very beginning…with Quality Th f d i h bl ho These terms are often used interchangeably, however they are two different concepts entirely Q ff Qo Quality will affect Reliability, but good Quality does not insure good Reliability 165 165 General Quality Issues o Companies competent in SnPb assembly may have i i h Pb f blissues with Pb-free assembly o Pb-free assembly requires its own process parameters d i i i l b f i iand inconsistencies can result by way of its own unique defects f “o Even if an assembly “process” has not switched to Pb- free, most of the components being purchased have, ith ith t k l dwith or without knowledge 166 166
    • General Quality Analysis o Reliability Testing is a “long-term” venture B f i f R li bili h ldo Before testing for Reliability, one should ensure Quality is acceptable Poor Quality will simply add another variable to theo Poor Quality will simply add another variable to the Reliability assessment o There are many ways to assess overall qualityo There are many ways to assess overall quality o One can / should examine actual raw materials (PCB, components, etc.) through completion of final productp , ) g p p (PCB, PCA, end products, etc.) 167 167 General Quality Testing o A test plan for… o Printed Circuit Boards (PCBs) o Why Test? o Recommended Testing o Some Findings… o Printed Circuit Assemblies (PCAs) o Why Test? o Recommended Testing o Some Findings… 168 168
    • A ‘Quality’ Based Test Plan for PCBs o Why Test? – To determine a board’s ability to withstand Pb-free processing o Test Plan… o Visual Examination o Thermal Analysisy o Thermal Stress Analysis o Solderability Testingy g o Peel Strength Testing o Microsection Analysiso Microsection Analysis 169 169 PCB Test Plan o Recommended Testing… Glass Transition Temperature (Tg) and Z axis Thermal Expansion byo Glass Transition Temperature (Tg) and Z-axis Thermal Expansion by Thermomechanical Analysis (TMA) o IPC-TM-650, method 2.4.24 Ti t D l i ti (T )o Time to Delamination (T288) o IPC-TM-650, method o Glass Transition Temperature (Tg) and Cure Factor (Tg) by Differential Scanning Calorimetry (DSC) o IPC-TM-650, method 2.4.25 o As Received & Thermal Stress Analysis @ 300°Cy @ o IPC-TM-650, methods 2.1.1 & 2.6.8 o Solderability Testing o ANSI/IPC-J-STD-003o ANSI/IPC-J-STD-003 o Peel Strength Testing 170 170
    • PCB Test Plan o Additional Evaluation of the samples is completed via Mi i A l iMicrosection Analysis… 171 17 PCB Test Plan o Some findings… o The possible effects of higher temperatures and longer times… 172 172
    • PCB Test Plan Results Summary o A comparison of board characteristics… Test ID Possible Requirement Material A Material B Material C Visual Examination --- No Anomalies No Anomalies No Anomalies Tg > 150C 175C 180C 180C Cure Factor < 5C 2.6C 3.5C 3.6C % CTE < 4% 1.6% 1.9% 2.9% T288 > 10 min > 10 min > 10 min 6.6 min As Rec'd Microsection IPC A 600 No Anomalies No Anomalies No AnomaliesAs Rec d Microsection IPC-A-600 No Anomalies No Anomalies No Anomalies Thermal Stress --- No Anomalies No Anomalies No Anomalies Solderability > 95% coverage 100% 100% 97%y g Peel Strength > 8 lbs/in 8.4 lbs/in 8.6 lbs/in 7.5 lbs/in 173 173 General Discussion o Testing has shown that studies need to be completed d i Pb f ld d fi i hon products using Pb-free solders and finishes o Sn/Pb Products which easily met reliability estimates l b b h Pb f imay no longer be as robust when Pb-free processing and materials have been implemented, i.e. solder joint concerns in respect to brittleness creep elasticity etcconcerns in respect to brittleness, creep, elasticity, etc. 174 174
    • General Discussion o Processing temperatures and times are critical parameters i Pb f d ti whi h ibl iin Pb-free production, which can cause possible issues with… o Board integrityo Board integrity o Intermetallic Growth o Mismatched board and component finishes have beenp found to cause strength issues on Pb-containing products and will be more prevalent with the continued push towards Pb f lPb-free alternatives o Reliability testing for Pb-free products is indeed similar to t t tipast testing 175 175 General Reliability Issues o The reliability of a product, whether Pb-free or not, is i i lcritical o There are decades of data available concerning S /Pb R li biliSn/Pb Reliability o Conclusions concerning Pb-Free Reliability are “generally based on little “hard” data o Why? …The acquisition of data takes time and currently h i h d d h di hnot enough time has passed and not enough studies have been performed 176 176
    • Industry Specification o IPC (www.ipc.org) is the main industry body the produces specification for PCBs. o While specifications exist, they are not very standardized. o Various laminate formulation (especially since RoHS) o Infinite number of layer stack up configurations. o Glass Mats o 4 Grades of Glass fibers (E, S, D & Quartz) o 5 weave styles (Plain Twill Long Shaft Basket & Locking Lenoo 5 weave styles (Plain, Twill, Long Shaft, Basket & Locking Leno o Scores of Mat Weave Patterns 32 x 32 to 70 x 70. o Final PCB Finishes. o HASL, OSP, ImSn, ImAg, ENIG 177 IPC Specifications DesignManuf. 178
    • Key IPC Standards o IPC-1710 M f ’ Q lifi i P filo Manufacturer’s Qualification Profile o IPC-2221/2222 o Standards on Printed Board Designg o IPC-4101 o Specification for Base Materials for Printed Boards IPC SM 840o IPC-SM-840 o Qualification and Performance of Permanent Solder Mask o IPC-6012 o Qualification and Performance for Rigid Printed Boards o IPC-600 A bili f P i d B do Acceptability of Printed Boards o Test Methods (TM-650) 179 PCB Supply Chain Best Practices: Selection and Q lifi ti f C t tQualification of Contract ManufacturersManufacturers 180
    • Executive Summary o PCBs should always be considered critical components or a critical commodity. o Without stringent controls in place for PCB supplier selection, qualification, and management, long term product quality and reliability is simply not achievable. o This section will cover some common best practices and recommendations for selection & management of PCB suppliers. 181 PCB Best Practices: Commodity Team o Existence of a PCB Commodity Team with at least one t ti f h f th f ll irepresentative from each of the following areas: o Design o Manufacturingg o Purchasing o Quality/Reliability Th h ld i i hl b io The team should meet on a minimum monthly basis to discuss new products and technology requirements in the development pipeline.p p p o Pricing, delivery, and quality performance issues with approved PCB suppliers should also be reviewed. Th t i l t k d ith id tif i li do The team is also tasked with identifying new suppliers and creating supplier selection and monitoring criteria. 182
    • PCB Best Practices: Selection Criteria o Established PCB supplier selection criteria in place. The criteria should be unique to your business but some generally usedq y g y criteria are: o Time in business o Revenue o Growth o Employee Turnover o Training Programo Training Program o Certified to the standards you require (IPC, MIL-SPEC, ISO, etc.) o Capable of producing the technology you need as part of their mainstream capabilities (don’t exist in their process “niches” wherep ( p they claim capability but have less than ~ 15% of their volume built there.) o Have quality and problem solving methodologies in place o Have a technology roadmap o Have a continuous improvement program in place 183 PCB Best Practices: Qualification Criteria o Rigorous qualification criteria which includes: o On site visits by someone knowledgeable in PCB fabrication techniques. An onsite visit to the facility which will produce your PCBs is vitalo An onsite visit to the facility which will produce your PCBs is vital. The site visit is your best opportunity to review process controls, quality monitoring and analytical techniques, storage and h dli ti d f t ll t blhandling practices and conformance to generally acceptable manufacturing practices. o It is also the best way to meet and establish relationships with the people responsible for manufacturing your product. o Sample builds of an actual part you will produce which are evaluated by the PCB supplier and that are also independentlyevaluated by the PCB supplier and that are also independently evaluated by you or a representative to the standards that you require. 184
    • PCB Best Practices: Supplier Tiering o Use of supplier tiering (Low, Middle, High ) strategies if you have a diverse product line with products that range from simpler to complexdiverse product line with products that range from simpler to complex. This allows for strategic tailoring to save cost and to maximize supplier quality to your product design. Match supplier qualifications to the complexity of your product. Typical criteria for tiering suppliers include:p y y p yp g pp o Finest line width o Finest conductor spacing, o Smallest drilled hole and via sizeo Smallest drilled hole and via size o Impedance control requirment o Specialty laminate needed (Rogers, flex, mixed) Use of HDI micro vias blind or buried viaso Use of HDI, micro vias, blind or buried vias. o Minimize use of suppliers who have to outsource critical areas of construction. Again, do not exist in the margins of their process capabilitiescapabilities 185 PCB Best Practices: Relationship Mgt. o Relationship Management. Ideally, you choose a strategy that allows you to partner with your PCB suppliers for success. This is especially critical is you have low volumes, low spend, or high technology and reliability requirements for your PCBs. Some goodspe d, o g ec o ogy a d e ab y equ e e s o you C s. So e good practices include: o Monthly conference calls with your PCB commodity team and each PCB supplier. The PCB supplier team should members equivalent to your team members. o QBRs (quarterly business reviews) which review spend, quality, and performance metrics, andQ (q y ) p , q y, p , also include “state of the business updates” which address any known changes like factory expansion, move, or relocation, critical staffing changes, new equipment/capability installation etc. The sharing is done from both sides with you sharing any data which you think would help strengthen the business relationship – business growth, new product and quoting opportunities, etc At least twice per year the QBRs should be joint onsite meetings which alternate betweenetc. At least twice per year, the QBRs should be joint onsite meetings which alternate between your site and the supplier factory site. The factory supplier site QBR visit can double as the annual on site visit and audit that you perform. o Semi-Annual “Lunch and Learns” or technical presentations performed onsite at your facility by your supplier. All suppliers perform education and outreach on their processes and capabilities.y pp pp p p p They can educate your technical community on PCB design for manufacturing, quality, reliability, and low cost factors. They can also educate your technical community on pitfalls, defects, and newly available technology. This is usually performed free of charge to you. They’ll often spring for free lunch for attendees as well in order to encourage attendance. 186
    • PCB Best Practices: Supplier Scorecards o Supplier Scorecards are in place and performed quarterly and yearly on a rolling basis. Typical metrics include: o On Time Delivery o PPM Defect Rates o Communication – speed, accuracy, channels, responsiveness to quotes Quality Excursions / Root Cause Corrective Action Processo Quality Excursions / Root Cause Corrective Action Process Resolution o SCARs (Supplier Corrective Action Requests) Reporting( pp q ) p g o Discussion of any recalls, notifications, scrap events exceeding a certain dollar amount 187 PCB Best Practices: Prototype Development o Prototype Development o In an ideal environment, all of your PCBs for a given product should come from the same factory from start to finish – (f ibili ) l d i ( bili &prototype (feasibility), pre-release production (testability & reliability), to released production (manufacturability). o Each factory move introduces an element of risk since the producto Each factory move introduces an element of risk since the product must go through setup and optimization specific to the factory and equipment contained there. While this is not always possible for fprototypes, all PCBs intended for quality and reliability testing should come from the actual PCB production facility. 188
    • PCB Best Practices: Cont. Quality Monitoring o Continuous Quality Monitoring is in place. Consider i i d i i th f ll irequiring and reviewing the following: o Top 3 PCB factory defects monitoring and reporting o Process control and improvement plans for the top 3 defectsp p p o Yield and scrap reporting for your products o Feedback on issues facing the industry R li bilit t ti f d (HATS IST ld fl t t )o Reliability testing performed (HATS, IST, solder float, etc.) o As a starting point, review the IPC-9151B, Printed Board Process Capability, Quality, and Relative Reliability (PCQR2) Benchmark Test Standard and Database at: http://www ipc org/html/IPC 9151B pdfStandard and Database at: http://www.ipc.org/html/IPC-9151B.pdf o Your PCB suppliers may be part of this activity already. Ask if they participate and if you can get a copy of their results. IST – Interconnect Stress Test HATS Highly Accelerated Thermal Shock 189 HATS – Highly Accelerated Thermal Shock Comprehensive ProductComprehensive Product Qualification Plan Development Cheryl Tulkoff, ASQ CRE ctulkoff@dfrsolutions.com 190
    • Test Plan Development o Introduction to Test Plan Development o Testing Examplesg p o Introduction to Physics of Failure Methodology for Test Plan Developmentp o Examples & Case Studies o Initial Reliability Assessment and Virtual Qualificationo Initial Reliability Assessment and Virtual Qualification Options 191 Test Plan Development o Product test plans are critical to the success of a new product or technology o Stressful enough to identify defects Show correlation to a realistic environmento Show correlation to a realistic environment o Recommended approach o Industry Standards + Physics of Failure Failure Analysis / o Results in an optimized test plan that is acceptable to management and customers o Experience in product test plans include ALT Plan Approval Start Manufacture Qualification and RGT Units Pass Qual? N Y Perform Qual Failure Analysis / Repairs Order SRT UnitsPerform RGTPerform SRT Update SRT Units? N Y Update RGT units? Y N o Industrial controls o Process monitoring o Consumer appliances o Telecom (Class I, II, and III environments) Perform Updates on SRT Units Perform Updates on RGT Units Limited Re- qualification? N Order Limited Re Y o Personal computers o Mobile phones and other mobile products o Avionics (engine controls, fuselage) o Automotive (under-hood, passenger Finish Submit Final Report Order Limited Re- qual units and Perform Limited Re-qualification Pass Limited Re-qual? Failure Analysis / Repairs ALT Objective Met? N Y Y Request Guidance from GD N o Automotive (under hood, passenger compartment, chassis, and trunk) o Down-hole oil-drilling Month Cycles/Year Ramp Dwell Max Temp (ºC) Min Temp (ºC) T Cycles per Day AF Jan+Feb+Dec 90 6 hrs 6 hrs 30 5 25 1 12.654 Mar+Nov 60 6 hrs 6 hrs 35 10 25 1 11.799 Apr+Oct 60 6 hrs 6 hrs 40 15 25 1 10.944 May+Sep 60 6 hrs 6 hrs 45 20 25 1 10.26 192 Jun+Jul+Aug 90 6 hrs 6 hrs 50 25 25 1 9.576 Operational 16.6 5 min 3 hrs 25 -40 65 1 2.223
    • Testing Example: Next Generation Microprocessor o Package qualification testing o Reviewed coupon designed, identified deficiencies T f do Tests performed o Nine point cyclic bend o Static bendo Static bend o Drop o Mechanical shock o Harmonic vibration o Random vibration o Thermal cycling o Temperature / humidity 193 Testing Example: Intelligent Gas Meter o Customer transitioning into new product space, concerned about long-term performanceperformance o Reviewed potential use environment o Identified potential drivers for failure Start N Failure Analysis / Repairs (temperature, humidity, salt spray, sulfur gas, etc.) o Started with industry standards and best practices o Modified based on understanding of Physics of Failure D l d d l bl ALT Plan Approval Manufacture Qualification and RGT Units Pass Qual? Y Perform Qual Order SRT UnitsPerform RGTPerform SRT Perform Updates on SRT Units Update SRT Units? N Y Update RGT units? Perform Updates on RGT Units Y N o Developed optimized test plan acceptable to management and customers o Other examples of test plan development Finish Submit Final Report Limited Re- qualification? N Order Limited Re- qual units and Perform Limited Re-qualification Pass Limited Re-qual? ALT Objective Met? Y N Y Y N o Consumer appliances o Telecom o Avionics (engine controls) T k d hi l Month Cycles/Year Ramp Dwell Max Temp (ºC) Min Temp (ºC) T Cycles per Day AF Failure Analysis / Repairs N Request Guidance from GD N o Tracked vehicle o Automotive o Down-hole oil-drilling ( C) ( C) Jan+Feb+Dec 90 6 hrs 6 hrs 30 5 25 1 12.654 Mar+Nov 60 6 hrs 6 hrs 35 10 25 1 11.799 Apr+Oct 60 6 hrs 6 hrs 40 15 25 1 10.944 May+Sep 60 6 hrs 6 hrs 45 20 25 1 10.26 Jun+Jul+Aug 90 6 hrs 6 hrs 50 25 25 1 9.576 Operational 16.6 5 min 3 hrs 25 -40 65 1 2.223 194
    • Test Plan Development - Use Environment o The critical first step is a good understanding of the shipping and use environment for the productand use environment for the product. o Do you really understand the customer and how they use your product (even the corner cases)?product (even the corner cases)? o How well is the product protected during shipping (truck, ship, plane, parachute, storage, etc.)?p , p , g , ) o Temp/humidity, thermal cycling, ambient temp/operating temp. o Salt, sulfur, dust, fluids, etc.S , , , , o Mechanical cycles (lid cycling, connector cycling, torsion, etc.) o Do you have data or are you guessing?o Do you have data or are you guessing? 195 19 Identify Use Environment o Approach 1: Use of industry/military specifications o MIL-STD-810, o MIL-HDBK-310, o SAE J1211, o IPC-SM-785, o Telcordia GR3108, o IEC 60721-3, etc. o Advantages N dditi l t! MIL HDBK310 o No additional cost! o Sometimes very comprehensive o Agreement throughout the industry o Missing information? Consider standards fromo Missing information? Consider standards from other industries o Disadvantages o Most more than 20 years old o Always less or greater than actual (by how much, unknown) IPC SM785 196 IPC SM785
    • Use Environment (cont.) o Approach 2: Based on actual measurements of similar products in similar environments o Determine average and realistic worst-case f fo Identify all failure-inducing loads o Include all environments M f t io Manufacturing o Transportation Storageo Storage o Field 197 Identify Failure Inducing Loads • Temperature Cycling – Tmax, Tmin, dwell, ramp times • Sustained Temperaturep – T and exposure time • Humidity – Controlled, condensation • CorrosionCorrosion – Salt, corrosive gases (Cl2, etc.) • Power cycling – Duty cycles, power dissipation El t i l L d• Electrical Loads – Voltage, current, current density – Static and transient • Electrical Noise • Mechanical Bending (Static and Cyclic) – Board-level strain • Random Vibration – PSD, exposure time, kurtosisPSD, exposure time, kurtosis • Harmonic Vibration – G and frequency • Mechanical shock G wave form # of events 198 – G, wave form, # of events
    • Identify Use Environment (Best Practice) o Use standards when… o Certain aspects of your environment are common o No access to use environment o Measure when… o Certain aspects of your environment are uniqueo Certain aspects of your environment are unique o Strong relationship with customer o Do not mistake test specifications for the actual useo Do not mistake test specifications for the actual use environment o Common mistake with vibration loadso Common mistake with vibration loads 199 Identify Electrical Environments o Often very well defined in developed countries o Introduction into developing countries can sometimes cause surprises o Rules of thumb o China: Can have issues with grounding (connected to rebar?)o China: Can have issues with grounding (connected to rebar?) o India: Numerous brownouts (several a day) o Mexico: Voltage surgeso Mexico: Voltage surges 200
    • Identify Temperature: Worst-Case (Ambient) Temperature Avg. U.S. Avg. U.S. Weighted by Registration Phoenix U.S. Worst CaseTemperature CLIM Data Weighted by Registration (Source: Confidential) (hrs/yr) Worst Case (hrs/yr) 95F (35C) 0.375% 0.650% 11% (948) 13% (1,140) 105F (40.46C) 0.087% 0.050% 2.3% (198) 3.8% (331) 115F (46.11C) 0.008% 0.001% 0.02% (1.4) 0.1% (9) 201 Temperature: Closed Containers Container and Ambient Temperature 75.0 65.0 Container Temp (°C) Outdoor Temp (°C) Temp. Variation 45 0 55.0 ture(°C) Trucking Container 35.0 45.0 Temperat Container 25.0 15.0 0 50 100 150 200 250 300 350 400 450 Hours 202
    • Temperature: Long-Term Exposure o For electronics used outside with minimal power dissipation, the diurnal (daily) temperature cycle provides the primary degradation-inducing loadload Phoenix AZ Month Cycles/Year Ramp Dwell Max. Temp (o C) Min. Temp. (o C) J +F b +D 90 6 h 6 h 20 5 Phoenix, AZ Jan.+Feb.+Dec. 90 6 hrs 6 hrs 20 5 March+November 60 6 hrs 6 hrs 25 10 April+October 60 6 hrs 6 hrs 30 15 May+September 60 6 hrs 6 hrs 35 20 June+July+August 90 6 hrs 6 hrs 40 25 203 Humidity / Moisture (Rules of Thumb) o Non-condensing o Standard during operation, even in outdoor applications o Due to power dissipation C do Condensing o Can occur in sleep mode or non-powered Driven by mounting configuration (attached to something at lowero Driven by mounting configuration (attached to something at lower temperature?) o Driven by rapid change in environment o Can lead to standing water if condensation on housing o Standing water o Indirect spray, dripping water, submersion, etc. o Often driven by packaging 204
    • Toyota Approach  Toyota's development engineers are 4X as productive as U S counterparts4X as productive as U.S. counterparts.  Why?  Focus on learning as much as possible o Western engineers o Toyota engineers  Use of that knowledge to develop a stream of excellent products g o Define several product concepts o Select the one that has the most promise D f d d d y g o Efforts concentrated at lowest possible design level o Thorough understanding of the technology of a subsystem so it cano Draw up specifications and divide them into subsystems; o Subsystems are designed, built and rolled up for system testing. technology of a subsystem so it can be used appropriately in future designs o Failures? Rework the specs and the designs accordingly (non-optimized and confusing endeavor) 205 Toyota Example: Radiators o Traditional approach: Design radiator for a specific vehicle based on h i l ifi ti itt f th t hi lmechanical specifications written for that vehicle o Toyota considers a range of radiator solutions based on cooling capacities and the cooling demands of various engines that might becapacities and the cooling demands of various engines that might be used. o How the radiator actually fits into a vehicle would be kept loose so that T t ' k l d f di t t h l ld b d t t thToyota's knowledge of radiator technology could be used to create the optimum design o Toyota's system is "test & design" rather than the traditional "design &o Toyota s system is test & design rather than the traditional design & test." o Toyota engineers test at the fundamental knowledge level so they don't have to test at the later more expensive stages of design and prototypinghave to test at the later, more expensive stages of design and prototyping 206
    • Sorting Out Testing Methods, Brands and Different Approaches MEOST Mixed Environment & Operating Stress Test) STRIFE (Stress + Life) HALT (Highly Accelerated Life Test) ( ) CERT Combined Environment Reliability Test) Shainin’s - Step Stress Probe PoF-ALT (Physics of Failure based Accelerated Life Test) PRD Product Ruggedization Development) Dust test Corrosion Testing MFG, nitric acid test HASS Highly Accelerated Stress Screen) HAST (Highly Accelerated Stress Test) Entella’s - FMVT (Failure Mode Verification Test) Salt Spray 207 20 General Test Plan Development Outline – PCBA Example o Component qualification (with end product in mind) o Thermal cycling, high temp, temperature & humidity, etc.o Thermal cycling, high temp, temperature & humidity, etc. o PCBA qualification o Thermal cycling o HALT/HAST (Highly Accelerated Life or Stress Testing) o Drop/shock o Heat age o System level qualification Shock and Vibrationo Shock and Vibration o Dust testing o Torsion o Etc. C C 208 20 PCBA = Printed Circuit Board Assembly
    • Component Approval & Qualification Procedure Th t i t Potential suppliers and part # of needed component is identified The component requirements are determined needed component is identified CE evaluates electrical capabilities of component Improvements made and d t b itt d No data resubmitted Do critical electrical parameters meet specifications? Includes: Yes Does component meet reliability requirements No Root cause found, improvements made and retested Yes • Surface finish requirements • Whisker testing • Reliability testing Component approved for system testing Yes Does component No Root cause found, • Reliability testing • MSL & heat resist Component is approved and b t f AVL f th t t Does component meet system level reliability No improvements made and retested Yes 209 becomes part of AVL for that system Supplier auditing PCBA Qualification o Develop a comprehensive test plan o Assemble boards at optimum conditions o Rework specified components on some boardsp p o Visually inspect and electrically test o C-SAM & X-ray inspect critical components on 5 oro C SAM & X ray inspect critical components on 5 or more boards (+3 reworked for BGAs) o Use these boards for further reliability testing (TC,o Use these boards for further reliability testing (TC, HALT, S&V) o Perform failure analysiso Perform failure analysis o Compile results and review 210
    • Assemble at Optimum Conditions 66 pcs Example of a PCBA Test Plan Visual Inspection 66 pcs Electrical Continuity Test (DC devices) Send to Intel 10 pcs (Notebooks) Use for Rework Section*( ) 66 pcs 10 pcs X-Section Analysis (Devices ?) 2 pcs 2 4 4 4 4 12 10 Section 25 pcs 25 1 Non-Op + Cont (S & V) 4 pcs Square Wave (S & V) 4 pcs HALT (Duration ?) 4 pcs Thermal + Non-Op +Cont (S & V) 4 pcs2 2 22 X-Section Analysis (Devices ?) 1 pcs X-Section Analysis (Devices ?) 1 pcs 1 1 X-Section Analysis (Devices ?) 1 pcs 1 Dye / Pry Analysis 1 1 1 Dye / Pry Analysis D / P A l i p X-Section Analysis (Devices ?) 1 pcs 1 D / P A l i 1 Thermal Cycle Test (0/100C) Dye / Pry Analysis (Devices ?) 1 pcs Dye / Pry Analysis (Devices ?) 1 pcs Dye / Pry Analysis (Devices ?) 1 pcs Dye / Pry Analysis (Devices ?) 1 pcs Thermal Cycle Test (0/100C) 12 pcs X-Section Analysis (Devices ?) 1 pcs 14 7 NOTES: * - Rework should follow the supplier’s standard process for removing and replacing components Number in lower right corner of box represents Remaining quantity from that test element. 211 211 1 pcs Dye / Pry Analysis (Devices ?) 4 pcs g q y Vibration Durability: Two Types of Circuit Board Issues o Board in Resonance o Components. Shaken Off/Fatigued by Board Motion o Components In Resonance. o Components Shake/Fatigue themselves apart or off the Board. ll ll C lby Board Motion. o By Flexing Attachment Features o Especially Large, Tall Cantilever Devices 3 Med. Sized Alum CAPS 1 Small Long Leaded Snsr 1 Hall Effect Sensor. 1 Large Coil Assembly Lead Motion - Flexed Down Normal Bending Lead Wires Stressed g y PC Board - Normal - Flexed up Stressed Solder Joint Displacement Gull Wing I.C. PC Boardp  Time to Failure Determine by Intensity/Frequency of Stress VersesIntensity/Frequency of Stress Verses Strength of Material Log (Peak Strain) Solder Fatigue Life Log (Number of Cycles to Failure) 212 21
    • Failure Mechanism Hierarchy (Non Manufacturing Issues) Relative to the N-S CurveRelative to the N-S Curve Cyclic Creep Fatigue Region Plastic Dominated Fatigue Region Plastic Fracture or Shear Region Useful Acceleration Range High Elastic Region Cyclic Creep Fatigue Region Note: With this Knowledge the Foolish Failure Factors such as Temp., Stress Application Rate, & Material Properties can shift the range of Region Could be viewed as Number of mechanism region . Low Stress ~ “Near I fi it ” Lif as regions with Non-Field Relevant Failure of Cycles Infinite” Life Region Relevant Failure Mechanisms Low Low Stress High 213 21 Thermal Cycle Testing o From IPC-SM-785 - Guidelines for Accelerated Reliability Testing & Solder Joint Reliability (SJR) Theory & Application - John Lau. o Thermal Cycling Key Parameters: o Thermo-mechanical expansion/contraction is the force that drives material damage accumulation stress agingmaterial damage accumulation stress aging. o Primary Aging Factors are: High End Temp., High to Low Temp. Difference & # of Cycles. Correlation to Number of Cycles Not the Time DurationCorrelation to Number of Cycles,Not the Time Duration o Secondary Aging Factors are: Hot Dwell Time & Change Rate. o Limit Factors (to Avoid Foolish Failures) are: High End Temp., Change Rate & Min. Hot Dwell Time. Note: PROFILES MUST BE BASED ON Temperatures as are measuredNote: PROFILES MUST BE BASED ON Temperatures as are measured at the components on the PCB (Not Chamber Settings) and must include Self heating and Thermal Lag Effects 214 21
    • Thermal Cycling o From IPC-SM-785 - Guidelines for Accelerated Reliability Testing & Solder Joint Reliability (SJR) Theory & Application - John Lau. o Thermal Cycling Continued: o Max Temp. MUST NOT EXCEED: o The (Tg - Glass Transition Temp.) of the substrate. Material properties dramatically change( g p ) p p y g above the Tg invalidation the tests. (Tg for FR4 PCB 125-135’C). o The Lowest Re-Crystalization Temperature of the Plastics used in the Device. Temp Dwell Time (MEASURED on the PCB/COMPONENTS IS VERY IMPORTANTo Temp. Dwell Time (MEASURED on the PCB/COMPONENTS IS VERY IMPORTANT. o Hot Dwell is more important than Cold Dwell - needed to realize creep damage. o Hot Dwell under a TENSILE LOAD causes faster attachment aging rates then Compressive Load. o For FR4 PCB Tensile Loading occurs at Hot Temperatures.) o Practical Min. Temp. - Cooling Parts below 50% of the Absolute Temp. melting point of a metal is not value added (wasted time and expensive cooling energy o Because Metal becomes a structures (do not creep) < 50% absolute (K) Melting temperature( p) % ( ) g p o Eutectic Solder Melts at 183ºC +> 456ºK, o 50% = 228ºK => - 44ºC 215 21 Change Control – When to Requalify o Inadequate change control is responsible for many (some would say most) field failures.y ) o Examples would include o Burning Li notebook batteries o Electrolytic capacitor leakage o Recent flip chip underfill problems C i ll b tt t t f ilo Coin cell battery contact failure o Heat sink clogging failure o DDR2 Memory moduleso DDR2 Memory modules o ImAg corrosion o All changes need to be evaluated carefully (testing to failure recommended). 216 21
    • HALT (Highly Accelerated Life Testing) o A typical HALT test exposes the product to simultaneous vibration and thermal cycling. The product is tested in the operationaly g p p mode while the vibration stress is increased with each thermal cycle. The objective of the test is to cause failure of the product thuso The objective of the test is to cause failure of the product thus identifying the weakest link which can be then be improved. The test duration is typically less than a week. On its own, this test is bl d h l f f d ( l fnot able to predict the life of a product (acceleration factor is not known). However, it is very useful when a product can be compared side-by-side with a previous generation of product with known reliability. 217 HALT Testing o HALT was able to quickly identify the primary failure mechanisms that we found with LF products. o These included PCB pad cratering, trace fracture, inner plane separation, and poorly formed solder joints. These are all failure mechanisms that would likely occur in the earlier stages of a products life if not correctedof a products life if not corrected. o Failure mechanisms that HALT did not find were long term thermal fatigue issues such as barrel cracking in vias or highthermal fatigue issues such as barrel cracking in vias or high cycle solder joint fatigue failures of resistors and/or capacitors (thermal cycling required for these). 218
    • HALT Procedure o Note that functional testing is performed while the vibration is taking place. This is important since intermittent opens can be found at this condition. o Vibration should start at 0 Grms and step up by 5 Grms each cycle until failure is detected. Failing units should be removed as the chamber is cycling past room temperature. Failing units shall be analyzed carefully tocycling past room temperature. Failing units shall be analyzed carefully to find root cause failure. 219 Virtual Qualification (VQ) o This assessment uses physics-of-failure-based d d ti d l t di t ti t f ildegradation models to predict time-to-failure o Models include Interconnect fatigue (solder joint and plated through hole)o Interconnect fatigue (solder joint and plated-through hole) o Capacitor failure (electrolytic and ceramic) o Integrated circuit wearoutg o Customers develop a degree of assurance that their product will survive for the desired lifetime in the expected use environment 220
    • On-Going Reliability Testing (ORT) o Qualification shows that a limited number of early manufactured products (maybe even from a pilot line) are reliable. o It’s often not possible to create every permutation of component suppliers in the qual builds. o How do you know the product will remain reliable as you go to high volume and new component suppliers are introduced? o There is no perfect answer but an ORT program can help. 221 22 Summary o Product test plans are critical to the success of a new product or technology o Stressful enough to identify defectso Stressful enough to identify defects o Show correlation to a realistic environment o PoF Knowledge can be used to develop test plans and profiles that can be correlated to the field. o Vibration fatigue is easy, as is vibration endurance by design. True accelerated wear out thermal cycling is also possibleo True accelerated wear out thermal cycling is also possible o True ALT with combined temperature & vibration is still challenging. o Change control processes and testing should not be overlooked (reliability engineerg p g ( y g needs to stay involved in sustaining). o On-going reliability testing can be a useful (but admittedly imperfect) tool. 222 22
    • Contact Information o Questions: o Contact Cheryl Tulkoff, ctulkoff@dfrsolutions.com, 512-913-8624 o askdfr@dfrsolutions.com o www.dfrsolutions.com 223