Double Patterning

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  • the 820 million transistors of an Intel Core 2 Extreme chip can process nearly 72 billion instructions per second
  • Double Patterning

    1. 1. Double Patterning Wai-Shing Luk
    2. 2. Background <ul><li>At the past, chips were continuously getting smaller and smaller, and hence less power consumption. </li></ul><ul><li>However, we’re fast approaching the end of the road where optical lithography( 光刻 ) cannot take us where we need to go next. </li></ul>
    3. 3. 光刻过程 <ul><li>Photo-resist coating </li></ul><ul><li>Illumination </li></ul><ul><li>Exposure </li></ul><ul><li>Etching </li></ul><ul><li>Impurities Doping </li></ul><ul><li>Metal connection </li></ul>
    4. 4. Sub-wavelength Lithograph <ul><li>Feature size << lithograph wavelength </li></ul><ul><ul><li>45nm vs. 193nm </li></ul></ul><ul><li>What you see in the mask/layout is not what you get in the chip: </li></ul><ul><ul><li>图形失真 </li></ul></ul><ul><ul><li>成品率下降 </li></ul></ul>
    5. 5. What is Double Patterning? <ul><li>Instead of exposing the photo-resist layer once under one mask, as in conventional optical lithography, expose it twice, by splitting the mask into two, each with features half as dense. </li></ul>
    6. 6. TBUF_X16, Layer 9 <ul><li>Blue line indicates the conflict that can’t be resolved. </li></ul>
    7. 7. TBUF_X16, Layer 11
    8. 8. SDFFRS_X2 Layer 9, 11
    9. 9. Random, 4K rectangles
    10. 10. fft_all.gds, 320K polygons
    11. 11. Current Status of Our SW <ul><li>fft_all: 320K polygons, 1.3M rectangles </li></ul><ul><ul><li>Conflict graph construction within 1 minute </li></ul></ul><ul><ul><li>Color assignment within 9 minutes </li></ul></ul><ul><ul><li>Compare: 26 minutes for just displaying the result using “eog” </li></ul></ul><ul><ul><li>Note: Only g++ 3.4.5 was used, no advanced compiler optimization has been done yet. </li></ul></ul>
    12. 12. Key Techniques <ul><li>Novel polygon cutting algorithm to reduce the number of rectangles and the total cut-length. </li></ul><ul><li>Novel dynamic priority search tree for plane-sweeping. </li></ul><ul><li>Decompose the underlying conflict graph into its tri-connected components using SPQR-tree </li></ul><ul><li>Graph-theoretical approach instead of ILP </li></ul><ul><ul><li>Recast the coloring problem as a T-join problem and is then by solved by Hadlock’s algorithm </li></ul></ul>
    13. 13. New Polygon Cutting Algorithm <ul><li>Allow minimal overlapping to reduce the number of rectangles, and hence to reduce the number of conflicts. </li></ul><ul><li>Limited support of diagonal line segments </li></ul>
    14. 14. Dynamic Priority Search Tree <ul><li>In plane sweeping, events are frequently “inserted” and “deleted” to the scan line. </li></ul><ul><li>In our PST, all data are stored at the leaf nodes of PST, making “insert” and “delete” operations very fast (O(1) time for each tree rotation). The payoff is that the “query” operation will be little slower than the traditional PST. </li></ul>
    15. 15. Splitting and Stitching <ul><li>Additional rectangle splits for resolving conflicts </li></ul>
    16. 16. Conflict Detection <ul><li>Two rectangles are NOT conflict if their distance is > b. </li></ul><ul><li>Conflict: (A,C), (A,E), (E,B), (B,D), but not (A,B), (A,D) (B,C)! </li></ul><ul><li>Define: a polygon is said to be rectilinearly convex if it is both x-monotone and y-monotone. </li></ul><ul><li>Rule: </li></ul><ul><ul><li>(A,D) are not conflict because A-F-D reconstructs a rectilinearly convex polygon. </li></ul></ul><ul><ul><li>(A,C) are conflict because A-F-C reconstructs a rectilinearly concave polygon </li></ul></ul>A B C D E F b
    17. 17. Layout Splitting Problem Formulation <ul><li>INSTANCE: Graph G = ( V , E ) and a weight function w : E  N </li></ul><ul><li>SOLUTION: Disjoint vertex subsets V 0 and V 1 where V = V 0 ∪ V 1 </li></ul><ul><li>MINIMIZE: the total cost of edges whose end vertices in same color. </li></ul><ul><li>Note: the problem is linear-time solvable for bipartite graphs, polynomial-time solvable for planar graphs, but NP-hard in general. </li></ul><ul><li>To reduce the problem size, graph partitioning techniques could be used. </li></ul>
    18. 18. Bi-connected Graph <ul><li>A vertex is called a cut-vertex of G if removing it will disconnect G. </li></ul><ul><li>If no cut-vertex can be found in G , then the graph is called a bi-connected graph. </li></ul><ul><li>For example, a and b below are cut-vertices. </li></ul>
    19. 19. Bi-connected Components <ul><li>A connected graph can be decomposed into its bi-connected components in linear-time. </li></ul><ul><li>Each bi-connected component can be solved independently without affecting the final sol’n. </li></ul><ul><li>Question: Is it possible to further decompose the graph? </li></ul>
    20. 20. Tri-connected Graph <ul><li>A pair of vertices is called a separation pair of a bi-connected graph G if removing it will disconnect G. </li></ul><ul><li>If no separation pair can be found in G , then the graph is called a tri-connected graph. </li></ul><ul><li>Eg. {c,d}, {d,e}, {e,f}, {g,h} are separation pairs. </li></ul>
    21. 21. Tri-connected Components <ul><li>A bi-connected graph can be decomposed into its tri-connected components in linear-time using a data structure named SPQR-tree </li></ul>
    22. 22. SPQR-Tree virtual edge skeleton
    23. 24. Divide-and-Conquer Method <ul><li>Three basic steps: </li></ul><ul><ul><li>Divide a graph into its tri-connected components. </li></ul></ul><ul><ul><li>Solve each tri-connected components in a bottom-up fashion. </li></ul></ul><ul><ul><li>Merge the solutions into a complete one in a top-down fashion. </li></ul></ul><ul><ul><li>We calculate two possible solutions for each components, namely { s , t } in same color and { s , t } in opposite colors. </li></ul></ul>
    24. 25. Example
    25. 26. More Technical Details <ul><li>In Hadlock’s algorithm, voronoi graph instead of complete graph is used. </li></ul><ul><li>A brute-force method is used for solving the maximum weighted planar subgraph problem (could be improved) </li></ul>
    26. 27. Conclusions <ul><li>Experiment results show that our method can achieve 3-10X speedup </li></ul><ul><li>We believe that it is a key to the success of 22nm process </li></ul><ul><li>Unfortunately we didn’t have chance to try a realistic 32/22nm layout yet </li></ul><ul><li>because nearly everything is confidential under 90nm </li></ul><ul><li>Foundries may move to EUV if DPL fails. </li></ul>

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