OKAN UNIVERSITYELECTRICAL AND ELECTRONICS ENGINEERING DEPARTMENT EEE467 - Advanced Digital Design Show sound signals on VGA with using PMOD MIC AHMET İLKER ŞİN 070203012
Outlines1 ) Project objective 7) Explain of code2) Analogue to Digital Converting 8) VGA3) Microphone SelectionDynamic microphonesCondenser microphonesElectret condenser microphone4) PMOD MICMicrophone ModulePre- amplifierCompandorPMOD MIC Block5) Functional Description TIMING FSM6) Design Procedures (Block Diagrams)
Project objectiveThe main objective of this project is to display an Audio signals on VGA screen. The initial objective of this project is to compare and evaluate the FPGA prototyping boards readily available in the market and a selection is to be made. The aim of this project will be to capture the sound from an audio signals via PMOD MIC and display the signal to reading on a VGA screen
Analogue to Digital ConvertingThe audio signal from ADCs have resolution which is themicrophone will be of number of the discreet values that itanalogue format. Therefore, a can produces over a range of analogueconversion to a digital format values. For example, For a Full scaleis needed as the FPGA is a measurement range of 0 to 10 volts, ifdigital electronic chip. the ADC resolution is 12 bits (212 =Therefore an Analogue to 4096 quantization levels (codes)), theDigital Converter (ADC) ADC voltage resolution will be (10V -component is needed. This 0V) / 4095 steps = 10V / 4095 stepscomponent will convert a 0.00244 V/step 2.44 mV/stepcontinuous signal to discreetdigital numbers.
Microphone Selection There are three different types of microphones availableDynamic microphones: An ideal one for general purposewith simple design with few moving parts and is sturdyand resilient to rough handling. This type of microphonesare more likely suitable for handling high volume (e.g.from musical instruments or amplifiers). They have nointernal amplifier and do not require batteries or externalpower.
Microphone SelectionCondenser microphones: This type of Microphonesrequires power from a battery or external source (called"phantom power"). The audio signal out from themicrophone is stronger signal than that from a dynamic.They are also more sensitive and responsive than dynamics,making them well-suited to capturing subtle nuances in asound. However, they are not ideal for capturing highvolume as the high level of sensitivity makes them prone todistortion. A condenser simply means capacitor, whereenergy is stored in the form of an electrostatic field. Thistype of microphone, which uses a capacitor to convertacoustical energy into electrical energy.
Microphone SelectionElectret condenser microphone: This microphoneuses a special type of capacitor which has apermanent voltage built in during manufacture. Like apermanent magnet, in that it doesnt require anyexternal power for operation. Therefore a powersource (e.g. a battery or “phantom Power” is notrequired. The other feature is the same as a normalcondenser microphone The selection of the suitable microphone depends on the Sensitivity and Frequency range criteria
Microphone SelectionSensitivity: This determines how much voltage isgenerated per units sound pressure level (mV/Pa). Amore sensitive microphone of 50 or 100Mv/Panormally large) is required if there’s a need tocharacterize lower level sounds. For louder soundlike jet aircraft, a less sensitive microphone issufficientFrequency range: the audible range is 20 to20 kHz and many microphonesextend well beyond this.
PMOD MICKnowing and going through all those above selection criteria,the decision to choose the suitable microphone was madesimple by DIGILENT as there is a preinstalled microphone aperipheral board for FPGA prototyping boards comes with avery low cost This I/O interface board called PMOD MIC hasbeen specifically designed for use with DIGILENT and XILINXdevelopment kits which will work on an SPI interface via 6accessories header pins I/O peripheral ports
PMOD MICThis board consists of an analogue microphone, anSA575DTB IC which is a compandor chip and ADCS7476 chipwhich is an Analogue to Digital Converter (ADC). TheCompandor IC is connected as an Automatic LevelConfiguration (act as a pre-amplifier) and the ADC convertsthe analogue volts into 12bit digital code
Pre- amplifierIn order to amplify alow level audio signalsuch as pickup,microphone, turntable,into line level signals, apre-amplifier (or pre-amp) is needed. Thiscomponent provides avoltage gain but notsignificant current gain
CompandorCompanding is aprocess in signalprocessing thatmitigates thedetrimental effects ofa channel with limiteddynamic range.There’s an electroniccomponent that canper form this processcalled a compandor The Differences of an analogue signal before and after companding
PMOD MIC BlockThe block diagram of PMODmicrophone can be illustrated as inFigure PMOD MIC Block diagramtakes in analog sound throughmicrophone and outputs a digitalsound signal
PMOD MIC BlockThis block will need to be programmed to accept the analogaudio signal from the microphone to go through the pre-ampand finally to convert the Analog signal into a 12 bit digitaldata signal. The PMOD MIC board needs to be powered witha supply voltage of minimum 2.7 V to maximum 5.25V. Fromthe J1 and J18 peripheral board a 3.3V and GND is prerouted and ready for use without programming. For the ADC,there’s a need to input a 12.5MHz (max. 20MHz) to clockinput. This is where the 50 MHz clock supply on FPGA boardswill be divided and supply back to the input. Next is thechips select signal (low) which will inform the ADC toperform conversion once there’s logic 0. Those are thephysical Input/ output (I/O) connection required
PMOD MIC BlockADC Connection Diagram (left) and Block Diagram (right).
PMOD MIC BlockThe function of this block is not changedfrom previous revision. The connectiondiagram from PMOD MIC board to FPGAare shown in Figure below PMOD MIC board FPGA BOARD B2 A3 MISO SCK
PMOD MIC Block In this block, the FPGA needs to be programmed to take in the digital ADC codes and perform some averaging in order to determine the average voltage level over the continuous signal . In the case of a set of n values , the RMS value is given by VRMS Calculation
Functional DescriptionThe input ports are a 50MHz clock, anasynchronous reset button, and thedata from the ADCS7476 that isserially shifted-in on each clock cycle(SDATA). The outputs are the SCLKsignal, which clocks the PmodMIC at12.5MHz; a chip select signal (nCS),which enables the ADCS7476 chip onthe PmodMIC; and as the 12-bitoutput vector (labeled DATA) from theADCS7476 chip, which can be used byany external component. The STARTsignal is used to tell the componentwhen to start a conversion. After aconversion is done, the componentactivates the DONE signal. A blockdiagram of the component is shown inFigure
TIMINGThe timing diagram in Figure is used to determinethe correct timing sequence for the finite statemachine that clocks the PmodMIC. It is the timingsequence that is used to generate 16 bits of datausing the ADCS7476 chip inside the PmodMIC. Thesignal nCS must be at a low or zero state while thedata is generated on the falling edge of the clocksignal. Immediately following the data transfer, thesignal nCS must be driven high to signal when a newset of data can be generated
TIMINGTiming Diagram of the ADCS7476 Chip on the PmodMIC
FSMThe logic that created the timing sequenceto take in the data input SDATA seriallyand latch in the 16-bit vector, as well asclock the nCS and SCLK outputs, wasdesigned by creating the finite statemachine shown in FigureThere are three states: Idle, ShiftIn, andSyncData. During the Idle state, the DONEoutput signal needs to be high in order toallow a conversion. When the START signal isgoing high, the state machine goes into theShiftIn state.In the ShiftIn state, the DONE signal goeslow and the data from the PmodMIC isserially shifted-in from MSB to LSB for 16clock cycles to ensure that all 16 bits of datahave been received from each chip. Aftershifting is done, the state machine goes into FSM of the PmodMIC Referencethe SyncData state. Component
FSMIn the SyncData state, the effectivedata received from the PmodMIC isplaced on the 12-bit output portDATAIn the SyncData state, theeffective data received from thePmodMIC is placed on the 12-bitoutput port DATAIf the START input signal is low themachine goes back to the Idle state,ready to accept another conversionNo mater what the current state is,the RST input signal resets the statemachine and puts it into the Idle state
Design Procedures (Block Diagrams)The FPGA needs to be programmed inorder to produce the outputcorresponding to the analogue inputlevel from a microphone During theresearch period, the block diagram ofan Sound Meter using FPGA wasproposed. The diagram shows somefundamental concepts in differentblocks below in Figure
PMOD MIC Analog I/O Interface Mıcrophone Preamp VGA O UTPUT Fılter ADC(12 bit) Preamp FPGA Chip FılterClock Converter( 50 to 12.5 MHZ) Counter 4- bit Amplifiers Analogue to Dıgıtal FSM Converter
Design Procedures (Block Diagrams)Keeping in mind that the different in the FPGA chip, theappropriate HDL codes planned to be written to design theFPGA chip to generate the output correctly. As most of thedesigns using FPGA done we using VGA screen. This projectwill explore on the display on VGA Screen
Explain of codeThis program incorporates the Moore StateMachine and a clock divider.This program has four inputs and outputs.The signals are explained in the Table
Explain of codeIn this program, the state machine comprises of three states,Idle, Shit-In and Sync DATA. The Idle state is the beginningstate where nCS and DONE will be 1. When START signal is setto one, the State will now enter Shift In mode where nCS andDONE will be 1. A counter will count till 15 to serially shift in the16 bits SDATA information from the microphone through thecompandor. When the counter hits 15, the 12 bit informationfrom SDATA signal (MSB to LSB) will be captured into DATA andoutput from ADC. At this point of time nCS and DONE signalswill turn to 1 to disable the ADC and tell the program that aconversion is completed. The START signal will then become 0and the finite state machine will go into Idle state again. In anypoint of the state the RST button is pressed, the state will gointo Idle
Explain of codeThis program was designed to meet the timing requirements in the ADC datasheet. In addition, the 12.5MHz clock pulse for ADC was also created using the Digital Clock Module (DCM) .This feature replaces the clock divider process Timing diagram for ADCS7574 ADC chip on PMOB MIC board
VGAStands for "Video Graphics Array." It is the standard monitor or display interface used in most PCs. Therefore, if a montior is VGA-compatible, it should work with most new computers. The VGA standard was originally developed by IBM in 1987 and allowed for a display resolution of 640x480 pixels. Since then, many revisions of the standard have been introduced. The most common is Super VGA (SVGA), which allows for resolutions greater than 640x480, such as 800x600 or 1024x768. A standard VGA connection has 15 pins and is shaped like a trapezoid
VGA A VGA signal contains 5 active signals Two TTL compatible signals for synchronization HSYNC – horizontal synchronization VSYNC – vertical synchronization
VGA In standard VGA format, the screen contains 640x480 pixels –640 pixels in a row – 480 rows The standard refresh rate for a screen is = 60 Hz – The entire screen is refreshed 60 times per second
VGAEach VGA monitor uses a clock that determines when each pixelis updated This clock operates at the VGA-specified frequency of25.175 MHz.Basis for the 25.175 MHz clock –Includes pixelprocessing time, horizontal and vertical synchronization times andguardband times– [640 (pixels/row) + 160 ] x [480 (rows) + 45 ] x 60 (refreshes/second)