Logic Design 2009

Nguyen Thanh Kien Department of Computer Engineering Faculty of Information Technology Hanoi University of Technology Digital Logic Design

About
Author: Nguyen Thanh Kien
Office:
Department of Computer Engineering
Faculty of Information Technology
Hanoi University of Technology
Mobile: +84 983 588 135
Email: [email_address]
[email_address]
ftp://dce.hut.edu.vn/kiennt

Content
1. Introduction
2. Function Minimization Methods
3. Larger Combinational Systems
4. Sequential Systems
5. Hardware Design Languages

Acknowledge
The following materials are used as reference for this slide:
“ Logic Circuits” slide, Dr. Trinh Van Loan.
Introduction to Logic Design, 2nd Ed, Alan B. Marcovitz, Mc. Graw Hill,2005
Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

Reference textbooks
Introduction to Logic Design, 2 nd Ed,, Alan B, Marcovitz, Mc. Graw Hill,2005
Foundation of Digital Logic Design, G.Langholz, A. Kandel, J. Mott, World Scientific, 1998

Grading policy
Homework: 20%
Lab work: 20%
Midterm: 30%
Final Exam (multichoice and writing): 30%

1. Introduction
1.1. Review of Number Systems
1.2. Switching Algebra and Logic Circuits

Chapter 1. Introduction

1.1.1 Number Representation
1.1.2 Binary Addition
1.1.3 Signed Numbers
1.1.4 Binary Subtraction
1.1.5 Binary Coded Decimal (BCD)
1.1.6 Other Codes

1.1.1. Number Representation
Numbers are normally written using a positional number system:
Base/radix: b (the number of digits)
Digits: 0..(b-1)
0 ≤ a i ≤ (b-1)
Binary: b=2, digits:0,1
Decimal: b=10, digits: 0,1,2,3,4,5,6,7,8,9
Octal: b=8, digits: 0,1,2,3,4,5,6,7
Hexadecimal: b=16, digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

1.1.1. Number Representation 11101.11 (2) = 1x2 4 +1x2 3 +1x2 2 +0x2 1 +1x2 0 +1x2 -1 +1x2 -2 = 29.75 (10)

Decimal:
b=10
Digits: 0,1,2,3,4,5,6,7,8,9
Eg:
539.45 (10) = 5x10 2 +3x10 1 +9x10 0 +4x10 -1 +5x10 -2
ai = 0..9

Binary:
b=2
Digits: 0,1
Eg:
1011.011(2) = 11 + 0*2 -1 + 1*2 -2 +1*2 -3 =11 + 0 + 0.25 + 0.125
= 11.375 (10)
ai = 0,1 bit – b inary dig it

Binary (cnt’)
n-bit binary number can represent which range?
a n-1 ...a 1 a 0 from 0 to 2 n -1
MSB – Most Significant Bit
LSB – Least Significant Bit
0001 = 1 1001 = 9
0010 = 2 1010 = 10
0011 = 3 1011 = 11
0100 = 4 1100 = 12
0101 = 5 1101 = 13
0110 = 6 1110 = 14
0111 = 7 1111 = 15
1000 = 8

Octal:
b=8
Digits: 0,1,2,3,4,5,6,7
Eg:
503.071 (8) = 5x8 2 + 0x8 1 + 3x8 0 + 0x8 -1 + 7x8 -2 + 1x8 -3
ai = 0..7
Hexadecimal:
b=16
Digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Eg:
1010 0011(2)= A3(16)
503.071 (16) = 5x16 2 + 0x16 1 + 3x16 0 + 0x16 -1 + 7x16 -2 + 1x16 -3
ai = 0..F

Convert from base b to base 10
Base b to base 10 conversion
Eg:0
1010.11 (2) = 10.75
1010.11 (8) = 0*8 0 +1*8 1 +0*8 2 +1*8 3 + 1*8 -1 +1*8 -2 = 0+8+0+512+0.125+0.015625
A12 (16) = 10572 = 2*16 0 + 1*16 1 + 10*16 2 = 2 + 16 + 2560= 2578

110.011(2)=?(10) 6.375
110.011(8)=?(10) 72.0175
110.011(16)=?(10) 272.039...

Convert from base 10 to base b
Base 10 to base b conversion
For integer part:
Divide integer part by b until the result is 0
Write remainders in reverse order to get the converted result.
For the odd part after “.”
Multiply by b until the result is 0

Convert from base 10 to base 2
The odd part after “.”
0.625 x 2 = 1 .25
0.25 x 2 = 0 .5
0.5 x 2 = 1 .0
Eg1: 6.625 (10) = ? (2)
The integer part
Eg2: 20.75 (10) = ? (2)
6.625 (10) = 110.101 (2) 0 1 2 1 1 2 3 0 2 6

20.75 (10) = ? (2) 10100.11(2)
20 2 0.75 * 2 = 1 .5
0 10 2 0.5 * 2 = 1 .0
0 5 2
1 2 2
0 1 2
1 0

20.75 (10) =? (8) =10100.11 (2) = 24.6 (8)
20 8 0.75 * 8 = 6 .0
4 2 8
2 0

Convert from base 2 to base 2 n
Group from right to left n-bit groups and replace the equivalent values in base 2 n
Eg:
101011(2) = ?(8) 1010.110 (2) =12.6 (8)
101011(2) = ?(16) 1010.110 (2) =A.C (16)

Convert from base 2 n to base 2
Each digit in base 2 n is replaced by n bit in base 2.
Eg:
37A.B(16)=?(2) = 0011 0111 1010 . 1011(2)

Convert from base i to base j
If both i and j are powers of 2, use base 2 as an intermediate base:
Eg: base 8  base 2  base 16
735.37 (8) = 0001 1101 1101 . 0111 1100(2) = 1DD.7C ? (16)
Else, use base 10 as an intermediate base:
Eg: base 5  base 10  base 2

1.1.6 Other Codes

Binary long addition similar to decimal long addition.
decimal binary carry 110 11110
A 2565 10110
B 6754 11011
sum 9319 110001
Eg: 10101 (2) + 11011 (2) = 110000 ? (2)

Overflow:
Occur when the result of addition is out of range of representation (the result can not be stored in the predefined number of bits)
In 8-bit computer, the result of addition of two binary numbers 10101010 and 11010011 is 9-bit binary number which can not be stored in 8-bit => overflow

n-bit adder in computer:
A = a n-1 a n-2 ...a 1 a 0
B = b n-1 b n-2 ...b 1 b 0

1.1.6 Other Codes

Represent sign and amplitude
Use the most-left-bit to represent sign:
0: positive, 1: negative
Eg: represent signed numbers using 4 bit:
+5 = 0101, -5 = 1101, -3 = 1011
Using 3 right bits to represent amplitude, we can represent from -7 to +7.
Drawbacks:
+0 = 0000, -0 = 1000 => complex when calculating
=> need an other representation

2’s complement representation
Most left bit is still sign bit
Positive and 0 numbers are expressed in usual binary format.
The largest number can be represented is 2 n-1 -1
n=8 => largest signed number: 2 8-1 -1 = 127
Negative number a is stored as the binary equivalent of 2 n -a in a n-bit system.
-3 is stored as 2 8 -3=11111101 in a 8-bit system
The most negative number can be stored is -2 n-1

+10 = 0000 1010
- 10 = 2 8 -10 = 1 0000 0000
– 0000 1010
1111 0110
- 10 = 1111 0110
+10 + (-10) = ? 0000 1010
1111 0110
1 0000 0000

Procedure to find binary representation of negative number in 2’s complement:
Find the binary equivalent of the magnitude
Complement each bit (0=>1, 1=>0)
Add 1
Eg: find representation of -13 in 8-bit signed number system using 2’s complement:
Magnitude: 13 = 0000 1101
Complement: 1111 0010
Add 1: 1
-13 = 1111 0011
+

Range of representation:
Use n bit to represent 2’s complement numbers
Range: -2 n-1 => 2 n-1 -1

4 bit representation of unsigned and signed (2’s complement) -1 15 1111 -2 14 1110 -3 13 1101 -4 12 1100 -5 11 1011 -6 10 1010 -7 9 1001 -8 8 1000 +7 7 0111 +6 6 0110 +5 5 0101 +4 4 0100 +3 3 0011 +2 2 0010 +1 1 0001 0 0 0000 Signed Unsigned Binary format

To find the magnitude of a negative number:
Complement each bit
Add 1
Eg: 1001 0110(2) = -106?
0110 1001
+ 1
01101010 = 106

Addition of signed numbers
The reason that 2’s complement is so popular is the simplicity of addition.
To add any two numbers, no matter what the sign of each is, we just do binary addition on their representation.
-2 1110 0 0000 +2 0010 +3 0011 +5 0101 +7 0111 -5 1011 -5 1011 -5 1011

Addition of signed numbers
Overflow
Occur when?
Add two numbers of the opposite sign?
Add two positive numbers?
Add two negative numbers?
maybe
Overflow occurs when adding two numbers with the same sign and the result is in different sign
0110 0101 = 101 + 0101 0010 = 82 1011 0111

1.1.6 Other Codes

Find the 2’s complement of the second operand, then add.
a – b = a + (-b)
Eg: 7 – 5 = ?
-5 1011 2 0010 + 1 -5 +1011 1010 7 0111 5 0101

1.1.6 Other Codes

Binary-Coded Decimal - BCD
BCD:
Use four bits (a nibble) to represent each of the decimal digits 0 through 9.
Eg:
375 = 0011 0111 0101 (BCD)
0001 0101 1111 15 0001 0100 1110 14 0001 0011 1101 13 0001 0010 1100 12 0001 0001 1011 11 0001 0000 1010 10 1001 1001 9 1000 1000 8 0111 0111 7 0110 0110 6 0101 0101 5 0100 0100 4 0011 0011 3 0010 0010 2 0001 0001 1 0000 0000 0 BCD Binary Decimal

1.1.6 Other Codes

ASCII
American Standard Code for Information Interchange - ASCII
Use seven bits to represent various characters on the standard keyboard as well as a number of control signal

Problems
1. Convert the following unsigned numbers:
98.625 (10) =? (2)
11011.011 (2) =? (10)
6A1.1E (16) =? (8)
2. Represent the following signed numbers:
a. -74 in 8-bit signed 2’s complement.
b. -74 in 16-bit signed 2’s complement.

1. Introduction

1.2.1 Definition of Switching Algebra
1.2.2 Basic Properties of Switching Algebra
1.2.3 Manipulation of Algebraic Functions
1.2.4 Representations of Algebraic Functions
1.2.5 Implementation of Functions with AND, OR, NOT, NAND, NOR, XOR Gates

Switching algebra is binary:
All variables and constant take on 0 or 1.
Light on/off, switch: up/down, voltage: low/high...
Quantities which are not naturally binary must be coded into binary format.
Three operators:
OR: a+b
AND: a.b
NOT: a’

Basic Properties of Switching Algebra
P1: Commutative:
a + b = b + a a.b = b.a
P2: Associative:
a + (b + c) = (a + b) + c a.(b.c) = (a.b).c
P3:
a + 0 = a a . 1 = a
P4:
a + 1 = 1 a . 0 = 0

P5:
a + a’ = 1 a . a’ = 0
P6: no coefficient and no exponent
a + a = a a . a = a
n.a=a (a) n =a
P7: complement
(a’)’ = a
P8: distributive:
a.(b+c) = a.b + a.c a + b.c = (a+b).(a+c)

P9: adjacency
ab + ab’ = a (a+b)(a+b’)=a
P10:
a + a’b = a +b a(a’+b) = ab
P11: De Morgan
(a + b)’ = a’b’ (ab)’ = a’ + b’
P12: absorption
a + ab = a a(a+b) = a
Basic Properties of Switching Algebra Basic Properties of Switching Algebra

P13: redundant
ab+b’c+ac = ab+b’c

Problems
1. Prove the following equalities:
a. xy’+y=x+y
b. xy+xz’+yz=xy+x’z => prove it incorrect
c. x’y’z+yz+xz=z
d. (x+y)[x’(y’+z’)]’+x’y’+x’z’ = 1

Manipulation of Algebraic Functions
A literal:
Is the appearance of a variable or its complement
Eg: x and x’ are two different literals
Expression ab’+bc’d+a’d+e’ has 8 literals
A product term:
Is one or more literal connected by AND operators
Expression ab’+bc’d+a’d+e’ has 4 product terms
Note: A single literal is also a product term

A standard product term - minterm:
Is a product term which includes every variable of the function, either uncomplemented or complemented.
Eg: for a function of four variables a,b,c,d :
the product term a’bc’d is a standard product term
the product term a’bd’ is not
Manipulation of Algebraic Functions Manipulation of Algebraic Functions

A sum of product - SOP:
Is one or more product terms connected by OR operators
Eg: ab’c+abc’+a’c+a’
d
A canonical sum – sum of standard product term
Is a sum of products expression where all terms are standard product terms.
Eg: A function of three variables a,b,c:
ab’c + abc’ + abc is a canonical sum
ab’c + abc’ + a is not

A minimum sum of products:
Is one of those SOP expression for a function that has the fewest number of product terms.
If there is more than one expression with fewest number of terms, then minimum is defined as one or more of those expressions with the fewest number of literals.
Eg:
F1(x,y,z) = x’yz’+x’yz+ xy’z’+xy’z+xyz
F2(x,y,z) = x’y+xy’+xyz
F3(x,y,z) = x’y+xy’+xz
F4(x,y,z) = x’y+xy’+yz
Manipulation of Algebraic Functions Manipulation of Algebraic Functions F3,F4 are minimum SOP of F1

A sum term:
Is one or more literals connected by OR operators
Eg:
a + b’ + c’
b’
A standard sum term - maxterm:
Is a sum term that includes each variable of the problem, either uncomplemented or complemented
Eg: For a function of four variables x,y,z,t
x+y+z’+t’ is a maxterm
x+y+t’ is not

A product of sum – POS:
Is one or more sum terms connected by AND
Eg:
(w+x’+y’)(w+y+z’)(w+x+z)
w
A canonical product – product of standard sum terms:
Is a product of sum term where all sum terms are standard

A minimum POS is defined the same way as SOP:
fewest number of terms
the same number of terms => fewest number of literals

Canonical forms
Three-variable minterm and Maxterm
x'+y’+z’ (M7) xyz (m7) 1 1 1 7 x'+y’+z (M6) xyz' (m6) 0 1 1 6 x'+y+z’ (M5) xy'z (m5) 1 0 1 5 x’+y+z (M4) xy’z’ (m4) 0 0 1 4 x+y’+z’ (M3) x'yz (m3) 1 1 0 3 x+y’+z (M2) x'yz’ (m2) 0 1 0 2 x+y+z’ (M1) x’y’z (m 1 ) 1 0 0 1 x+y+z (M0) x’y’z’ (m 0 ) 0 0 0 0 Maxterm minterm z y x Decimal

Canonical forms
Properties of minterm/Maxterm:
m i m j =0 if i≠j
=m i if i=j
M i +M j =1 if i≠j
= M i if i=j
m i =M i ’ and M i =m i ’ for every i

Canonical forms
An algebraic expression of a Boolean function can be derived from a given truth table in two ways:
By summing (ORing) those minterm for which the function takes a value 1.
By multiplying (ANDing) those maxterm for which the function takes a value 0.

Canonical forms f(x2,x1,x0)=m 1 +m 4 +m 5 +m 6 +m 7 = Σ (1,4,5,6,7) f(x2,x1,x0)=M 0 M 2 M 3 = Π (0,2,3) Canonical sum-of-products (SOP) Canonical product-of-sums (POS) 1 1 1 1 7 1 0 1 1 6 1 1 0 1 5 1 0 0 1 4 0 1 1 0 3 0 0 1 0 2 1 1 0 0 1 0 0 0 0 0 f x0 x1 x2 Decimal

F(a,b,c)= abc’+a’b’
F(a,b,c)=m0+m1+m6
∑ (0,1,6)
0 1 1 1 7 1 0 1 1 6 0 1 0 1 5 0 0 0 1 4 0 1 1 0 3 0 0 1 0 2 1 1 0 0 1 1 0 0 0 0 f c b a Decimal

Truth table
Venn diagram
Karnaugh map

Truth table
List all the possible binary combinations of the independent variables and display the corresponding binary values of dependant variables.

Truth table
n independent variables and m dependant functions:
2 n rows
n+m columns
3 independent variables 2 dependent functions 2 3 rows

Venn diagram
Venn diagram using ‘space’ to present logic
F(A,B)=A.B
F(A,B,C)=C.not(B)

Venn diagram A A A+B A.B A.B A+B

Karnaugh map
A Karnaugh map is a graphical method for representing the true table of a Boolean function.
K-map may be used for any variables number, but often at most six.
6 7 5 4 1 2 3 1 0 0 10 11 01 00 BC A 5 4 10 7 6 11 3 2 01 1 0 00 1 0 C AB

Karnaugh map (K-map)
If variables number is n => 2 n cells in K-map.
2 n cells are arranged in logical pattern for minimization purpose.
6 7 5 4 1 2 3 1 0 0 10 11 01 00 BC A

Two-variable K-map
F(A,B)
A B 0 1 0 1 B A 0 1 0 1 3 2 1 0 3 1 2 0

Two-variable K-map
F(A,B) = AB
A B 0 1 0 1 1 0 0 0

Three-variable K-map
F(A,B,C)
6 7 5 4 1 2 3 1 0 0 10 11 01 00 BC A 5 4 10 7 6 11 3 2 01 1 0 00 1 0 C AB

Three-variable K-map
F(x,y,z) = xyz + yz’ + x
1 1 1 1 1 0 1 1 1 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 0 0 0 0 F z y x 1 1 1 1 1 1 0 0 0 0 10 11 01 00 yz x 1 1 10 1 1 11 0 1 01 0 0 00 1 0 z xy

Four-variable K-map
F(A,B,C,D)
10 11 01 00 10 11 01 00 CD AB

Four-variable K-map
F(A,B,C,D) = AB + CD’ + BCD
1 0 0 0 10 1 1 1 1 11 1 1 0 0 01 1 0 0 0 00 10 11 01 00 CD AB

Five-variable K-map 00 01 11 10 AB CD 00 01 11 10 00 01 11 10 AB CD 00 01 11 10 E 0 1 5 variables Karnaugh Map consists of two 4 variables Karnaugh Map connected up/down.

Six-variable K-map 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 E 0 1 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 1 1 1 1 1 1 00 01 11 10 AB CD 00 01 11 10 F 0 1

Karnaugh map with don’t care don’t care ~ input conditions that not occur

Basic logic gates
AND OR NOT
1 1 1 0 0 1 0 1 0 0 0 0 out B A 1 1 1 1 0 1 1 1 0 0 0 0 out B A 0 1 1 0 out A

Basic logic gates
NAND NOR XOR
0 1 1 1 0 1 1 1 0 1 0 0 out B A 0 1 1 0 0 1 0 1 0 1 0 0 out B A 0 1 1 1 0 1 1 1 0 0 0 0 out B A

Implementation of Functions with AND, OR
Assume all inputs are available in uncomplemented and complemented
F1 = x’yz’+x’yz+xy’z’+xy’z+xyz F2 = x’y+xy’+xz

Implementation of Functions with AND, OR, NOT
Complemented inputs can be produced using inverters NOT:
X Y Z F

Multilevel circuits
A circuit is called n-level circuit if the maximum number of gates through which one signal must pass from input to output
two-level circuit three-level circuit

Implementation of Functions with NAND
Using equivalent change steps, every expression can be represented using only NAND gates.
NOT AND OR A B A.B (A’.B’)’ =A+B A B

Implementation of Functions with NAND
Represent the following expression using only NAND:
F(a,b,c) = ab + bc’ + b’
=

Implementation of Functions with NOR
Using equivalent change steps, every expression can be represented using only NOR gates.

Implementation of Functions with NOR
Represent the following expression using only NOR:
F(a,b,c) = ab + bc’ + b’

Chapter 2.
Logic Function Minimization Methods

2.1 Algebraic Method
2.2 The Karnaugh Map Method
2.3 Quine-McCluskey Method

What is minimization?
Number of operands is minimal and number of literal in each operand is minimal
Why minimization needed?
Minimize electronic components used to construct the circuit to implement that expression

2.1. Algebraic Method
Use algebraic properties to minimize expressions
Drawback:
Heuristic, depending on experience – no formal method/procedure
Manually
Not sure whether the last expression is minimal or not

2.1. Algebraic Method
Eg: Minimize these expressions using algebraic method:
F0(x,y,z)=xyz+x’yz+xy’z+xyz’
F1(a,b,c,d)=ab+abc+a’cd+a’c’d+a’bcd’
F2(A,B,C,D)=
F3(x,y,z)=(x+y)(x+y+z’)+y’
F4(a,b,c,d)=(a+b’+c)(a+c’)(a’+b’+c)(a+c+d)

1. Minimum Sum of Product Expressions Using the Karnaugh Map
2. Don’t Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems

Implicant, Prime Implicant
An implicant of a function is a product term that can be used in a SOP
Implicants of F Minterm Groups of 2 Groups of 4 A’B’C’D’ A’CD AB A’B’CD BCD A’BCD ABC’ ABC’D’ ABD ABCD’ ABC ABC’D ABD’ ABCD 10 1 1 1 1 11 1 01 1 1 00 10 11 01 00 CD AB

Implicant, Prime Implicant
A prime Implicant is an implicant which can not be contained in any other implicants.
1 1 1 1 10 1 1 11 1 1 01 1 1 1 00 10 11 01 00 CD AB

Essential Prime Implicant
Essential PI is a PI which contains at least one minterm which is not contained in other PI.
minterm 0 is only contained in PI B’D’ minterm 5 is only contained in PI BD => BD & B’D’ are two Essential PI 1 1 1 1 10 1 1 11 1 1 01 1 1 1 00 10 11 01 00 CD AB

2.2.1 Minimum Sum of Product Expressions
Rules to minimize using K-map:
Rule 1: Fill K-map cells with corresponding values
Rule 2: Group adjacent cells whose values are 1. Number of cells is 2 n .
Rule 3: Each group will be a part of result. Variables in each group will be excluded: 2 n cells => exclude n variables.

Step 2: Group adjacent cells whose values are 1. Number of cells is 2 n .
1 1 10 1 1 11 1 1 01 00 10 11 01 00 CD AB 1 1 10 1 1 11 1 1 01 1 1 00 10 11 01 00 CD AB

Step 3: Each group will be a part of result. Variables in each group will be excluded: 2 n cells => exclude n variables.
2.2.1 Minimum Sum of Product Expressions 2 1 cells => eliminate 1 variable 2 2 cells => eliminate 2 variables F(A,B,C,D) = A’BC’ + AC 1 1 10 1 1 11 1 1 01 00 10 11 01 00 CD AB

Example 1: Minimize these functions using K-map:
a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
b. F(A,B,C,D) = R(1,3,5,8,9,13,14,15)
c. F(A,B,C,D) = R(2,4,5,6,7,9,12,13)
d. F(A,B,C,D)= R(1,3,4,5,7,9,13,14,15)
e. F(A,B,C,D)=R(1,3,4,6,9,11,12,14)

a. F(A,B,C,D) = R(0,2,5,6,9,11,13,14)
= BC’D + AB’D + BCD’ + A’B’D’
1 1 10 1 1 11 1 1 01 1 1 00 10 11 01 00 CD AB

b. F(A,B,C,D) = R(1,3,4,6,9,11,12,14)
= B’D + BD’
1 1 10 1 1 11 1 1 01 1 1 00 10 11 01 00 CD AB

2.2 The Karnaugh Map
1. Minimum Sum of Product Expressions Using the Karnaugh Map
2. Don’t Cares
3. Product of Sums
4. Minimum Cost Gate Implementation
5. Five- and Six-Variable Maps
6. Multiple Output Problems

2.2.2 Don’t care
If the function has don’t care values in cells:
Cells with don’t care values
can be grouped with ‘1’ cells
Do not group only don’t
care cells in one group.

Examples: F(a,b,c,d)=R(1,3,5,7,12,13) don’t care (0,4,10,15) - 10 - 1 1 11 1 1 - 01 1 1 - 00 10 11 01 00 CD AB

1. Quine-McCluskey Method for One Output
2. Iterated Consensus for One Output
3. Prime Implicant Tables for One Output
4. Quine-McCluskey for Multiple Output Problems
5. Iterated Consensus for Multiple Output Problems
6. Prime Implicant Tables for Multiple Output Problems

2.3. Quine-Mcluskey method Karnaugh map cannot handle more than 6 variables. Quine-McCluskey method has no limitation with number of variables, and is suitable for computer algorithm. 0 1 00 01 1 11 1 1 10 1 1 AB C ABC+ABC+ABC+ABC+ABC 010 *10 11* 1*0 1*1 10* 110 111 100 101 1** find a pair of numbers of 1 bit difference

Quine-Mcluskey Procedure
1: Represent minterms in binary numbers
2: Group each minterm by the number of ‘1’ appearance
3: Make set of 1 bit different numbers between neighboring group
write the difference within parenthesis
mark * to the number which is not included in a set
4: Make set of 1 bit different sets with the same number in a parenthesis
append the difference to parenthesis
mark + to the set which is not included in a set
5: Iterate these step until all the generated set is marked *
6: Select prime implicants
7: Convert to logic variable

S1. Represent minterms in binary numbers f = ABCDEF+ABCDEF+ABCDEF+ABCDEF+ABCDEF +ABCDEF+ABCDEF +ABCDEF+ABCDEF+ABCDEF f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 f(A,B,C,D,E,F)=Σ(0,2,6,7,14,8,41,12,15,10)

S2. Grouping f = 000000+000010+000110+000111+001110 +001000+101001+001100+001111+001010 000000 once twice three times 000010 001000 000110 001100 001010 000111 001110 101001 four times 001111 group 0 group 1 group 2 group 3 group 4 group each term by the appearance of 1 no times

S3 & S4. Making set (1) 000000 0 000010 2 001000 8 000110 6 001010 10 001100 12 000111 7 001110 14 101001 41 001111 15 0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) 14,15(1) find a pair of 1 bit difference between neighboring group write difference within ( ) mark to the number not included in any set group 0 group 1 group 2 group 3 group 4

S3 & S4. Making set (2) 0,2 (2) 0,8 (8) 2,6(4) 2,10(8) 8,10(2) 8,12(4) 6,7(1) 6,14(8) 10,14(4) 12,14(2) 7,15(8) 14,15(1) 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) mark to the set not involved in the next level set when all the set is marked finish Each pair appears in duplicate find a pair of 1 bit different sets with the same value in ( ) between neighboring group append difference within ( )

S6. Selecting Prime Implicants (1) 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) 0 2 6 7 8 10 12 14 15 41 x x x x x x x x x x x x x x x x x If only one x in a column, then the row is inevitable implicant minterms (given at first) Prime implicant （　 marked ） write x into the position where minterm is included in the prime implicant inevitable implicant

S6. Selecting Prime Implicants (2) 41 0,2,8,10(2,8) 2,6,10,14(4,8) 8,10,12,14(2,4) 6,7,14,15(1,8) 0 2 6 7 8 10 12 14 15 41 x x x x x x x x x x x x x x x x x mini term prime implicants mark minterms involved in the inevitable implicants inevitable implicants

S7. C onversion to logic variables 41 101001 0,2,8,10(2,8) 000000 000010 001000 001010 8,10,12,14(2,4) 001000 001010 001100 001110 6,7,14,15(1,8) 000110 000111 001110 001111 ABCDEF ABDF ABCF ABDE F=ABCDEF +ABDF +ABCF +ABDE

Examples:
Minimize the following functions using Quine-Mcluskey method:
a.
b. F(a,b,c,d,e,f) =
∑ (17,21,25,29, 44,45,46,47,49,52,53,54,55,47,61)

Quine-Mcluskey method w ith don’t care
1: Represent logic function in sum of mini terms ==>A
2: Represent don’t care in sum of mini terms ==>B
3: If there exist duplication in A and B, remove from A
4: Apply Quine-McCluskey method for A and B
5: Be careful not to include B in selecting prime implicants

Quine-Mcluskey method w ith don’t care f=ABCD+BCD+ACD+ABCD+ABCD don’t care AD mini term ABCD 0000 0001 0010 0011 0101 0111 1011 1101 1111 decimal 0 1 2 3 5 7 11 13 15 first comparison second comparison 0,1(1) 0,2(2) 1,3(2) 1,5(4) 2,3(1) 3,7(4) 3,11(8) 5,7(2) 5,13(8) 7,15(8) 11,15(4) 13,15(2) 0,1,2,3(1,2) 1,3,5,7(2,4) 3,7,11,15(4,8) 5,7,13,15(2,8)

Quine-Mcluskey method w ith don’t care 0 2 11 13 15 0,1,2,3(1,2) 1,3,5,7(2,4) 3,7,11,15(4,8) 5,7,13,15(2,8) x x x x x x 00** 0**1 **11 *1*1 ABCD f=AB+CD+BD

Chapter 3.
Larger Combinational Systems

Introduction
Logic circuits are divided into two classes:
Combinational logic circuits
Output signals only depend on current input signals
Memoryless circuits
Sequential logic circuits
Output signals not only depend on current input signals, but also depend on those input signals in the past
Memory circuits

3.1 Delay in Combinational Logic Circuits
3.2 Adders and Other Arithmetic Circuits
3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.7 Three-State Gates
3.8 Gate Arrays-ROMs, PLAs and PALs
3.9 Larger Examples

Delay through logic gates
When the input to a gate changes, the output of that gate doesn’t change immediately; but there is a small delay Δ .
The output is stable after the longest delay path

3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

Half Adder  =a  b r = ab Half Adder (Carry-out) a b  r 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 =1 & a b  r HA a b  r (Result)

Addition of two n-bit numbers  4  3  2  1  0 r 3 r 2 r 1 r 0 A = a 3 a 2 a 1 a 0 +B = b 3 b 2 b 1 b 0 r 4  3 r 3  2 r 2  1 r 1  0 Summation

Full Adder  i r i+1  i = a i  b i  r i r i+1 = a i b i + r i (a i  b i ) FA a i r i b i  i r i+1 a i b i r i  i r i+1 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 10 11 01 00 a i b i r i 1 1 1 1 1 0 10 11 01 00 a i b i r i

Combinational logic circuit design procedure
Problems: design a combinational logic circuit to do smth.
Design procedure:
S1: Find inputs, outputs and relations.
S2: Construct truth table
S3: For each output, using K-map to minimize from truth table.
S4: Draw the circuit.

Example 1
Problem: Design a combinational logic circuit to implement this operation: M=N+3, N is 3-bit binary number, the number of bit of M is selected properly.
Solution:
S1: three inputs: n 2 n 1 n 0
four outputs: m 3 m 2 m 1 m 0

Example 1
S1: three inputs: n 2 n 1 n 0
four outputs: m 3 m 2 m 1 m 0
S2: truth table
S3:
m 3 = n 2 n 0 + n 2 n 1 n2 n1 n0 m3 m2 m1 m0 0 1 0 1 1 1 1 1 0 0 1 0 1 1 0 0 0 1 1 0 1 1 1 1 0 0 0 1 0 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 m0 m1 m2 m3 n0 n1 n2 1 1 1 0 1 0 0 0 0 0 10 11 01 00 n1n0 n2

Example 2
Problem: design a combinational logic circuit to calculate square of a 2-bit binary number.
Solution:
Step1: find inputs, outputs
Inputs: a1,a0
Outputs: b3,b2,b1,b0
Ex2

Step 2: truth table
Step3: using K-map to minimize outputs
b3 = a1.a0 b1 = 0
b2 = a1.a0’ b0 = a0
Example 2 1 0 0 1 1 1 0 0 1 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 b0 b1 b2 b3 a0 a1

Example 2
Step 4: Draw circuit
b3 = a1.a0 b1 = 0
b2 = a1.a0’ b0 = a0

Full Adder =1 & r i a i b i =1 &  i r i+1  1

Full Adder =1 & r i a i b i =1 &  i r i+1  1 HA HA

n-bit Adder
Serial n-bit adder
A = a n-1 a n-2 ...a 1 a 0 , B = b n-1 b n-2 ...b 1 b 0
Delay = n x Δ ? FA a n-1 b n-1 r n-1 r n  n-1 FA a n-2 b n-2 r n-2  n-2 FA a 1 b 1 r 1 r 2  1 FA a 0 b 0 r 0 = 0  0  n

n-bit Adder
Parallel n-bit adder:
r i+1 = a i b i + r i (a i  b i ) P i = a i  b i and G i = a i b i  r i+1 = G i + r i P i r 1 = G 0 + r 0 P 0 r 2 = G 1 + G 0 P 1 + r 0 P 0 P 1  1 G 1 G 0 P 1 r 2  1  2 & P 0 r 0 &  1 G 0 P 0 r 0 r 1  1  2 &

Parallel 4-bit addition r 4 =  4  3  2  1  0 r 2 r 1 a 2 b 2 a 1 b 1 a 0 b 0 P 3 G 3 P 2 G 2 P 1 G 1 P 0 G 0 Calculate P i and G i a 3 b 3 a 2 b 2 a 1 b 1 a 0 b 0 Carry calculation Sum calculation r 0 a 3 b 3 r 3 r 4 r 0

Subtractor
To subtract a-b , simply add a to 2’s complement of b .
Second choice:
Half Subtractor => Full Subtractor => n-bit Subtractor

Subtractor
Subtractor by using 2’s complement
A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 1 C1 C2 C3 C4 A B C S C+ FA A B C S C+ FA A B C S C+ FA A B C S C+ FA

Adder and Subtractor C1 C2 C3 C4 A B C S C+ FA A B C S C+ FA A B C S C+ FA A B C S C+ FA MPX MPX MPX MPX A3 A2 A1 A0 B3 B2 B1 B0 S3 S2 S1 S0 sel

3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

Decoder
An nxm decoder is a combinational circuit that converts binary information from n input lines to m output lines, where m≤2 n .
m = 2 n => complete decoder
Fundamental property: only one output is 1 for any given input combination.

Decoder
Complete decoders: m=2 n
Eg: + 3 bit inputs x1,x2,x3. + 8 bit outputs Y 0 ,Y 1 …Y 7

Design 3x8 decoder En if (En=0) Disable or D0...D7=0 else if (En=1) Function as a 3x8 decoder

BCD-to-decimal decoder BCD to decimal Decoder A B C D Y 0 Y 1 Y i Y 9 : : N A B C D Y 0 Y 1 .. Y 9 0 0 0 0 0 1 0 .. 0 1 0 0 0 1 0 1 .. 0 2 0 0 1 0 0 0 .. 0 3 0 0 1 1 0 0 .. 0 4 0 1 0 0 0 0 .. 0 5 0 1 0 1 0 0 .. 0 6 0 1 1 0 0 0 .. 0 7 0 1 1 1 0 0 .. 0 8 1 0 0 0 0 0 .. 0 9 1 0 0 1 0 0 . 1

BCD-to-decimal decoder   10     11 01 1 00 10 11 01 00 CD AB

Decoder
4x16 decoder using two 3x8 decoders

Decoder implementation of arbitrary functions F1(x1,x2,x3,x4)= Σ (0,1,3,8,12)

BCD-to-7segment decoder Each segment is a Light Emitting Diode (LED) a b c d e f g 1 1 0 1 1 1 1 1 0 0 1 9 1 1 1 1 1 1 1 0 0 0 1 8 0 0 0 0 1 1 1 1 1 1 0 7 1 1 1 1 1 0 1 0 1 1 0 6 1 1 0 1 1 0 1 1 0 1 0 5 1 1 0 0 1 1 0 0 0 1 0 4 1 0 0 1 1 1 1 1 1 0 0 3 1 0 1 1 0 1 1 0 1 0 0 2 0 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 0 0 0 0 0 g f e d c b a D C B A N

BCD-to-7segment decoder   1 1 10     11 1 1 1 0 01 1 1 0 1 00 10 11 01 00 CD AB

3.3 Decoders
3.4 Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

Encoder
An encoder is a circuit that performs the function of a decoder in reverse.
An mxn encoder has m inputs, n outputs where m≤2 n . The outputs generate the binary codes corresponding to m inputs.
For example: encoder for PC’s keyboard
Key <=> Character <=> Key code
102 keys, 8 bit ASCII

Keyboard encoder
9 keys
4-bit key code.
1 2 i Encoder 9 P 2 P 1 P i A B C D N=i ‘ 1’ P 9

Keyboard encoder A = 1 if (N=8) or (N=9) B = 1 if (N=4) or (N=5) or (N=6) or (N=7) C = 1 if (N=2) or (N=3) or (N=6) or (N=7) D = 1 if (N=1) or (N=3) or (N=5) or (N=7) or (N=9) 1001 9 1000 8 0111 7 0110 6 0101 5 0100 4 0011 3 0010 2 0001 1 ABCD N

Keyboard encoder  1  1  1  1 N=9 N=8 N=7 N=6 N=5 N=4 N=3 N=2 N=1 A B C D

3.3 Decoders
3.4 Encoders
3.5 Multiplexors
3.6 Demultiplexors
3.9 Larger Examples

Multiplexor
Multiplexor has one output and more than one input.
Function: select one of input for output
control inputs X 0 X 1 C 0 Y MUX 2-1 C 0 Y 0 X 0 1 X 1 C 1 C 0 Y 0 0 X 0 0 1 X 1 1 0 X 2 1 1 X 3 X 0 X 1 X 2 X 3 C 0 C 1 Y MUX 4-1

2-to-1 Multiplexor MUX 2-1 X 0 X 1 C 0 Y C 0 Y 0 X 0 1 X 1 1 1 1 1 1 0 10 11 01 00 X 1 X 0 C 0 C 0 X 1 X 0 Y 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1

2-to-1 Multiplexor

4-to-1 Multiplexor Y = s 1 ’s 0 ’I 0 + s 1 ’s 0 I 1 +s 1 s 0 ’I 2 + s 1 s 0 I 3

Application of multiplexor
Select source
Source 1 Source 2 Receiver Y 3 Y 2 Y 1 Y 0 A = a 3 a 2 a 1 a 0 B = b 3 b 2 b 1 b 0 C 0

Convert parallel-serial
A a 0 a 1 a 2 a 3 C 0 C 1 Y a 0 a 1 a 2 a 3 Y C 1 C 0 0 1 0 1 t t t

Implementation of arbitrary functions:
x 0 x 1 x 2 x 3 C 1 C 0 f(0,0) f(0,1) f(1,0) f(1,1) A B Y = f(A,B) Inputs to select function Variables

Example
F(A,B) = A’B + AB’
x 0 x 1 x 2 x 3 C 1 C 0 0 1 1 0 A B Y = f(A,B) Inputs to select function Variables

3.3 Decoders
3.4 Encoders and Priority Encoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

Demultiplexor
Demultiplexor has one input and more than one output
Function: select one of outputs for input
DeMUX 1-2 E C 0 S 0 S 1

Demultiplexor 1-4 E C 1 C 0 S 0 S 1 S 2 S 3

3.3 Decoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

3.7 Three-State Gates (Tristate)
Three state gates exhibit three states instead of two states. The three states are:
High : 1
Low : 0
High impedance : z
In this state the output is disconnected which is equal to open circuit. In the other words in that state circuit has no logic significant. We can have AND or NAND three-state gates but the most common is three-state buffer gate

3.7 Three-State Gates (Tristate)
We may use conventional gates such as AND or NAND as three-state gates but the most common is three-state buffer gate.
Note that buffer produces transfer function and can be used for power amplification. Three state buffer has extra input control line entering the bottom of the gate symbol (see next slide)

Three-State buffer
Three-state buffer
C A Y
----------------------
0 0 z
0 1 z
0 0
1 1 1

Application of three-state buffer
Three-state buffers can be used to implement
multiplexer

3.3 Decoders
3.5 Multiplexers
3.6 Demultiplexers
3.8 Gate Arrays - ROMs, PLAs and PALs
3.9 Larger Examples

3.8 Gate Arrays - ROM, PLA and PAL
PLA - Programmable Logic Arrays
PAL - Programmable Array Logic
ROM

PLA - Programmable logic arrays
Pre-fabricated building block of many AND/OR gates
actually NOR or NAND
"personalized" by making or breaking connections among the gates
programmable array block diagram for sum of products form
A B C Z1 Z2 m0 0 0 0 0 1 m1 0 0 1 0 0 m2 0 1 0 1 1 m3 0 1 1 0 0 m4 1 0 0 0 1 m5 1 0 1 1 0 m6 1 1 0 1 1 m7 1 1 1 1 0 • • • inputs AND array • • • outputs OR array product terms

Before programming
All possible connections are available before "programming"
in reality, all AND and OR gates are NANDs

After programming
Unwanted connections are "blown"
fuse (normally connected, break unwanted ones)
anti-fuse (normally disconnected, make wanted connections)
A B C F1 F2 F3 F0 AB B'C AC' B'C' A

PLA example
Multiple functions of A, B, C
F1 = A B C
F2 = A + B + C
F3 = A' B' C'
F4 = A' + B' + C'
F5 = A xor B xor C
F6 = A xnor B xnor C
full decoder as for memory address bits stored in memory A B C F1 F2 F3 F4 F5 F6 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 0 0 1 1 1 1 1 0 0 1 1 A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC A B C F1 F2 F3 F4 F5 F6

PALs and PLAs
Programmable logic array (PLA)
what we've seen so far
unconstrained fully-general AND and OR arrays
Programmable array logic (PAL)
constrained topology of the OR array
innovation by Monolithic Memories
faster and smaller OR plane
a given column of the OR array has access to only a subset of the possible product terms

ROM – Read Only Memories
Two dimensional array of 1s and 0s
entry (row) is called a "word"
width of row = word-size
index is called an "address"
address is input
selected word is output
decoder
0 n-1
Address
2 -1 n 0 word[i] = 0011 word[j] = 1010 bit lines (normally pulled to 1 through resistor – selectively connected to 0 by word line controlled switches) j i internal organization word lines (only one is active – decoder is just right for this) Example: 10 address x 8 data ROM 2 10 words x 8 ROM 1024 words x 8 ROM 1k x 8 ROM 1 1 1 1

ROM – Read Only Memories F0 = A' B' C + A B' C' + A B' C F1 = A' B' C + A' B C' + A B C F2 = A' B' C' + A' B' C + A B' C' F3 = A' B C + A B' C' + A B C'
Combinational logic implementation (two-level canonical form) using a ROM
truth table A B C F0 F1 F2 F3 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 block diagram ROM 8 words x 4 bits/word address outputs A B C F0 F1 F2 F3

ROM structure
Similar to a PLA structure but with a fully decoded AND array
completely flexible OR array (unlike PAL)
n address lines • • • inputs decoder 2 n word lines • • • outputs memory array (2 n words by m bits) m data lines

3.3 Decoders
3.5 Multiplexers
3.6 Demultiplexers
3.9 Larger Examples

3.9 Larger Examples
1. Seven-segment displays
2. Comparator

Comparator
1-bit full comparator:
a i > b i G i =1 a i < b i L i =1 a i = bi E i =1

Comparator
N-bit parallel comparator:

Midterm examination (90’)
1. Represent the following function in the canonical form SOP:
F(A,B,C)=(A+B’)C
2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:
F(A,B,C,D,E)= ∑(1,4,6,7,8,9,10,11,15)
3. Design 4x16 decoder using only 2x4 decoders.
4. Design a combinational logic circuit to calculate the following function: M=N+3 where N is BCD number (Binary-Coded Decimal).

Midterm examination 2 (90’)
1. Represent the following function in the canonical form SOP and POS:
F(A,B,C)=C
2. Use the Quine-McCluskey method to obtain the minimal sum for the following function:
F(A,B,C,D,E)= ∑(1,4,6,7,8,11,12,13,15)
3. Using 3x8 decoder to implement the following function:
F(A,B,C) = AB + B’C
4. Design a combinational logic circuit to calculate the following function: M=N+5 where N is BCD number (Binary-Coded Decimal).

Chapter 4.
Sequential Systems

4.1 Definitions
4.2 State Tables and Diagrams
4.3 Latches and Flip Flops
4.4 Analysis of Sequential Systems
4.5 Design of Sequential Systems
4.6 Solving Larger Sequential Problems

4.1 Definitions
Combinatorial circuit is memoryless.
In a circuit with memory , an output value at t n+1 must be a function not only of the inputs at t n+1 but also of the outputs at t n .
To achieve this, the circuit must have some feedback connections from its outputs to its inputs.
A circuit with memory is a combinatorial circuit incorporating some feedback connections.

Feedback and memory devices
To implement feedback, signals are fed back from outputs to inputs using memory devices.
A memory device stores an output value at time t n so that it can be input to the circuit at t n+1 .
But then, output at t n depends on input at t n-1 , which in turn depends on t n-2 …
The circuit maps input sequences to output sequences

Sequential circuit model
Circuits with memory are called sequential circuits .
Circuit inputs Circuit outputs Present state Next state

Sequential circuit model
Mealy model:
X : finite inputs. m inputs: x 1 ,x 2 ...,x m
S : finite states. n states: s 1 ,s 2 ...,s n
Y : finite outputs. l outputs: y 1 ,y 2 ...,y l
Fs : state function. s = Fs(X,S)
Fy : output function. y = Fy(X,S)
M oore: ~ Mealy
Difference: Fy = Fy(S)

Asynchronous/Synchronous sequential circuits
The timing of the signal in the circuit determine two types of sequential circuits:
Synchronous
Asynchronous.

Synchronous sequential circuits
In a synchronous sequential circuit, the state can change only at discrete instants of time.
To achieve that, the circuit uses a timing device, called a clock generator , that produce trains of periodic or aperiodic clock pulses .
The clock pulses are input to the memory devices so that they can change state only in response to the arrival of a pulse and only once for each pulse occurrence.
The operation of the circuit is synchronized with the clock pulse input.

Asynchronous sequential circuits
The behavior of an asynchronous sequential circuit depends only on the order in which the inputs change and can be affected at any instant of time.
There is no timing device in asynchronous sequential circuit (unclocked memory).

4.1 Definitions

State diagram
Depict graphically the operation of a sequential circuit.
Mealy state diagram

Example of state diagram
Example: a sequential circuit is used to detect the string “0101” from one input.

State diagram
Depict graphically the operation of a sequential circuit.
Moore state diagram

State table
State table presents in a tabular form the same information contained in the state diagram.
Mealy state table
Moore state table

Mealy state table PS: Present State NS: Next State k memory devices => 2 k rows n circuit inputs => NS portion contains 2 n columns Output portion also contains 2 n columns 1 0 c b d 0 0 a d c 0 0 c b b 0 0 a b a x=1 x=0 x=1 x=0 Output (z) NS PS c/1 b/0 d a/0 d/0 c c/0 b/0 b a/0 b/0 a x=1 x=0 NS/Output (z) PS

Moore state table The output portion always contains a single column. The entry at the intersection of any row with the output column indicates the output values corresponding to the PS associated with that row. 1 a f f 1 e f e 0 e d d 0 c d c 0 c b b 0 a b a z x=1 x=0 Output NS PS

Incompletely specified Mealy state table
Two inputs: x1,x2
A single output: z
b/0 c/1 -/- c/0 f a/0 d/1 f/0 -/- e b/1 e/- -/- a/- d -/- -/- f/1 f/0 c -/- -/- -/- e/0 b e/1 b/- c/1 -/- a 10 11 01 00 NS/Output (z) PS

4.1 Definitions

4.3. Latches and Flip-Flops
Simplest memory devices: Delay element
Δ T Yi yi yi(t+ Δ T) = Yi(t) Δ T Yi yi In practice, we don’t have to actually insert delay elements because propagation time delays between the inputs and the outputs of the combinatorial part of the circuit provide sufficient delay across the feedback loops.

Bistable devices:
Two stable states:
Q=0 : the device is reset (reset state)
Q=1: the device is set (set state)
A bistable device remains in one of two states indefinitely until directed by an input signal to change state.
Two types:
Latch
Flip-flop

Latch: transparency property :
Change state when the input values change
The new output state is delayed only by the propagation time delays of the gates between inputs and outputs of the latch.
Used to implement the memory part of asynchronous circuits.
Flip-flop: no transparency property
Has a control (triggering) input, called clock .
The state change only in response to a transition of a clock pulse at clock input.
Used to implement memory part of synchronous circuits

SR Latch
Two inputs: S (set), R (reset)
Two complementary outputs: Q, Q’
Indeterminate Next state Current state Q = (R+Q’)’ Q’= (S+Q)’ S Q R Q’ - 1 1 1 - 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 Q + S R Q

SR Latch Remember Reset Set Equivalent characteristic table SR=’00’ => Output no change A logic ‘1’ at inputs can change outputs’ states => active-HIGH latch S Q R Q’ Indeterminate 1 1 1
0
0 0 1 Q 0 0 Q + S R

SR Latch active-HIGH SR Latch active-LOW SR Latch S Q R Q’ S Q R Q’

SR Latch
Timing chart (NOR implementation)
set reset reset set S R Q Q

SR Latch
Timing chart (NAND implementation)
set reset set reset Q Q S R

SR Latch Circuit showing feedback Q + = R’Q + R’S SR=0 => Q + = R’Q + R’S + RS = R’Q + S for active-HIGH SR Latch Excitation table - 0 1 1 0 1 1 0 1 0 0 1 0 - 0 0 S R Q Q +

D Latch D Q Q’ S Q R Q’ D Graphic symbol Implementation using SR Latch Equivalent characteristic table Excitation table Q * = D 1 1 0 0 Q * D 1 1 1 0 1 0 1 0 1 0 0 0 D Q Q *

Gated Latches E: Enable input control The latch will not change state as long as E=0 E=1 SR=10 => Set E=1 SR=01 => Reset
The operation of latch is synchronized
with the E input => E: synchronous input
A latch with synchronous input is called gated latch. S Q E R Q’

Flip-flops
Latches implement memory part in asynchronous sequential circuits
Flip-flops do the same for synchronous circuits. FF has clock input and changes state synchronously with clock.
Four common types of flip-flops:
SR
D
JK
T

SR flip-flop
The triangle called dynamic indicator, indicates that the device responds only to an input clock transition from LOW (0) to HIGH (1) => Positive edge-triggered
Appending a small circle to the CLK input indicates that the flip-flop responds only to an input clock transition from HIGH (1) to LOW (0) => Negative edge-triggered
Positive edge-triggered Negative edge-triggered Pulse-triggered (Master-Slave) S Q CLK R Q S Q CLK R Q S Q CLK R Q

SR flip-flop
The information is entered on the leading edge of the clock pulse, but the flip-flop does change state (the output is postponed) until the trailing edge of the clock pulse.
Pulse-triggered (Master-Slave) Difference between Latch and Flip-flop?
The flip-flop can not change state except on the
triggering edge of clock pulse => synchronous
Present and next states in a latch are separated
In time by gate delays, they are separated by clock
periods in a flip-flop.
S Q CLK R Q’

SR flip-flop Indeterminate Next state Current state Characteristic table Reduced characteristic table Excitation table Q(t+1) = R’Q(t) + S (S=1 & R=1) is inhibited - 1 1 1 - 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 Q(t+1) S R Q Indeterminate 1 1 1
0
0 0 1 Q(t) 0 0 Q(t+1) S R - 0 1 1 0 1 1 0 1 0 0 1 0 - 0 0 S R Q Q(t+1)

Implementation of SR-FF CL S 　 Q R 　 Q Q Q S R SR-latch Q Q CL S R Implementation of SR-FF by SR-Latch

SR flip-flop
Timing chart
Q Q S R CL S Q CLK R Q

D flip-flop
D flip-flop is useful for storing a single bit
S Q CLK R Q D CLK Positive edge-triggered D flip-flop Implementation using SR flip-flop D Q CLK Q’

D flip-flop Next state Current state Characteristic table Reduced characteristic table Excitation table Q(t+1) = D 1
1
1
0
0 0 1 0 0 0 Q(t+1) D Q 1 1 0 0 Q(t+1) D 1 1 1 0 1 0 1 0 1 0 0 0 D Q Q(t+1)

JK flip-flop
JK = 00 => Q* = Q REMEMBER
JK = 01 => Q* = 0 RESET
JK = 10 => Q* = 1 SET
JK = 11 => Q* = not(Q) INVERT
S Q CLK R Q Positive edge-triggered JK flip-flop Implementation using SR flip-flop J Q CLK K Q’

JK flip-flop Next state Current state Characteristic table Reduced characteristic table Excitation table Q(t+1) = K’Q + JQ’ 0 1 1 1 1 1 1 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 0 Q(t+1) J K Q [Q(t)]’ 1 1 1
0
0 0 1 Q(t) 0 0 Q(t+1) J K - 0 1 1 - 1 1 0 1 - 0 1 0 - 0 0 J K Q Q(t+1)

Master-Slave flip-flop
A pulse-triggered flip-flop is a bistable device
states depend on the values of synchronous inputs at the leading edge of the clock pulse
those states does not change until the trailling edge of the clock pulse.

Master-Slave flip-flop
A pulse-triggered flip-flop consists of two latches, where one acts as a master and the other acts as a slave => Master-slave flip-flop
Master latch works when C=1 Slave latch works when C=0 S Q E R Q’ S Q E R Q’ Master Slave S C R Q Q’

Edge-Triggered flip-flop
A edge-triggered flip-flop is a bistable device whose state depends on the synchronous inputs either at the positive edge or at the negative edge of a clock pulse.

Positive edge-triggered D flip-flop
Q Q CLK D Y1 Y2

Positive edge-triggered JK flip-flop
Q Q CLK J K

Flip-Flop conversions
Each FF can mutually converted
How to implement y-FF by using x-FF
(1) Prepare expanded state table of y-FF
(2) Prepare excitation table of x-FF
(3) Combine (1) and (2)
(4) Calculate logic function for each input of x-ff
input of y-FF a 　 Q 　　 b Q Q Q combinatorial circuit x-FF CL CL

Example: Implement T-FF using SR-FF
S R Q Q+ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 - 1 1 1 - Expanded state table shows the state transition by the input T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 T-FF SR-FF

state 　　　　　 input Q 　　 Q+ 　　 S 　　 R 0 0 0 - 0 1 1 0 1 0 0 1 1 1 - 0 SR-FF S R Q Q+ 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 1 0 - 1 1 1 - expanded state table excitation table Excitation table shows the input value corresponding to the state transition

T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 T-FF state 　　　 input Q 　　 Q+ 　　 T 0 0 0 0 1 1 1 0 1 1 1 0 excitation table

T Q 0 0 0 1 1 0 1 1 Q+ 0 1 1 0 T Q Q+ S R 0 0 0 　 0 - 0 1 1 - 0 1 0 1 1 0 1 1 0 0 1 state 　　　　　 input Q 　　 Q+ 　　 S 　　 R 0 0 0 - 0 1 1 0 1 0 0 1 1 1 - 0 expanded state table of T-FF excitation table of SR-FF

Calculate logic function for FF input 0 1 0 1 T Q - 0 0 1 0 1 0 1 T Q 0 - 1 0 Karnaugh Map of R Karnaugh Map of S R=TQ S=TQ T Q Q+ S R 0 0 0 　 0 - 0 1 1 - 0 1 0 1 1 0 1 1 0 0 1 CL CL T S Q R Q Q Q

Example: Implement D flip-flop using JK FF
D Q 0 0 0 1 1 0 1 1 Q+ 0 0 1 1 D Q Q+ J K 0 0 0 　 0 - 0 1 0 - 1 1 0 1 1 - 1 1 1 - 0 state 　　　 input Q 　　 Q+ 　　 J K 0 0 0 - 0 1 1 - 1 0 - 1 1 1 - 0 excitation table of JK-FF expanded state table of D-FF

Example: Implement D flip-flop using JK FF
D Q Q+ J K 0 0 0 　 0 - 0 1 0 - 1 1 0 1 1 - 1 1 1 - 0 0 1 0 1 D Q - 1 1 - 0 1 0 1 D Q 0 - - 0 Karnaugh Map of J Karnaugh Map of K J=D K=D D J Q K Q Q Q CL CL

4.1 Definitions

Flip flop excitation equation
Flip Flop excitation equation express each synchronous input of each flip-flop as a function of the present state and the inputs of the circuit.
These Boolean functions are derived directly from the combinational part of the circuit.

Analysis procedure of sequential circuits
S1. Find excitation equations, and output equations.
S2. Establish state table.
S3. Establish state diagram.

Example1: A D flip-flop Moore model circuit
Excitation equations:
D1 = q1q2’ + xq1’
D2 = xq1
Output equations:
z = q2’
Since output is only a function of state z=q2’, and not directly of input, this is Moore model

Example1: A D flip-flop Moore model circuit State table State diagram q1* = d1 = q1q2’ + xq1’ q2* = d2 = xq1 0 01 00 11 1 11 10 10 0 10 00 01 1 10 00 00 z x=1 x=0 q1q2 q1*q2*

Example2: A JK flip-flop Moore model circuit
J A = x K A = xB’
J B = K B = x + A’
Output equations:
z = A + B
Since output is only a function of state z=A+B, and not directly of input, this is Moore model

Example2: A JK flip-flop Moore model circuit State table State diagram A* = A’J A + AK A = A’x+AxB’ B* = B’J B + BK B = B’(x+A’) + B(x+A’)’ 1 10 11 11 1 01 10 10 1 10 00 01 0 11 01 00 z x=1 x=0 AB A*B*

Example2: A JK flip-flop Moore model circuit

Example3: A D flip-flop Mealy model circuit
d1 = xq1 + xq2
d2 = xq1’q2’
Output equations:
z = xq1
Since output is a function of both present input and state z=xq1, this is Mealy model

Example3: A D flip-flop Mealy model circuit q1* = d1 = xq1 + xq2 q2* = d2 = xq1’q2’
Notice that:
State 11 is never reached, this example
really only has 3 states.
2. Whenever there is a 0 input, we return to
state 00.
1 0 10 00 11 1 0 10 00 10 0 0 10 00 01 0 0 01 00 00 x=1 x=0 x=1 x=0 q z q*

Mealy timing trace:
0 0 0 1 1 0 0 0 0 0 0 z 0 0 0 0 1 0 0 1 0 ? q2 0 1 1 1 0 0 1 0 0 ? q1 0 1 1 1 1 0 1 1 0 x

4.1 Definitions

Design Procedure for Sequential Systems
S1. From a word description, determine what needs to be stored in memory, that is, what are the possible states.
S2. If necessary, code the inputs and outputs in binary.
S3. Derive a state table or state diagram to describe the behavior of the system.
S4. Use state reduction techniques to find a state table that produces the same input/output behavior, but has fewer states.
S5. Choose a state assignment, that is, code the states in binary.
S6. Choose a flip flop type and derive the flip flop input maps or tables.
S7. Produce the logic equation and draw a block diagram.

Example1: Design sync sequential circuit using JK
Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0101 in input, otherwhile y=0.
Use Mealy model A: wait for first 0 B: had 0, wait for 1 C: had 01, wait for 0 D: had 010, wait for 1 System x=0101011 .. y=0001010 .. 1/0 A B C D 0/0 1/0 0/0 0/0 0/0 1/0 1/1

Example1: Design sync sequential circuit using JK Use two state variables q 1 q 2 to encode states in binary State table after assignment State table Q 1 Q 2 Q 1 Q 2 C,1 B,0 D A,0 D,0 C C,0 B,0 B A,0 B,0 A 1 0 x S D B 1 C A 0 1 0 q 1 q 2 10,1 01,0 11 00,0 11,0 10 10,0 01,0 01 00,0 01,0 00 1 0 x q 1 q 2

Example1: Design sync sequential circuit using JK q 1 *q 2 * Excitation table Application table 00,0 11,0 10 10,1 01,0 11 10,0 01,0 01 00,0 0 1 ,0 0 0 1 0 x q 1 q 2 0 - 1 1 1 - 0 1 - 1 1 0 - 0 0 0 K J q* q q 1 q 2 x 0 1 J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2 00 0 - 1- 0 - 0 - 01 0 - - 0 1 - - 1 11 - 1 - 0 - 0 - 1 10 - 0 1 - - 1 0 -

Example1: Design sync sequential circuit using JK Excitation equations: J 1 = xq 2 K 2 = x Output equation: y = xq 1 q 2 Minimization for J 1 q 1 q 2 x 0 1 J 1 K 1 J 2 K 2 J 1 K 1 J 2 K 2 00 0 - 1- 0 - 0 - 01 0 - - 0 1 - - 1 11 - 1 - 0 - 0 - 1 10 - 0 1 - - 1 0 - x q 1 q 2 0 1 00 0 0 01 0 1 11 - - 10 - -

Ex 1: Design sync sequential circuit using JK J 2 q 2 CLK K 2 q 2 J 1 q 1 CLK K 1 q 1 1 & =1 & y x CLOCK

Ex 2: Design sync sequential circuit using JK
Design a synchronous sequential circuit using JK flip-flop. The circuit has one input x, one output y. Output is 1 when receiving a string 0111 in input, otherwhile y=0.

Ex 3: Design sync sequential circuit using JK
Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.

S4. State reduction
State transition diagram may include redundancy. State reduction technique aims to simplify sequential circuit by reducing redundancy of the state transition diagram.
Equivalence:
two states are equivalent if output sequences are the same when the same input sequence is given
Method 1: Procedure to get equivalent states
Method 2: Reduction of incompletely specified state table

State reduction
Examples:
0/0 D C A B E F 1/0 0/0 1/1 0/0 1/1 0/0 1/0 1/0 0/0 1/0 0/0 D C B E AF 0/0 1/1 0/0 1/1 0/0 1/0 1/0 0/0 1/0 0/0 unify A and F A and F have the same output and transition state for the same input

State reduction
Examples:
D C B E AF 0/0 1/1 0/0 1/1 0/0 1/0 1/0 0/0 1/0 0/0 unify D and E C B AF DE 0/0 1/0 1/0 0/0 0/0 1/1 0/0 1/1 D and E have the same output and transition state for the same input

State reduction
Examples:
unify B and C C B AF DE 0/0 1/0 1/0 0/0 0/0 1/1 0/0 1/1 BC AF DE 0/0 1/0 0/0 1/1 0/0 1/0

State reduction 0 1 B C D E E D D F E F B C 0 1 0 0 0 1 0 1 0 0 0 0 0 0 A B C D E F current state next state output 0 1 B C D E E D D AF E AF 0 1 0 0 0 1 0 1 0 0 0 0 AF B C D E 0 1 B C DE DE DE DE DE AF 0 1 0 0 0 1 0 1 0 0 AF B C DE 0 1 BC BC DE DE DE AF 0 1 0 0 0 1 0 0 AF BC DE current state current state current state next state next state next state output output output

State reduction
Method 1: Procedure to get equivalent states
(1) Find multiple states that have the same output with the same input, and treat them as a set of state S1 (s1,s2,…)
(2) Rewrite state transition table by using the set of state.
(3) If the next state of the member of the set are different,the set includes nonequivalent state. Then divide the nonequivalent set and iterate (2)

Example of method 1 (1/4)
Reduce the state of the state transition diagram
a f e d c b 1/0 0/0 0/1 1/1 1/0 0/1 1/1 0/0 0/1 1/1 1/0 0/1 0 1 a b d c a b f e d c e a
0 1
0 0
1
0 0
1 1
1 1
1 0
a b c d e f current state next state output

Example of method 1 (2/4) (1) Find a set of state with the same output S1 (a,c) S2 (b,d,e) S3 (f) (2) Rewrite next state by using set of state a : S1,S2 c : S1,S2 b : S2,S1 d : S3,S2 e : S2,S1 f : S2,S1 S1 S2 S3 (b,e) and d are not equivakent hence, divide S2 into S2 and S4 a : S1,S2 c : S1,S2 b : S4,S1 e : S4,S1 f : S2,S1 S1 S2 S3 S4 d : S3,S2 equivalent equivalent 0 1 a b d c a b f e d c e a
0 1
0 0
1
0 0
1 1
1 1
1 0
a b c d e f current state next state output

Example of method 1 (3/4) 0 1 a b d c a b f e d c e a
0 1
0 0
1
0 0
1 1
1 1
1 0
a b c d e f current state next state output a : S1,S2 c : S1,S2 b : S4,S1 e : S4,S1 f : S2,S1 S1 S2 S3 S4 d : S3,S2 (2) Rewrite state transition table 0 1 S1 S2 S4 S1 S3 S2 S2 S1
0 1
0 0
1
1 1
1 0
S1 S2 S4 S3 current state next state output

Example of method 1 (4/4) a f e d c b 1/0 0/0 0/1 1/1 1/0 0/1 1/1 0/0 0/1 1/1 0/1 1 3 2 4 1/0 0/0 0/1 0/1 0/1 1/1 1/1 1/0 Generate state transition diagram 0 1 S1 S2 S4 S1 S3 S2 S2 S1
0 1
0 0
1
1 1
1 0
S1 S2 S4 S3 current state next state output

State reduction
Method 2: Reduction of incompletely specified state table
1: Find non compatible pairs
2: Find compatible set that doesn’t involve non compatible pairs
3: Obtain maximum compatible set
4: Calculate minimum closed set
5: Generate reduced state transition table
Incompletely specified: don’t care appears in the next state and output compatible pair: for every input, output are the same

Example of method 2 (1/5) current state next state input X 1 X 0 00 01 10 11 d e b - e - - a a - - e - b e d a b f - d c - e output input X 1 X 0 00 01 10 11 0 - 0 - - 1 - 0 1 - 0 - - 0 0 - - - - 0 1 - 1 0 a b c d e f a set of not compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f) Implication table a b c d e b c d e f × × × × × 1:fill in × at incompatible pair 2: fill in conditions to be compatible de be ad be bf ae ae de ae de ○ ef ad bc

Example of method 2 (2/5) (a,b,e) (a,b,c,d,e,f) (a,b,d,e,f) (b,c,d,e,f) (a,c) (a,f) (a,b,d,e) (b,d,e,f) (b,d) (b,c,e,f) (c,d,e,f) (b,d) (a,d,e) (b,d) (b,e,f) (d,e,f) (c,f) (b,e,f) (b,c,e) (c,f) (c,d,e) (d,e,f) (d,f) (d,e) (e,f) Maximum compatible set is (a,b,e),(a,d,e),(b,e,f),(b,c,e),(c,d,e) Decompose state set by non compatible pairs (a,c) (a,f) (b,d) (c,f) (d,f) remove duplicated node remove pair involved to other node

Example of method 2 (3/5) Maximum compatible set C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e) Logic function to represent each set involved a: C1+C2 b: C1+C3+C4 c: C4+C5 d: C2+C5 e: C1+C2+C4+C5 f: C3 Minimum closed set is a subset of maximum compatible set that involves all the state axbxcxdxexf = 1 (C1+C2)(C1+C3+C4)(C4+C5)(C2+C5)(C1+C2+C4+C5)C3 =(C1+C2C3+C2C4)(C2C4+C5) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4) (C1+C2+C4+C5)C3 =(C1C5+C2C3C5+C2C4)C3 =C1C3C5+C2C3C5+C2C3C4 hence (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) are candidates for minimum closed set

Example of method 2 (4/5) C1:(a,b,e) C2:(a,d,e) C3:(b,e,f) C4:(b,c,e) C5:(c,d,e) candidate for minimum closed set: (C1,C3,C5),(C2,C3,C5),(C2,C3,C4) check state transition of each candidate by using Implication table C1->(d,e)(a,d),(b,e),(b,f),(a,e) ->(a,d,e)(b,e,f) ->C1,C3 C2 ->(b,e),(a,d),(b,e),(b,f),(e,f) ->(b,e,f)(a,d) ->C3,C2 C3->(a,e),(d,e),(a,d),(b,c) ->(a,d,e)(b,c) ->C2,C4 C4->(a,e) ->(C1|C2) C5->(d,e),(e,f) ->(C2|C5),C3 C2,C3,C4 is closed Implication table a b c d e b c d e f × × × × × de be ad be bf ae ae de ae de ○ ef ad bc

Example of method 2 (5/5) C2:(a,d,e),C3:(b,e,f),C4:(b,c,e) are used current state next state input X 1 X 0 00 01 10 11 d e b - e - - a a - - e - b e d a b f - d c - e output inputX 1 X 0 00 01 10 11 0 - 0 - - 1 - 0 1 - 0 - - 0 0 - - - - 0 1 - 1 0 a b c d e f current state next state input X 1 X 0 00 01 10 11 C2 C3 C3 C2 C2 C4 C3 C2 C2 C4 C3 C2 output input X 1 X 0 00 01 10 11 0 0 0 0 1 1 1 0 1 1 0 0 C2 C3 C4 Reduced State Transition Table

State assignment
State assignment is to encode the state table into binary notation , the result is a transition table that combines next-state table and the output table.
Better state allocation results in an easy logic function for input of FF.
SP (Substitution Property): indicator for good state allocation.
a b c d b d a c C C1 C2 divide state into blocks so that the next state of the same block exists in the same block state is allocated to distinguish blocks of SP

State assignment q1 q2 q3 q4 q5 q6 q2 q3 q1 q5 q6 q4 q4 q6 q5 q2 q1 q3 input 　 X current state next state 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 0 1 1 0 1 0 1 0 0 1 0 0 0 0 1 0 u u u u u u u u u current state input 　 X next state 0 1 1 2 3 1+ 2+ 3+ 1+ 2+ 3+ block 1 (q1,q2,q3) block 2 (q4,q5,q6) This partition is SP The first bit is used to distinguish the blocks.

Chapter 5.
Hardware Design Languages

Problems
Problem 1:
Design a synchronous up/down counter using JK with one input x. If x=0 the circuit counts up from 0 to 3 and repeat, if x=1 the circuit counts down from 3 downto 0 and repeat.
Problem 2:
Design a synchronous counter using JK with one input x. The circuit counts from 0 to 13 then repeat.
Problem 3:

Problems for sequential circuit design
Textbook:
Chapter 6: 6.5
7a,b,c,d,
8a,b,c,d
9a,b,c,d
Chapter 7: 7.6
4,5,6,8,9,11,13,15

Logic Design 2009

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