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Assic 12th Lecture

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Verilog lect 12

Verilog lect 12

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  • 1. 1 Verilog HDLVerilog HDL ASIC DESIGN USING FPGA BEIT VII KICSIT Sept 24 2012 Lecture 12
  • 2. 2 Tasks Sept 24 2012 • In Verilog, you may use a task to encapsulate a behavior. • It is defined in a module. • It is invoked when its name is called in the procedural code. • It has access to all data objects, so it does not need inputs, outputs, though it can have inputs, outputs and inouts. Lecture 12
  • 3. 3 Tasks Sept 24 2012 • You can use the task statement to structure your Verilog code so that a portion of code is reusable. • Task may take more than zero time to complete ; they can have delays (#), wait statements and event controls (@) in them. • Task may call other Tasks and Functions. Lecture 12
  • 4. 4 Tasks Sept 24 2012 • The definition of a task is the following: task <task name>; // Notice: no parameter list or ()s <argument ports> <declarations> <statements> endtask •An invocation of a task is of the following form: <name of task> (<port list>);Lecture 12
  • 5. 5 Tasks Sept 24 2012 • Tasks can be used to apply stimulus; module hello_tsk ; initial begin say_hello ; // Task say_hello ; // Task end task say_hello; $display(“ Hello Verilog Tasks! ”) ; endtask endmodule Lecture 12
  • 6. 6 Tasks Sept 24 2012 module test_adder_t3; reg [7:0] a, b; reg cin; wire [7:0] sum, sum_chk; wire cout, cout_chk; // RTL Instance adder adder_inst(a, b, cin, sum, cout); //Model instance adder_model adder_model_inst(a,b,cin,sum_chk,cout_chk); initial begin test_design(0, 0, 0); // Task test_design(0, 1, 1); // Task test_design(10, 34 1); // Task test_design(150, 85, 0); // Task end Lecture 12
  • 7. 7 Tasks Sept 24 2012 task test_design; input [7:0] ax, bx; input cx; begin a = ax; b = bx; cin = cx; #50 if(sum !== sum_chk || cout !== cout_chk) begin $display(“ERROR: Sum is wrong"); $stop; end end endtask endmodule Lecture 12
  • 8. 8 Tasks Sept 24 2012 Lecture 12