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Assic 28th Lecture
 

Assic 28th Lecture

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Digital design lect 28

Digital design lect 28

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    Assic 28th Lecture Assic 28th Lecture Presentation Transcript

    • 1 System on ChipSystem on Chip ASIC DESIGN USING FPGA BEIT VII KICSIT 2012 Lecture 28
    • 2012 Lecture 28 2 System on Chip (SoC) System • A collection of all kinds of components and/or subsystems appropriately interconnected to perform the specified functions for end users.
    • 2012 Lecture 28 3 System on Chip (SoC) System on Chip • A system on a chip or system on chip (SoC or SOC) is an integrated circuit (IC) that integrates all components of a computer or other electronic system into a single chip. • It may contain digital, analog, mixed-signal, and often radio-frequency functions---all on a single chip substrate.
    • 2012 Lecture 28 4 System on Chip (SoC) • For example, a SoC for a sound-detecting device might include an audio receiver, an analog-to- digital converter ( ADC ), a microprocessor , necessary memory , and the input/output logic control for a user - all on a single microchip. • Another example is the Cell phone chip, which includes all the functionalities of a hand-held computer as well as GPS, Video Graphic processor, Radio Receiver/ Transmitter etc.
    • 2012 Lecture 28 5 SoC Example
    • 2012 Lecture 28 6 SoC Evolution
    • 2012 Lecture 28 7 SoC Explained
    • 2012 Lecture 28 8 ASIC Vs SoC
    • 2012 Lecture 28 9 SoC Architecture • Hardware: – Analog: ADC, DAC, PLL, TxRx, RF…etc. – Digital: Processor, Interface, Accelerator…etc. – Storage: SRAM, DRAM, FLASH, ROM…etc. • Software: – OS, Application SW.
    • 2012 Lecture 28 10 SoC Architecture
    • 2012 Lecture 28 11 SoC Applications
    • 2012 Lecture 28 12 SoC Advantages • Reduce overall system cost • Increase performance • Lower power consumption • Reduce size
    • 2012 Lecture 28 13 SoC Design Considerations • Architecture strategy • Design-for-test (DFT) strategy • Validation strategy • Synthesis and backend strategy • Integration strategy
    • 2012 Lecture 28 14 SoC Design Considerations • Architecture strategy – Central processing core – DSP cores – On chip bus – Easy plug-and-play IPs – I/O, peripherals – Platform based design methodology – Parameterization – Function partition
    • 2012 Lecture 28 15 SoC Design Considerations • Design-for-test (DFT) strategy – usually implemented using a full scan, MUXed flip- flop of scan insertion. – For embedded memories, Built in Self-test (BIST) and Module Test are best used.
    • 2012 Lecture 28 16 SoC Design Considerations • Validation strategy – Incorporating more third-party IPs, requires post- silicon system-on-a-chip (SoC) validation- especially IP validation. – immensely complicated effort. – post-silicon validation and debug require: Compact, parameterizable, distributed, reconfigurable, on-chip RTL instruments (technology-independent) with automated insertion for use in simulation, emulation, FPGA, and SoC/ASIC
    • 2012 Lecture 28 17 SoC Design Considerations • Integration strategy – Power Management. – The signal-level interface of the new component must fit to the SoC interconnection network. – functionality must match with the rest of the system. – Improve the reduced performance of the introduced components due to integration overheads.