Multi-Stage Clos Networks in Router Architecture


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Multi-Stage Clos Networks in Router Architecture [Scholarly Paper Presentation]

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Multi-Stage Clos Networks in Router Architecture

  1. 1. Multi-Stage Clos Networks<br />In<br />Router Architecture<br />Scholarly Paper Presentation<br />(In partial fulfillment for MS Degree in Computer Engineering)<br />Advisor: Dr. Jeremy Allnutt<br />Co-advisor: Dr BijanJabbari<br />George Mason University, Fairfax, Virginia<br />Lawrence Awuah<br /><br /><br />Fall 2007<br />
  2. 2. Summary<br /><ul><li>Switch Architecture Overview
  3. 3. Packet Forwarding and ASIC Design
  4. 4. Switch Fabric Implementation
  5. 5. Mathematical Analysis</li></li></ul><li>Switch Fabric Implementations<br /><ul><li>Maintains data plane connectivity among all of the PFEs.
  6. 6. Four operationally independent, identical and active switch planes.
  7. 7. The fifth plane that acting as a hot spare to provide redundancy. </li></li></ul><li>PFE and SIB connections[Fiber-Optic Array cables]<br /><ul><li>Each T640 routing node is connected to the TX Matrix platform by a five fiber-optic array cable set [VCSEL].
  8. 8. Each cable is connected to each of the five parallel switch planes (four active, one redundant as discussed above )
  9. 9. A fully populated routing matrix requires a total of 20 VCSEL fibers for switch plane interconnect (four T640 => 20 cables total).</li></li></ul><li>PFE & Switch Fabric Cell Distribution<br /><ul><li>Cell/Packet distribution similar to TCP/IP SAR of IP datagram packet.
  10. 10. Egress PFE drops packets if cells missing (assigned sequence #s).
  11. 11. Ingress PFE distribute packets on cell-by-cell basis - load balancing.</li></li></ul><li>TX-SIB, T640 Node and Clos Switch Fabric Communications<br /><ul><li>A T640 routing node – the first and third stages of the Clos switch fabric.
  12. 12. The TX Matrix platform functions as the switching core of a routing matrix - the second stage of the Clos switch fabric.
  13. 13. The TX Matrix platform contains five SIB cards connected to the T640-SIB cards in each T640 routing node by way of inter-chassis fiber-optic array cables.
  14. 14. Each TX Matrix SIB provides connectivity between the ingress and egress T640 routing nodes delivering high performance switching capacity. </li></li></ul><li>State Information<br />
  15. 15. Mathematical Analysis <br />Multi-stage Clos networks<br />Theory of 3-stage Clos networks applications in switching fabric.<br />Non-blocking condition k ≥ 2n-1.<br />
  16. 16. Analysis of interest:<br /><ul><li>Theory of multi-stage Clos networks applications in switching fabric.
  17. 17. flow control and congestion control, queuing algorithm – RED, WDRR.</li></ul>Single-stage crossbar switch<br />
  18. 18. Multi-stage Clos networks (3-stage)<br />Non-blocking condition k ≥ 2n-1 <=> assuming that;<br />(i) all the other n-1 input lines are already engaged in connections; (ii) all the other n-1 output lines connections are already engaged in connections; (iii) and all these 2n-2 intermediate-stage switches are occupied <br />For i input and j output lines to be connected, there must be at least 2n-2 + 1 (= 2n-1) intermediate-stage switches hence the condition k ≥ 2n-1.<br />
  19. 19. Clos Switch Fabric Implementation<br />Number of crosspoints for (2t-1)-stage switch:<br />
  20. 20. Random Early Detection (RED)<br /><ul><li>Active queue management and congestion avoidance algorithm.
  21. 21. The main goal of RED gateways is to provide congestion avoidance by controlling the average queue size developed in the network.
  22. 22. As avg (average queue size) varies from to, the packet marking probability pb varies linearly from 0 to maxp.</li></ul>Pb = maxp * (avg –<br /> ( –<br />The final packet-marking probability pa given by:<br /> Pa = pb / (1 – count * pb)<br />Where count is the number of non-marked packet since last marked packet. <br />Using bytes rather than packets then: <br />Pb = PacketSize * maxp * (avg –<br />MaxPacketSize ( –<br />
  23. 23. RED Algorithm<br />
  24. 24. Future work<br />Recommends research work in the area of<br /><ul><li>Hierarchical Multi-stage Clos networks Implementations for High Speed packet forwarding @ rate of Terabyte/s.</li></li></ul><li>*Computers & Human*<br />"Computers are incredibly fast, accurate and stupid. Human beings are incredibly slow, inaccurate and brilliant. Together they are powerful beyond imagination" <br />Einstein<br />Q & A !!!<br />Thank you<br />
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