Instruction, interrupts & io processing

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Instruction, interrupts & io processing

  1. 1. Unit 5 -INSTRUCTION, INTERRUPTS and IO PROCESSING Abhineet Anand Computer Science and Engg. Department University of Petroleum and Energy Studies, Dehradun December 9, 2012 Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 1 / 23
  2. 2. Outline 1 Instruction Codes Introduction Operation Code Operands 2 Instruction Formats Single accumulator organization General register organization Stack organization Evaluation of Arithmetic Statement 3 Addressing Modes Type of Addressing Modes 4 Program Interrupt Types of Interrupts Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 2 / 23
  3. 3. Instruction Codes A Computer instruction is binary code that specifies a sequence of micro operation for the Computer. The Computer reads each instruction from memory and places it in a control register. The control then interprets the binary code of the instruction and proceeds to execute it by issuing a sequence of micro operations. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 3 / 23
  4. 4. Instruction Codes An instruction code is a group of bits that instruct the computer to perform a specific task. It is usually divided into parts, each having its own particular interpretation. They are: Operation Code, and Operands. The most basic part of an instruction code is its operation part. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 4 / 23
  5. 5. Operation Code The Operation Code (OpCode) of an instruction is a group of bits that define each operation such add, subtract, multiply, shift, and complement. It must consist of at least n bits for a given 2n distinct operations. Suppose we are having 64 (26 ) operation then the length of OpCode will be 6. The control unit decode the OpCode and do the required operation. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 5 / 23
  6. 6. Operands The Operation must be performed on some data stored in processor register or in memory. Every Computer has its own particular instruction code format. The Simplest way to organize a computer is to have an instruction code format with two parts. The first part specifies the operation to be performed and the second specifies an address. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 6 / 23
  7. 7. Instruction Formats The bits of the instruction are divided into groups called fields. The most common fields found in instruction formats are: An Operation Code field that specifies the operation to be performed. An Address field that designates a memory address or a processor register. A mode field that specifies the way the operand or the effective address is determined. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 7 / 23
  8. 8. Instruction Formats Computer may have instruction of several different lengths containing varying numbers of addresses. The number of address fields in the instruction format of a computer depends on the internal organization of its registers. Most computers fall into one of three types of CPU organization: 1 2 3 Single accumulator organization. General register organization. Stack organization. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 8 / 23
  9. 9. Single accumulator organization All Operation are performed with an implied accumulator register. The instruction format in this type of computers uses one address field. Example: ADD X where, X is the address of the operand. The ADD instruction in this case results in the operation AC < − AC + M[X]. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 9 / 23
  10. 10. General register organization The instruction format in this type of computer needs three register address fields. Thus the instruction for an arithmetic addition may be written in an assembly language as ADD R1, R2, R3 to denote the operation R1 < − R2 + R3. The number of address fields in the instruction can be reduced from three to two if the destination register is the same as one of the source registers. ADD R1, R2 would denote the operation R1 < − R1 + R2. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 10 / 23
  11. 11. Stack organization The stack-organized CPU would have PUSH and POP instruction which requires an address filed. Example: PUSH X will push the word at address X to the top of the stack. The stack pointer is updated automatically. The operation is performed on the two items that are on top of the stack. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 11 / 23
  12. 12. Evaluation of Arithmetic Statement X=(A+B)∗(C+D) Three - Address Instruction ADD R1, A, B R1 < − M[A] + M[B] ADD R2, C, D R2 < − M[C] + M[D] MUL X, R1, R2 M[X] < − R1 ∗ R2. Two - Address Instruction MOV R1, A R1 < − M[A] ADD R1, B R1 < − R1 + M[B] MOV R2, C R2 < − M[C] ADD R2, D R2 < − R2 + M[D] MUL R1, R2 R1 < − R1 ∗ R2 MOV X, R1 M[X] < − R1 Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 12 / 23
  13. 13. Evaluation of Arithmetic Statement One - Address Instruction LOAD A AC< − M[A] ADD B AC < − AC + M[B] STORE T M[T] < − AC LOAD C AC < − M[C] ADD D AC< − AC + M[D] MUL T AC < − AC ∗ M[T] STORE X M[X] < − AC Zero - Address Instruction PUSH A TOS < − A PUSH B TOS < − B ADD TOS < − (A + B) PUSH C TOS < − C PUSH D TOS < − D ADD TOS < −(C + D) MUL TOS < − (C + D) * (A+ B) POP X M[X] < − TOS Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 13 / 23
  14. 14. Addressing Modes The way the operands are chosen during program execution is dependent on the addressing mode of the instruction. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually referenced. An Operation Code field that specifies the operation to be performed. An Address field that designates a memory address or a processor register. A mode field that specifies the way the operand or the effective address is determined. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 14 / 23
  15. 15. Addressing Modes Computer use addressing mode techniques for the purpose of accommodating one or both of the following provisions: To give programming versatility to the user by providing such facilities as pointers to memory, counters for loop control, indexing of data, and program relocation. To reduce the number of bits in the addressing field of the instruction. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 15 / 23
  16. 16. Type of Addressing Modes Although most addressing mode modify the address field of the instruction, there are two modes that need no address field at all. These are: Implied Mode: Operands are specified implicitly in the definition of the instruction. Like ”Complement Accumulator”. Zero-Address instruction in a stack-organized computer are implied-mode instruction since the operands are implied to be on top of the stack. Immediate Mode: In this mode the operand is specified in the instruction itself. Immediate-mode instruction are useful for initializing registers to a constant value. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 16 / 23
  17. 17. Type of Addressing Modes Register Mode: In this mode the operands are in register that reside within the CPU. The particular register is selected from a register filed in the instruction. Register Indirect Mode: In this mode the instruction specifies a register in the CPU whose content give the address of the operand in memory. The advantage is that the address field of the instruction uses a fewer bits to select a register than would have been required to specify a memory address directly. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 17 / 23
  18. 18. Type of Addressing Modes Auto-increment Mode or Auto-decrement Mode Direct Address Mode Indirect Address Mode Relative Address Mode Indexed Addressing Mode Base Register Addressing Mode Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 18 / 23
  19. 19. Program Interrupt The concept of program interrupt is used to handle a variety of problems that arise out of normal program sequence. Program interrupt refers to the transfer of program control from a currently running program to another service program as a result of an external or internal generated request. Control returns to the original program after the service program is executed. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 19 / 23
  20. 20. Program Interrupt The interrupt procedure is, in principal, quite similar, to subroutine call except for three variation: 1 2 3 The interrupt is usually initiated by an internal or external signal rather than from the execution of an instruction; The address of the interrupt service program is determined by the hardware rather than from the address field of instruction; and an interrupt procedure usually stores all the information necessary to define the state of the CPU rather than storing only the program counter. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 20 / 23
  21. 21. Program Interrupt These three procedure concept are clarified further as: 1 2 3 The content of the program counter The content of all processor register The content of certain status conditions The collection of all status bit conditions in the CPU is sometimes called a Program Status Word or PSW. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 21 / 23
  22. 22. Types of Interrupts There are three major types of interrupts that cause a break in the normal execution of a program. They are: 1 2 3 External Interrupts - come from input-output (I/O) devices, from a timing devices, from a circuit monitoring the power supply, or from any other external source. Example: I/O devices requesting for transfer of data, I/O devices finished transfer of data, elapsed time of an event, or power failure. Internal Interrupts - arise from illegal or erroneous use of an instruction or date, also known as trap. Example: register overflow, divide by zero, invalid operation code, stack overflow, protection violation. Software Interrupts - initiated by executing an instruction. It is a special call instruction that behaves like an interrupt rather than a subroutine call. Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 22 / 23
  23. 23. THANK YOU Abhineet Anand (UPES, Dehradun) INST n , INTERRUPTS, IO PROCESSING December 9, 2012 23 / 23

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