Basic logic gates

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Basic logic gates

  1. 1. Basic Logic Gates
  2. 2. Basic Logic Gates and Basic Digital Design• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
  3. 3. NOT Gate -- Inverter X Y 0 1 1 0
  4. 4. NOT• Y = ~X (Verilog)• Y = !X (ABEL)• Y = not X (VHDL)• Y = X’•Y = X•Y = X (textook)• not(Y,X) (Verilog)
  5. 5. NOTX ~X ~~X = X X ~X ~~X 0 1 0 1 0 1
  6. 6. AND Gate AND X Y ZX 0 0 0 0 1 0 Z 1 0 0Y 1 1 1 Z = X & Y
  7. 7. AND•X & Y (Verilog and ABEL)• X and Y (VHDL) V•X Y U•X Y•X * Y• XY (textbook)• and(Z,X,Y) (Verilog)
  8. 8. OR Gate OR X Y ZX 0 0 0 Z 0 1 1Y 1 0 1 1 1 1Z = X | Y
  9. 9. OR•X | Y (Verilog)•X # Y (ABEL)• X or Y (VHDL)•X + Y (textbook)•X V Y•X U Y• or(Z,X,Y) (Verilog)
  10. 10. Basic Logic Gates and Basic Digital Design• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
  11. 11. NAND Gate NAND X Y ZX 0 0 1 0 1 1 Z 1 0 1Y 1 1 0 Z = ~(X & Y) nand(Z,X,Y)
  12. 12. NAND Gate NOT-AND X Y W ZX 0 0 0 1 W 0 1 0 1 Z 1 0 0 1Y 1 1 1 0 W = X & Y Z = ~W = ~(X & Y)
  13. 13. NOR Gate NOR X Y ZX 0 0 1 Z 0 1 0Y 1 0 0 1 1 0Z = ~(X | Y)nor(Z,X,Y)
  14. 14. NOR Gate NOT-OR X Y W ZX 0 0 0 1 W Z 0 1 1 0Y 1 0 1 0 1 1 1 0W = X | YZ = ~W = ~(X | Y)
  15. 15. Basic Logic Gates and Basic Digital Design• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
  16. 16. NAND Gate X Z X Z = Y YZ = ~(X & Y) Z = ~X | ~Y X Y W Z X Y ~X ~Y Z 0 0 0 1 0 0 1 1 1 0 1 0 1 0 1 1 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1 0 0 0
  17. 17. De Morgan’s Theorem-1~(X & Y) = ~X | ~Y• NOT all variables• Change & to | and | to &• NOT the result
  18. 18. NOR GateX X Z ZY YZ = ~(X | Y) Z = ~X & ~Y X Y Z X Y ~X ~Y Z 0 0 1 0 0 1 1 1 0 1 0 0 1 1 0 0 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0
  19. 19. De Morgan’s Theorem-2~(X | Y) = ~X & ~Y• NOT all variables• Change & to | and | to &• NOT the result
  20. 20. De Morgan’s Theorem• NOT all variables• Change & to | and | to &• NOT the result• --------------------------------------------• ~X | ~Y = ~(~~X & ~~Y) = ~(X & Y)• ~(X & Y) = ~~(~X | ~Y) = ~X | ~Y• ~X & !Y = ~(~~X | ~~Y) = ~(X | Y)• ~(X | Y) = ~~(~X & ~Y) = ~X & ~Y
  21. 21. Basic Logic Gates and Basic Digital Design• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
  22. 22. Exclusive-OR Gate XOR X Y ZX Z 0 0 0Y 0 1 1Z = X ^ Y 1 0 1xor(Z,X,Y) 1 1 0
  23. 23. XOR•X ^ Y (Verilog)•X $ Y (ABEL)•X @ YgX ⊕ Y (textbook)• xor(Z,X,Y) (Verilog)
  24. 24. Exclusive-NOR Gate XNOR X Y ZX Z 0 0 1Y 0 1 0Z = ~(X ^ Y) 1 0 0Z = X ~^ Y 1 1 1xnor(Z,X,Y)
  25. 25. XNOR• X ~^ Y (Verilog)• !(X $ Y) (ABEL)•X @ YgX e Y• xnor(Z,X,Y) (Verilog)
  26. 26. Basic Logic Gates and Basic Digital Design• NOT, AND, and OR Gates• NAND and NOR Gates• DeMorgan’s Theorem• Exclusive-OR (XOR) Gate• Multiple-input Gates
  27. 27. Multiple-input Gates Z1 Z2 Z3 Z4
  28. 28. Multiple-input AND Gate Z1Output Z 1 is HIGH only if all inputs are HIGH An open input will float HIGH
  29. 29. Multiple-input OR Gate Z2Output Z 2 is LOW only if all inputs are LOW
  30. 30. Multiple-input NAND Gate Z3Output Z 3 is LOW only if all inputs are HIGH
  31. 31. Multiple-input NOR Gate Z4Output Z 4 is HIGH only if all inputs are LOW

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