Easy Learn to Verilog HDL


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Verilog Course Book

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Easy Learn to Verilog HDL

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  2. 2. VLSI DESIGN Reference Material By Verilog Course Team Where Technology and Creativity Meet
  3. 3. Contact UsVERILOG COURSE TEAMEmail:info@verilogcourseteam.comBlog: www.vlsiprojects.blogspot.comWeb: www.verilogcourseteam.comPhone: +91 98942 20795Revision: 1For hardcopies drop a mail or contact us.Disclaimer:Due care and diligence has been taken while editing of this material. VerilogCourse Team does not warrant or assume any legal liability or responsibilityfor the accuracy, completeness, or usefulness of any information, apparatus,product, or process disclosed. No warranty of any kind, implied, expressed orstatutory, including to fitness for a particular purpose and freedom fromcomputer virus, is given with respect to the contents of this material or itshyperlinks to other Internet resources. The material acts as just a reference tomove forward and understand the concept. Reference in this material to anyspecific commercial products, processes, or services, or the use of any trade,firm or corporation name is for the information, and does not constituteendorsement, recommendation, or favoring.
  4. 4. About Verilog Course TeamVerilog Course Team is a Electronic Design Services (EDS) for VLSI /EMBEDDED and MATLAB, delivering a wide variety of end-to-end services ,including design , development, & testing for customers around the world .Withproven expertise across multiple domains such as Consumer Electronics Market,Infotainment, Office Automation, Mobility and Equipment Controls. Verilog CourseTeam is managed by Engineers / Professionals possessing significant industrialexperience across various application domains and engineering horizontals . Ourengineers have expertise across a wide range of technologies, to the efforts ofengineering our clients. Leveraging standards based components and investments indedicated test lab infrastructure; we offer innovative, flexible and cost-effectiveServices and solutions.Our MissionOur mission is to provide cost effective, technology independent, good qualityreusable Intellectual Property cores with quality and cost factor are ourimportant constraints so as to satisfy our customers ultimately. We develop andcontinuously evaluate systems so as to pursue quality in all our deliverables. At ourteam, we are completely dedicated to customer’s requirements. Our products aredesigned and devoted to empower their competitive edge and help them succeed.     Visit www.verilogcourseteam.com for more details.
  5. 5. PrefaceThe India Semiconductor Association (ISA), an Indian semiconductorindustry organization, has briefed growth, trends and forecasts for the Indiansemiconductor market in collaboration with a U.S. consulting company Frost& Sullivan.The report titled as "ISA-Frost & Sullivan 2007/2008 Indian SemiconductorMarket Update."According to the report, total semiconductor consumption in India (total valueof semiconductors used for devices marketed in India) was $2.69 billion(USD) in 2006. The $2.69 billion represents 1.09% of the globalsemiconductor market. Of the total semiconductor consumption in India,consumption by local Indian set manufacturers accounted for $1.26 billion.The overall Indian semiconductor consumption will grow at an average rate of26.7% per year in 2006 through 2009. Based on the actual consumption in2006, the overall Indian semiconductor consumption is forecast to be $5.49billion in 2009. This represents 1.62% of the global semiconductor market in2009.Semiconductor consumption by local Indian set manufacturers is predicted toincrease at 35.8% per year in 2006 through 2009 and amount to $3.18 billionin 2009.This material is the result of the Verilog Course Team’s practical experienceboth in Design/Verification and Training. Many of the examples illustratedthroughout the material are real designs models. With Verilog Course Team’straining experience has led to step by step presentation, which addressescommon mistakes and hard-to-understand concepts in a way that easeslearning.Verilog Course Team invites suggestion and feedbacks from both students andfaculty community to improve the quality, content and presentation of thematerial.
  6. 6. VLSI DESIGNUNIT-I CMOS TECHNOLOGY1. An overview of silicon semiconductor technology 11.1 The Fabrication of a Semiconductor Device 11.1.2 Wafer Fabrication 21.1.3 Assembly 61.2 Basic CMOS Technology 81.2.1 A Basic n-well CMOS Process 91.2.2 A Basic p-well CMOS Process 131.2.3 Twin-Tub (Twin-Well) CMOS Process 131.2.4 Silicon On Insulator (SOI) Process 141.3 INTERCONNECT 181.3.1 Metal Interconnect 181.3.2 Polysilicon/Refractory Metal Interconnect 191.3.3 Local Interconnect 201.4 CIRCUIT ELEMENTS 211.4.1 Resistors 211.4.2 Capacitors 211.4.3 Electrically Alterable ROMs 231.4.4 Bipolar Transistors 241.4.5 LatchUp The Physical Origin of Latchup Latchup Triggering 281.4.6 Latchup Prevention 291.5. LAYOUT DESIGN RULES 301.5.1 Layer Representations 311.5.2 CMOS n-well Rules 321.5.3 Scribe Line 34Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  7. 7. VLSI DESIGN1.5.4 SOI Rules 341.5.5 Layer Assignments 351.6 PHYSICAL DEISGN 351.6.1 Basic Concept 351.6.2 CAD Tools sets 371.6.3 Physical Design-The Inverter 381.6.4 Physical Design-The NOR 381.6.5 Physical Design-The NAND 391.7 DESIGN STRATEGIES 391.7.1 Structured Design Strategies 401.7.2 Hierarchy 40UNIT 2 MOS TRANSISTOR THEORY2 .1 NMOS ENHANCEMENT TRANSISTOR 412.2 PMOS ENHANCEMENT TRANSISTOR 452.3 THRESHOLD VOLTAGE 452 . 3 . 1 Threshold Voltage Equations 462.4 BODY EFFECT 482.5 MOS Device Design Equations 482.5.1 Basic DC Equations 482.5.2 Second Order Effects 502.5.2.1 Threshold Voltage-Body Effect 512.5.2.2 Subthreshold Region 512.5.2.3 Channel-length Modulation 522.5.2.4 Mobility Variation 522.6 MOS MODELS 532.7 SMALL SIGNAL AC CHARACTERISTICS 54Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  8. 8. VLSI DESIGN2.8THE COMPLEMENTARY CMOS INVERTER – DC CHARACTERISTICS 552.8.1 βn/βp ratio 612.8.2 Noise Margin 622.9 THE TRANSMISSION GATE 642.10 THE TRISTATE INVERTER 68UNIT 3 SPECIFIFCATION OF VERILOG HDL3. HISTORY OF VERILOG 693.1 BASIC CONCEPTS 693.1.1 Hardware Description Language 693.1.2 VERILOG Introduction 693.1.3 VERILOG Features 703.1.4 Design Flow 703.1.5 Design Hierarchies 733.1.5.1 Bottom up Design 733.1.5.2 Top-Down Design 743.1.6 Lexical Conventions 743.1.6.1 Whitespace 753.1.6.2 Comments 753.1.6.3 Identifiers and Keywords 763.1.6.4 Escaped Identifiers 763.1.7 Numbers in Verilog 763.1.7.1 Integer Numbers 773.1.7.2 Real Numbers 773.1.7.3 Signed and Unsigned Numbers 773.1.8 Strings 783.1.9 Data types 79Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  9. 9. VLSI DESIGN3.1.9.1 Data Types Value set 793.1.9.2 Nets 793.1.9.3 Vectors 803.1.9.4 Integer, Real and Time Register Data Types 803.1.9.5 Arrays 813.1.9.6 Memories 823.1.9.7 Parameters 823.1.9.8 Strings 823.2 MODULES 833.2.1 Instances 843.3 PORTS 843.3.1 Port Declaration 853.3.2 Port Connection Rules 853.3.3 Ports Connection to External Signals 863.4 GATE DELAYS 873.4.1 Rise, Fall, and Turn-off Delays 873.4.2 Min/Typ/Max Values 883.5 MODELING CONCEPTS 893.6 SWITCH LEVEL MODELING 903.6.1 Switch level primitives 913.6.2 MOS switches 923.6.3 CMOS Switches 933.6.4 Bidirectional Switches 943.6.5Power and Ground 953.6.6 Resistive Switches 953.8 Delay Specification on Switches 963.8.1 MOS and CMOS switches 963.8.2 Bidirectional pass switches 97Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  10. 10. VLSI DESIGN3.9 GATE LEVEL MODELING 1013.9.1 Gate Types 1013.10 BEHAVIORAL AND RTL MODELING 1083.10.1 Operators 1083.10.1.1 Arithmetic Operators 1083.10.1.2 Relational Operators 1093.10.1.3 Bit-wise Operators 1103.10.1.4 Logical Operators 1123.10.1.5 Reduction Operators 1133.10.1.6 Shift Operators 1143.10.1.7 Concatenation Operator 1153.10.1.8 Replication Operator 1163.10.1.9 Conditional Operator 1163.10.1.10 Equality Operators 1173.10.2 Operator Precedence 1193.10.3 Timing controls 1193.10.3.1 Delay-based timing control 1193.10.3.2 Event based timing control 1223.10.3.3 Level-Sensitive Timing Control 1243.10.4 Procedural Blocks 1243.10.5 Procedural Assignment Statements 1253.10.6 Procedural Assignment Groups 1263.10.7 Sequential Statement Groups 1283.10.8 Parallel Statement Groups 1283.10.9 Blocking and Nonblocking assignment 1293.10.10 assign and deassign 1303.10.11 force and release 1313.10.12 Conditional Statements 131Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  11. 11. VLSI DESIGN3.10.12.1 The Conditional Statement if-else 1313.10.12.2 The Case Statement 1323.10.12.3 The casez and casex statement 1343.10.13 Looping Statements 1363.10.13.1 The forever statement 1363.10.13.2 The repeat statement 1363.10.13.3 The while loop statement 1373.10.13.4 The for loop statement 1383.11 DATA FLOW MODELING AND RTL 1393.11.1 Continuous Assignment Statements 1393.11.2 Propagation Delay 1413.12 STRUCTURAL GATE LEVEL DESCRIPTION 1413.12.1 2 to 4 Decoder 1413.12.2 Comparator 1423.12.3 Priority Encoder 1443.12.4 D-latch 1443.12.5 D Flip Flop 1453.12.6 Half adder 1453.12.7 Full adder 1463.12.8 Ripple Carry Adder 146UNIT 4 CMOS CHIP DESIGN4.1 INTRODUCTION TO CMOS 1484.2 LOGIC DESIGN WITH CMOS 1494.2.1 COMBITIONAL LOGIC 1494.2.2 INVERTER 1504.2.3 The NAND Gate 1514.2.4 The NOR Gate 152Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  12. 12. VLSI DESIGN4.3 TRANSMISSION GATES 1534.3.1Multiplexers 1534.3.2 Lathes 1534.4 CMOS CHIP DESIGN OPTIONS 1544.4.1 ASIC 1544.4.2 Uses of ASICs 1554.4.3 Full Custom ASICs 1554.4.5 Semi-Custom ASICs 1564.4.6 Standard- Cell-Based ASIC 1564.4.7 Gate Array Asic 1574.4.8 Channeled Gate Array 1584.4.9 Channelless Gate Array 1584.4.10 Structured Gate Array 1594.5 PROGRAMMABLE LOGIC 1594.5.1 Programmable Logic Structures 1604.5.2 Programmable of PALs 1614.5.3 Fusible Links 1614.5.4 UV-erasable EPROM 1614.5.5 EEPROM 1614.5.6 Programmable Interconnect 1624.6 ASIC DESIGN FLOW 163UNIT-5 CMOS TEST METHODS5.1 THE NEED FOR TESTING 1655.1.1 Functionality Tests 1665.2 MANUFACTURING TEST PRINCIPLS 1665.2.1 FAULT MODELS 1675.2.1.1 Stuck-At-Faults 167Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  13. 13. VLSI DESIGN5.2.1.2 Short-Circuit and Open-Circuit Faults 1685.2.2 Observability 1705.2.3 Controllability 1715.2.4 Fault Coverage 1715.2.5 Automatic Test Pattern Generation (Atpg) 1715.2.6 Fault Grading And Fault Simulation 1775.2.7 Delay Fault Testing 1785.2.8 Statistical Fault Analysis 1795.2.9 Fault Sampling 1805.3 DESIGN STRATEGIES FOR TEST 1805.3.1 Design for Testability 1805.3.2 Ad-Hoc Testing 1815.3.3 Scan-Based Test Techniques 1845.3.3.1 Level Sensitive Scan Design (LSSD) 1855.3.3.2 Serial Scan 1875.3.3.3 Partial Serial Scan 1885.3.3.4 Parallel Scan 1905.3.4 Self-Test Techniques 1915.3.4.1 Signature Analysis and BILBO 1915.3.4.2 Memory Self-Test 1935.3.4.3 Iterative logic array testing 1945.3.5 IDDQ testing 1945.4 CHIP-LEVEL TEST TECHNIQUES 1945.4.1 Regular Logic Array 1945.4.2 Memories 1955.4.3 Random Logic 1965.5 SYSTEM-LEVEL TEST TECHNIQUES 1965.5.1 Boundary Scan 196Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  14. 14. VLSI DESIGN5.5.1.1 Introduction 1965.5.1.2 The Test Access Port (TAP) 1975.5.1.3 The Test Architecture 1975.5.1.4 The TAP controller 1985.5.1.5 The Instruction Register (IR) 1985.5.1.6 Test-Data Registers 1995.5.1.7 Boundary Scan Registers 199Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                  
  15. 15. VLSI DESIGN CMOS TECHNOLOGYUNIT-IAn overview of silicon semiconductor technologySilicon in its pure or intrinsic state is a semiconductor, having a bulk electricalresistance somewhere between that of a conductor and an insulator. Theconductivity of silicon can be varied over several orders of magnitude byintroducing impurity atoms onto silicon crystal lattice. These dopants may eithersupply free electrons or holes. Impurity elements that use electrons are referred toas acceptors, since they accept some of the electrons already in the silicon,leaving vacancies or holes. Similarly, donor elements provide electrons. Siliconthat contains a majority of donors is known as n-type and that which contains amajority are brought together, the region where the silicon changes from n-typeand p-type materials are brought together, the region where the silicon changesfrom n-type to p-type is called a junction. By arranging junctions in certainphysical structures and combining these with other physical structures, varioussemiconductor devices may be constructed. Over the years, silicon semiconductorprocessing has evolved sophisticated techniques for building these junctions andother structures having special properties.An integrated circuit is a small but sophisticated device implementing severalelectronic functions. It is made up of two major parts: a tiny and very fragilesilicon chip (die) and a package which is intended to protect the internal siliconchip and to provide users with a practical way of handling the component. Thevarious steps in manufacturing processes of transistor both in “front-end” and“back-end” is taken as example, because it uses the MOS technology. Actually,this technology is used for the majority of the ICs manufacturing companies.1.1 The Fabrication of a Semiconductor DeviceThe manufacturing phase of an integrated circuit can be divided into two steps.The first, wafer fabrication, is the extremely sophisticated and intricate process ofmanufacturing the silicon chip. The second, assembly, is the highly precise andautomated process of packaging the die. Those two phases are commonly knownas “Front-End” and “Back-end”. They include two test steps:• Wafer probing and Final test.The flow chart is shown in figure 1.1.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 1 
  16. 16. VLSI DESIGN CMOS TECHNOLOGY Figure 1.1 Manufacturing Flow Chart of an Integrated Circuit1.1.2 Wafer Fabrication (Front-End)Identical integrated circuits, called die, are made on each wafer in a multi-stepprocess. Eachstep adds a new layer to the wafer or modifies the existing one. These layers formthe elements of the individual electronic circuits. The main steps for thefabrication of a die are summarized in the following table. Some of them arerepeated several times at different stages of the process. The order given heredoesnt reflect the real order of fabrication process. This step shapes the different components. The principle is quite simple (see drawing on next page). PhotoMasking Resin is put down on the wafer which is then exposed to light through a specific mask. The lighten part of the resin softens and is rinsed off with solvents (developing step). This operation removes a thin film material. There are Etching two different methods: wet (using a liquid or soluble compound) or dry (using a gaseous compound like oxygen or chlorine). This step is used to introduce dopants inside the Diffusion material or to grow a thin oxide layer onto the wafer. Wafers are inserted into a high temperature furnace (up to 1200 ° C) and doping gazes penetrate the silicon or react with it to grow a silicon oxide layer.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 2 
  17. 17. VLSI DESIGN CMOS TECHNOLOGY Ionic It allows to introduce a dopant at a given depth into Implantation the material using a high energy electron beam. It allows the realization of electrical connections Metal between the different cells of the integrated circuit Deposition and the outside. Two different methods are used to deposit the metal: evaporation or sputtering. Wafers are sealed with a passivation layer to prevent Passivation the device from contamination or moisture attack. This layer is usually made of silicon nitride or a silicon oxide composite. It’s the last step of wafer fabrication. Wafer thickness Back-lap is reduced (for microcontroller chips, thickness is reduced from 650 to 380 microns), and sometimes a thin gold layer is deposited on the back of the wafer.Initially, the silicon chip forms part of a very thin (usually 650 microns), roundsilicon slice: the raw wafer. Wafer diameters are typically 125, 150 or 200 mm (5,6 or 8 inches). However raw pure silicon has a main electrical property: it is anisolating material. So some of the features of silicon have to be altered, by meansof well controlled processes. This is obtained by "doping" the silicon.Dopants (or doping atoms) are purposely inserted in the silicon lattice, hencechanging the features of the material in predefined areas: they are divided into“N” and “P” categories representing the negative and positive carriers they hold.Many different dopants are used to achieve these desired features: Phosphorous,Arsenic (N type) and Boron (P type) are the most frequently used ones.Semiconductors manufacturers purchase wafers predoped with N or P impuritiesto an impurity level of.1 ppm (one doping atom per ten million atoms of silicon).There are two ways to dope the silicon. The first one is to insert the wafer into afurnace. Doping gases are then introduced which impregnate the silicon surface.This is one part of the manufacturing process called diffusion (the other part beingthe oxide growth). The second way to dope the silicon is called ionicimplantation. In this case, doping atoms are introduced inside the silicon using anelectron beam. Unlike diffusion, ionic implantation allows to put atoms at a givendepth inside the silicon and basically allows a better control of all the mainVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 3 
  18. 18. VLSI DESIGN CMOS TECHNOLOGYparameters during the process. Ionic implantation process is simpler thandiffusion process but more costly (ionic implanters are very expensive machines). Figure 1.2 Diffusion and Ionic Implantation ProcessesPhotoMasking (or masking) is an operation that is repeated many times duringthe process. This operation is described in figure 1.3. This step is calledphotomasking because the wafer is “masked” in some areas (using a specificpattern), in the same way one “masks out” or protects the windscreens of a carbefore painting the body. But even if the process is somewhat similar to thepainting of a car body, in the case of a silicon chip the dimensions are measuredin tenth of microns. The photoresist will replicate this pattern on the wafer. Theexposed part of the photoresist is then rinsed off with a solvent (usuallyhydrofluoric or phosphoric acid). Figure 1.3 Photo Masking ProcessMetal deposition is used to put down a metal layer on the wafer surface. Thereare two ways to do that. The process shown in the figure 1.4, is called sputtering.It consists first in creating a plasma with argon ions. These ions bump into thetarget surface (composed of a metal, usually aluminium) and rip metal atoms fromthe target. Then, atoms are projected in all the directions and most of themcondense on the substrate surface.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 4 
  19. 19. VLSI DESIGN CMOS TECHNOLOGY Figure 1.4 Metal Deposition ProcessEtching process is used to etch into a specific layer the circuit pattern that hasbeen defined during the photomasking process. Etching process usually occursafter deposition of the layer that has to be etched. For instance, the poly gates of atransistor are obtained by etching the poly layer. A second example is thealuminium connections obtained after etching of the aluminum layer. Figure 1.5 Etching ProcessPhotomasking, ionic implantation, diffusion, metal deposition, and etchingprocesses are repeated many times, using different materials and dopants atdifferent temperatures in order to achieve all the operations needed to produce therequested characteristics of the silicon chip. The resolution limit (minimal linesize inside the circuit) of current technology is 0.35 microns. Achieving suchresults requires very sophisticated processes as well as superior quality levels.Backlap is the final step of wafer fabrication. The wafer thickness is reducedfrom 650 microns to a minimum of 180 microns (for smartcard products).Wafer fabrication takes place in an extremely clean environment, where aircleanliness is one million times better than the air we normally breathe in a city,or some orders of magnitude better than the air in a heart transplant operatingtheatre. Photomasking, for example, takes place in rooms where there’s maximumVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 5 
  20. 20. VLSI DESIGN CMOS TECHNOLOGYone particle whose diameter is superior to 0.5 micron (and doesn’t exceed 1micron) inside one cubic foot of air.All these processes are part of the manufacturing phase of the chip itself. Siliconchips are grouped on a silicon wafer (in the same way postage stamps are printedon a single sheet of paper) before being separated from each other at thebeginning of the assembly phase.Wafer Probing. This step takes place between wafer fabrication and assembly. Itverifies the functionality of the device performing thousands of electrical tests, bymeans of special microprobes. Wafer probing is composed of two different tests:1. Process parametric test: This test is performed on some test samples andchecks the wafer fabrication process itself.2. Full wafer probing test: This test verifies the functionality of the finishedproduct and is performed on all the dies. The bad dies are automatically markedwith a black dot so they can be separated from good die after the wafer is cut. Arecord of what went wrong with the non-working die is closely examined byfailure analysis engineers to determine where the problem occurred so that may becorrected. The percentage of good die on an individual wafer is called its yield. Figure 1.6 Description of the Wafer Probing Operation1.1.3 Assembly (Back-End) Figure 1.7Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 6 
  21. 21. VLSI DESIGN CMOS TECHNOLOGYThe first step of assembly is to separate the silicon chips: this step is called diecutting (figure 1.7). Then, the dies are placed on a lead frame: the “leads” are thechip legs (which will be soldered or placed in a socket on a printed circuit board.On a surface smaller than a babys fingernail we now have thousands (or millions)of electronic components, all of them interconnected and capable of implementinga subset of a complex electronic function. At this stage the device is completelyfunctional, but it would be impossible to use it without some sort of supportingsystem. Any scratch would alter its behavior (or impact its reliability), any shockwould cause failure. Therefore, the die must be put into a ceramic or plasticpackage to be protected from the external world. Figure 1.8 Description of The Assembly Process Figure 1.9 Wire BondingWires thinner than a human hair (for microcontrollers the typical value is 33microns) are required to connect chips to the external world and enable electronicsignals to be fed through the chip. The process of connecting these thin wiresfrom the chip’s bond pads to the package lead is called wire bonding.The chip is then mounted in a ceramic or plastic package. The package not onlyprotects the chip from external shocks, but also makes the whole device easier tohandle. These packages come in a variety of shapes and sizes depending on thedie itself and the application in which it will be used.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 7 
  22. 22. VLSI DESIGN CMOS TECHNOLOGY Figure 1.10 Wire Bonding OperationProducts are then marked with a “traceability code” which is used by themanufacturer and the user to identify the function of the device (and its date offabrication). At the end of the assembly process, the integrated circuit is tested byautomated test equipment. Only the integrated circuits that passed the tests will bepacked and shipped to their final destination. Figure 1.11 Different Kinds of Plastic Packages1.2 Basic CMOS TechnologyComplementary metal–oxide–semiconductor (CMOS) (pronounced "see-moss), is a major class of integrated circuits. CMOS technology is used inmicroprocessors, microcontrollers, static RAM, and other digital logic circuits.CMOS technology is also used for a wide variety of analog circuits such as imagesensors, data converters, and highly integrated transceivers for many types ofcommunication. Frank Wanlass got a patent on CMOS in 1967 (US Patent3,356,858).Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 8 
  23. 23. VLSI DESIGN CMOS TECHNOLOGYCMOS is also sometimes referred to as complementary-symmetry metal–oxide–semiconductor. The words "complementary-symmetry" refer to the factthat the typical digital design style with CMOS uses complementary andsymmetrical pairs of p-type and n-type metal oxide semiconductor field effecttransistors (MOSFETs) for logic functions.Two important characteristics of CMOS devices are high noise immunity and lowstatic power consumption. Significant power is only drawn when the transistors inthe CMOS device are switching between on and off states. Consequently, CMOSdevices do not produce as much waste heat as other forms of logic, for exampletransistor-transistor logic (TTL) or NMOS logic, which uses all n-channel deviceswithout p-channel devices. CMOS also allows a high density of logic functions ona chip.The four main CMOS technologies are;• n-well process.• p-well process.• twin-tub process.• Silicon on insulator.1.2.1 A Basic n-well CMOS ProcessThe basic process steps for pattern transfer through lithography, and having gonethrough the fabrication procedure of a single n-type MOS transistor, thegeneralized fabrication sequence of n-well CMOS integrated circuits, as shown infigure. 1.12 In the following figures, some of the important process steps involvedin the fabrication of a CMOS inverter will be shown by a top view of thelithographic masks and a cross-sectional view of the relevant areas. The n-wellCMOS process starts with a moderately doped (with impurity concentrationtypically less than 1015 cm-3) p-type silicon substrate. Then, an initial oxide layeris grown on the entire surface. The first lithographic mask defines the n-wellregion. Donor atoms, usually phosphorus, are implanted through this window inthe oxide. Figure 1.12Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 9 
  24. 24. VLSI DESIGN CMOS TECHNOLOGYOnce the n-well is created, the active areas of the nMOS and pMOS transistorscan be defined. Figures 1.13 through 1.18 illustrate the significant milestones thatoccur during the fabrication process of a CMOS inverter.Following the creation of the n-well region, a thick field oxide is grown in theareas surrounding the transistor active regions, and a thin gate oxide is grown ontop of the active regions. The thickness and the quality of the gate oxide are twoof the most critical fabrication parameters, since they strongly affect theoperational characteristics of the MOS transistor, as well as its long-termreliability.Polysilicon Gate Connections Figure 1.13The polysilicon layer is deposited using chemical vapor deposition (CVD) andpatterned by dry (plasma) etching. CVD Chemical Reactions• SiH4(gas) + O2(gas) SiO2(solid) + 2H2 (gas)• SiH4(gas) + H2(gas) +SiH2(gas) 2H2(gas) + PolySilicon (solid)• Figure 1.14Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 10 
  25. 25. VLSI DESIGN CMOS TECHNOLOGY Isolation layer Figure 1.15The created polysilicon lines will function as the gate electrodes of the nMOS andthe pMOS transistors and their interconnects. Also, the polysilicon gates act asself-aligned masks for the source and drain implantations that follow this step.Using a set of two masks, the n+ and p+ regions are implanted into the substrateand into the n- well, respectively. Also, the ohmic contacts to the substrate and tothe n-well are implanted in this process step. Figure 1.16An insulating silicon dioxide layer is deposited over the entire wafer using CVD.Then, the contacts are defined and etched away to expose the silicon orpolysilicon contact windows. These contact windows are necessary to completethe circuit interconnections using the metal layer, which is patterned in the nextstep. Figure 1.17Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 11 
  26. 26. VLSI DESIGN CMOS TECHNOLOGYMetal (aluminum) is deposited over the entire chip surface using metalevaporation, and the metal lines are patterned through etching. Figure 1.18Since the wafer surface is non-planar, the quality and the integrity of the metallines created in this step are very critical and are ultimately essential for circuitreliability. The composite layout and the resulting cross-sectional view of thechip, showing one nMOS and one pMOS transistor (built-in n-well), thepolysilicon and metal interconnections. The final step is to deposit the passivationlayer (for protection) over the chip, except for wire-bonding pad areas. Thepatterning process by the use of a succession of masks and process steps isconceptually summarized in Figure. 1.19. It is seen that a series of masking stepsmust be sequentially performed for the desired patterns to be created on the wafersurface. An example of the end result of this sequence is shown as a cross-sectionon the right. Figure 1.19Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 12 
  27. 27. VLSI DESIGN CMOS TECHNOLOGY1.2.2 A Basic p-well CMOS ProcessN-well processes have emerged in popularity in recent years. Prior to this p-wellprocess was one of the most commonly available forms of CMOS. Typical p-wellfabrication steps are similar to an n-well process, except that a p-well isimplemented rather than an n-well. The first masking step defines the p-wellregions. This is followed by a low-dose boron implant driven in by a high-temperature step for the formation of the p-well. The well depth is optimized toensure against n-substrate to n+ diffusion breakdown, without compromising p-well to p+ separation.The next steps are to define the devices and other; to grow field oxide; contactcuts; and metallization. A p-well mask is used to define the p-channel transistorsand Vss contacts. Alternatively, an n-plus mask to define the n-channeltransistors, because the masks usually are the complement of each other. P-wellprocess are preferred in circumstances where the characteristics of the n- and p-transistors are required to be more balanced than that achievable in an n-wellprocess. Because the transistor that resides in the native substrate tends to havebetter characteristics, the p-well process has better p devices than an n-wellprocess. Because p-devices inherently have lower gain than n-devices, the n-wellprocess exacerbates this difference while a p-well process moderates thedifference.1.2.3 Twin-Tub (Twin-Well) CMOS ProcessTwin-tub technology provides the basis for separate optimization of the nMOSand pMOS transistors, thus making it possible for threshold voltage, body effectand the channel transconductance of both types of transistors to be tunedindependently. Generally, the starting material is a n+ or p+ substrate, with alightly doped epitaxial layer on top. This epitaxial layer provides the actualsubstrate on which the n-well and the p-well are formed. Figure 1.20 Twin-well CMOS process cross sectionSince two independent doping steps are performed for the creation of the wellregions, the dopant concentrations can be carefully optimized to produce thedesired device characteristics. The aim of epitaxy is to grow high-purity siliconVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 13 
  28. 28. VLSI DESIGN CMOS TECHNOLOGYlayers of controlled thickness with accurately determined dopant concentrationdistributed homogenously throughout the layer.The electrical properties of this layer are determined by the dopant and itsconcentration in the silicon. The process sequence, which is similar to the n-wellprocess apart from the tub formation where both p-well and n-well are utilized,entails the following steps,• Tub formation.• Thin-oxide construction.• Source and drain implantations.• Contact cut definition.• Metallization.In the conventional n-well CMOS process, the doping density of the well region istypically about one order of magnitude higher than the substrate, which, amongother effects, results in unbalanced drain parasitics. The twin-tub process (figure1.20) also avoids this problem.1.2.4 Silicon On Insulator (SOI) ProcessSilicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates insemiconductor manufacturing, especially microelectronics, to reduce parasiticdevice capacitance and thereby improve performance. SOI-based devices differfrom conventional silicon-built devices in that the silicon junction is above anelectrical insulator, typically silicon dioxide or (less commonly) sapphire. Thechoice of insulator depends largely on intended application, with sapphire beingused for radiation-sensitive applications and silicon oxide preferred for improvedperformance and diminished short channel effects in microelectronics devices.The insulating layer and topmost silicon layer also vary widely with application.The first implementation of SOI was announced by IBM in August 1998. Ratherthan using silicon as the substrate, the technologies have sought to use aninsulating substrate to improve process characteristics such as latchup and speed.Hence the emergence of Silicon On Insulator (SOI) technologies. SOI CMOSprocesses have several potential advantages over the traditional CMOStechnologies. These include closer packing of p- and n- transistors, absence oflatchup problems, and lower parasitics substrate capacitances. In the SOI processa thin layer of single-crystal silicon film is epitaxially grown on an insulator suchas sapphire or magnesium aluminium spinal. Alternatively, the silicon may begrown on SiO2 that has been in turn grown on silicon. This option has provedmore popular in recent years due to the compatibility of the starting material withconventional silicon CMOS fabrication. Various masking and doping techniquesVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 14 
  29. 29. VLSI DESIGN CMOS TECHNOLOGY(figure 1.21) are then used to form p-channel and n-channel devices. Unlike themore conventional CMOS approaches, the extra steps in well formation do notexist in the technology.The steps used in typical SOI CMOS process are as follows. A thin film (7-8 µm)of very lightly –doped n-type Si is grown over an insulator, Sapphire or SiO2 iscommonly used insulator (figure 1.21 a).• An anisotropic etch is used away the Si except where a diffusion area (n or p)will be needed. The etch must be anisotropic since the thickness of the Si is muchgreater than the spacing desired between the Si “islands: (figure 1.21 b, c).• The p-islands are formed next by masking the n-islands with a photoresist. Ap-type dopant, boron, for example is then implanted. It is masked by thephotoresist, but forms p-islands at the unmasked islands. The p-islands willbecome the n-channel devices (figure 1.12 d).• The p-islands are then covered with a photoresist and an n-type dopant-phosphorus, for example is implanted to form the n-islands. The n-islands willbecome the p-channel devices (figure 1.12 e).• A thin gate oxide (around 100-250 A) is grown over all of the Si structures,this is normally done by thermal oxidation.• A polysilicon film is deposited over the oxide. Often the polysilicon is dopedwith phosphorus to reduce its resistivity (figure 1.12f).• The polysilicon is then patterned by photomasking and is etched. This definesthe polysilicon layer in the structure (figure 1.12 g).• The next step is to form the n-doped source and drain of the n-channel devicesin the p-islands. The n-islands are covered with a photoresist and an n-typedopant, normally phosphorus is implanted. The dopant and an n-type dopant,normally phosphorus is implanted. The dopant will be blocked at the n-islands bythe photoresist, and it will be blocked from the gate region of the p-islands by thepolysilicon. After this step the n-channel devices are complete (figure 1.12 h).• The p-channel devices are formed next by masking the p-islands andimplanting a p-type dopant such as boron. The polysilicon over the gate of the n-island will block the dopant from the gate, thus forming the p-channel devices(figure 1.12 i).• A layer of phosphorus glass or some other insulator such as silicon dioxide isthen deposited over the entire structure.• The glass is etched as contact –cut locations. The metallization layer is formednext by evaporating aluminum over the entire surface and etching it to leave onlythe desired metal wires. The aluminium will flow through the contact cuts tomake contact with the diffusion or polysilicon regions (figure 1.12 j).• A final passivation layer of phosphorus glass is deposited and etched overbonding pad locations (not shown in figure).Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 15 
  30. 30. VLSI DESIGN CMOS TECHNOLOGYBecause the diffusion regions extend to the insulating substrate, only “sidewall”areas associated with source and drain diffusion contribute to the parasiticjunction capacitance. Since sapphire and SiO2 are extremely good insulators,leakage currents between transistors and substrate and adjacent devices are almosteliminated.In order to improve the yield, some processes use “preferential etch” in which heisland edges are tapered. Thus aluminium or poly runners can enter and leave theislands with a minimum step height. This is contrasted to “fully anisotropic etch”in which the undercut is brought to zero, as shown in figure 1.13.An” isotropicetch” is also shown in the same diagram for the comparison. Figure 1.12 SOI Process FlowVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 16 
  31. 31. VLSI DESIGN CMOS TECHNOLOGYThe advantages of SOI technology are as follows,• Due to absence of wells, transistor structures denser than bulk silicon arefeasible. Also direct n-to-p connections may be made.• Lower substrate capacitances provide the possibility for faster circuits.• No field-inversion problems exist( insulating substrate)• There is no latchup because of the isolation of the n-and p-transistors by theinsulating substrate.• Because there is no conducting substrate, there are no body-effect problems.However the absence of a backside substrate contact could lead to odd devicecharacteristic such as the “kink” effect in which the drain current increasesabruptly at around 2 to 3 volts.Some of the disadvantages are,• Due to absence of substrate diodes, the inputs are somewhat more difficult toprotect. Because device gains are lower, I/O structures have to be larger.• Single crystal sapphire, spinel substrate, and silicon SiO2 are considerablymore expensive than silicon substrate and their processing techniques tend to beless developed than bulk silicon techniques. Figure 1.13 Classification of Etching processesVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 17 
  32. 32. VLSI DESIGN CMOS TECHNOLOGY1.3 INTERCONNECTThe most important additions for CMOS logic processes are additional signal-and power-routing layers. This eases the routing (especially automatednetting) of logic signals between modules and improves the power and clockdistribution to modules. Improved mutability is achieved through additionallayers of metal or by improving the existing polysilicon interconnectionlayer.1.3.1 Metal InterconnectA second level of metal is almost mandatory for modern CMOS digital. Athird layer is becoming common and is certainly required for leading-edgehigh-density, high-speed chips. Normally, aluminum is used for the metallayers. I f some form of planarization is employed the second-level metalpitch can be the same as the first. As the vertical topology becomes morevaried, the width and spacing of metal conductors has to increase so thatthe conductors do not thin and hence break at vertical topology jumps (stepcoverage).Contacting the second-layer metal to the first-layer metal is achieved by avia, as shown in figure 1.14. If further contact to diffusion or polysilicon isrequired, a separation between the via and the contact cut is usuallyrequired. This requires a first-level metal tab to bridge between metal2 andthe lower-l e v e l conductor. It is important to realize that in contemporaryprocesses first level metal must be involved in any contact to underlyingareas. A number of contact geometries are shown in figure 1.15. Figure 1.14 Two-level metal process cross sectionProcesses usually require metal borders around the via on both levels ofmetal although some process require none. Processes may have norestrictions on the placement of via with respect to underlying layersVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 18 
  33. 33. VLSI DESIGN CMOS TECHNOLOGY(figure 1.15a) or they may have to be placed inside (figure 1.15b) oroutside (figur e1.15c) the underlying polysilicon or diffusion areas.Aggressive processes allow the stacking of vias on top of contacts, asshown in figure 1.15 (d). a b c d Figure 1.15 Two-level metal /via contact geometricsConsistent with the relatively large thickness of the intermediate isolationlayer, the vias might be larger than contact cuts and second-layer metalmay need to be thicker and require a larger via overlap although modernprocesses strive for uniform pitches on metal I and metal2.The process steps for a two-metal process are briefly as follows:• The oxide below the first-metal layer is deposited by atmosphericchemical vapor deposition (CVD).• The second oxide layer between the two metal layers is applied in asimilar manner.• Depending on the process, removal of the oxide is accomplished usinga plasma etcher designed to have a high rate of vertical ion bombardment.This allows fast and uniform etch rates. The structure of a via etchedusing such a method is shown in figure1. Polysilicon/Refractory Metal InterconnectThe polysilicon layer used for the gates of transistors is commonly usedas i t interconnect layer. However, the sheet resistance of dopedpolysilicon is between 20Ω and 40Ω/square. If used as a long distanceconductor, a polysilicon wire can represent a significant delay.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 19 
  34. 34. VLSI DESIGN CMOS TECHNOLOGYOne method to improve this that requires no extra mask levels is toreduce the polysilicon resistance by combining it with a refractory metal.Three such approaches are illustrated in figure 1.16.In figure 1.16(a)a silicide (e.g., silicon and tantalum) is used as the gate material. Sheetresistances of the order of 1 to 5Ω/square may be obtained. This is calledthe, silicide gate approach. Figure 1.16 Refractory metal interconnectSilicides are mechanically strong and may be dry ached in plasmareactors. Tantalum silicide is stable throughout standard processing andhas the advantage that it may be retrofitted into existing process lines.Figure 1.16(b) uses a sandwich of silicide upon polysilicon, which iscommonly called the polycide approach. Finally, the silicide/polysiliconapproach may he extended to include the formation of source and d r a i nr e g i o n s u s i n g t h e s i l i c i d e . This is called the salicide process (SelfAligned SILICIDE) (figur e 1.16c). The effect of all of these processesis to reduce the "second layer " interconnect resistance, allowing the gatematerial to be used as a moderate long-distance interconnect. This isachieved by minimum perturbation of an existing process. An increasingtrend in process is to use the salicide approach to reduce the resistance ofboth gate and source/drain conductors.1.3.3 Local InterconnectThe silicide itself may be used as a "local interconnect" layer forconnection within c e l ls . T i N i s u sed as a n example. Localinterconnect allows a direct connection between polysilicon anddiffusion, thus alleviating the need for area intensive contacts and metal.Figure 1.17 shows a portion (p-devices only) of a six transistor SRAMcell that uses local interconnect. The local interconnect has been used tomake the polysilicon-to-diffusion connections within the cell, therebyalleviating the need to use metal (and contacts). Metal2 (not shown) bitlines run over the cell vertically. Use of local i n t e r c o n n e c t in this RAMreduced the cell area by 25%.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 20 
  35. 35. VLSI DESIGN CMOS TECHNOLOGY Figure 1.17 Local interconnect as used in a RAM cellIn general, local interconnect if available can be used to complete intracellrouting, leaving the remaining metal layers for global wiring.1.4 CIRCUIT ELEMENTS1.4.1 ResistorsPolysilicon, if left undoped, is highly resistive. This property is used to buildresistors that are used in static memory cells. The process step is achieved bypreventing the resistor areas from being implanted during normalprocessing. Resistors in the tera-Ω (10 12 Ω) region are used. A value of3TΩ results in a standby current of 2µA for a 1 Mbit memory.For mixed signal CMOS (analog and digital), a resistive metal such asnichrome may be added to produce high-value, high-quality resistors. Theresistor accuracy might be further improved by laser trimming the resultresistors on each chip to some predetermined test specification. In thisprocess a high-powered laser vaporizes areas of the metal resistor until itmeets a measurement constraint. Sheet resistance values in the KΩ/squareare normal. The resistors have excellent temperature stability and long-termreliability.1.4.2 CapacitorsGood quality capacitors are required for switched-capacitor analog circuitswhile small high-value/area capacitors are required for dynamic memorycells. Both types of capacitors are usually added by using at least one extralayer of polysilicon, although the process techniques are very different.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 21 
  36. 36. VLSI DESIGN CMOS TECHNOLOGYPolysilicon capacitors for analog applications are the most straightforward.A second thin-oxide layer is required in order to have an oxide sandwichbetween the two polysilicon layers yielding a high-capacitance/unit area.Figure 1.18 shows a typical polysilicon capacitor. The presence of this,second oxide can also be used to fabricate transistors. These may differ,characteristics from the primary gate oxide devices. For memory capacitorsrecent processes have used three dimensions to increase thecapacitance/area. Figure 1.18 Polysilicon CapacitorOne popular structure is the trench capacitor,which has evolved considerably over the years to push memory densities to64Mbits and beyond. A typical trench structure is shown in figure 1.19(a).The sides of the trench are doped n+ and coated with a thin 1Onm oxide.Sometimes oxynitride is used because its high dielectric constant increasescapacitance. a b Figure 1.19 Dynamic memory capacitorsThe trench is filled with a polysilicon plug, which forms the bottom plate ofthe cell storage capacitor. This is held at VDD /2 via a metal connection at theVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 22 
  37. 37. VLSI DESIGN CMOS TECHNOLOGYedge of the array. The sidewall n+ forms the other side of capacitor and oneside of the pass transistor that is used to enable data onto the bit lines. Thebottom of the trench has a p+ plug that forms a channel stop region to isolateadjacent capacitors. The trench is 4µm deep and has a capacitance of 90fF.Rather than building a trench, figure 1.19(b) shows a fintype- capacitor usedin a 64-Mb DRAM. The storage capacitance is 20 to 30 fF. The fins have theadditional advantage of reducing the bit capacitance by shielding the bitlines. The fabrication of 3D-process structures such as these is a constantreminder of the skill, perseverance, and ingenuity of the process engineer.1.4.3 Electrically Alterable ROMsElectrically alterable/erasable R O M ( E A R O M / E E P R O M ) i s added toCMOS processes to yield permanent but reprogrammable s to r ag e to aprocess. This is usually added by adding a polysilicon layer. Figure 1.20shows a typical memory structure, which consists o f a stacked-gates t r u c t u r e . The normal gate is left floating, while a control gate is placedabove the floating gate. A very thin oxide called the tunnel oxideseparates the floating gate from the source, drain, and substrate. Figure 1.20 EEPROM technologyThis is usually 10 nm thick. Another thin oxide separates the control gatefrom the floating gate. By controlling the control-gate, source, and drainvoltages, the thin tunnel oxide between the floating gate and the drain ofthe device is used to allow electrons to "tunnel" to or from the floatinggate to turn the cell or on, respectively, using Fowler-Nordheim tunneling.Alternatively, by setting the appropriate voltages on the terminals, "hotelectrons" can be induced to charge the floating gate, therebyprogramming the transistor. In non-electrically alterable versions of thetechnology, the p r o cess can be reversed by illuminating the gate with UVlight. In these the chips are usually housed in glass-lidded packages.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 23 
  38. 38. VLSI DESIGN CMOS TECHNOLOGY1.4.4 Bipolar TransistorsThe addition of the bipolar transistor to the device repertoire forms thebasis for BiCMOS processes. Adding an npn-transistor can markedly aid inreducing the delay times of highly loaded signals, such as memory wordlines microprocessor busses. Additionally, for analog applications bipolartransistors may be used to provide better performance analog functions thanMOS alone. To get merged bipolar/CMOS functionality, Figure 1.21 Typical mixed signal BiCMOS process cross section Figure 1.22 BiCMOS process steps for the cross section shown in figure 1.21Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 24 
  39. 39. VLSI DESIGN CMOS TECHNOLOGYMOS transistors can add to a bipolar process or vice versa. In past days,MOS processes always had to have excellent gate oxides while bipolarprocesses had to have precisely controlled diffusions.A BiCMOS process has to have both. A mixed signal BiCMOS processcross section is shown in figure 1.21. This process features both npn- andpnp-transistors in addition to pMOS and nMOS transistors. The majorprocessing steps are summarized in figure 1.22, showing the particulardevice to which they correspond. The base layers of the process are similarto the process shown in figure 1.12. The starting material is a lightly-doped p-type substrate into which antimony or arsenic are diffused toform an n+ buried layer. Boron is diffused to form a buried p + layer. An n-type epitaxial layer 4.0 µm thick is then grown. N-wells and p-wells are thendiffused so that they join in the middle of the epitaxial layer. Thisepitaxial layer isolates the pnp-transistor in the horizontal direction, whilethe buried n+ layer isolates it vertically. The npn-transistor is junction-isolated. The base for the pnp is then ion-implanted using phosphorous. Adiffusion step follows this to get the right doping profile. The npn-collector is formed by depositing phosphorus before LOCOS. Fieldoxidation is carried out and the gate oxide is grown. Boron is then used toform the p-type base of the npn transistor.Following the threshold adjustment of the pMOS transistors, thepolysilicon gates are defined. The emitters of the npn-transistors employpolysilicon rather than a diffusion. These are formed by opening windowsand depositing polysilicon. The n+ and p+ source/drain implants are thencompleted. This step also dopes the npn-emitter and the extrinsic bases ofthe npn- and pnp-transistors (extrinsic because this is the part of the basethat is not directly between collector and emitter).Following the deposition of PSG, the normal two-layer metallization stepsare completed. Representative of a high-density digital BiCMOS processis that represented by the cross section shown in figure 1.23. The buried-layer-epitaxial layer-well structure is very similar to the previousstructure. However because this is a 0.8µm process, LDD structures mustbe constructed for the p-transistors and the n-transistors. The npn is formedby a double-diffused sequence in which both base and emitter are formedby impurities that diffuse out of a covering layer of polysilicon. Thisprocess, intended for logic applications, has only an npn-transistor. Thecollector of the npn is connected to the n-well, which is in turn connectedto the VDD supply. Thus all npn-collectors are commoned. A typical npn-transistor with a 0.8µm-square emitter has a current gain of 90 and an ft. of15 GHz.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 25 
  40. 40. VLSI DESIGN CMOS TECHNOLOGY Figure 1.23 Digital BiCMOS process cross section1.4.5 LatchUpIf every silver lining has a cloud, then the cloud that has plagued CMOS isa parasitic circuit effect called "latchup." The result of this effect is theshorting of the VDD and Vss lines, usually resulting in chip self-destruction or at least system failure with the requirement to power down.This effect was a critical factor in the lack of acceptance of early CMOSprocesses, but in cur-rent processes it is controlled by process innovationsand well-understood circuit techniques. The Physical Origin of LatchupThe source of the latchup effect may be explained by examining theprocess cross section of a CMOS inverter, shown in figure 1.24(a), onwhich is overlaid an equivalent circuit. The schematic depicts, in additionto the expected nMOS and pMOS transistors, a circuit composed of annpn-transistor, a pnp-transistor, and two resistors connected between thepower and ground rails (figure 1.24b). Under the right conditions, thisparasitic circuit has the VI characteristic shown in figure 1.24(c), whichindicates that above some critical voltage (known as the trigger point) thecircuit "snaps" and draws a large current while maintaining a low voltageacross the terminals (known as the holding voltage). This is, in effect, ashort circuit. As mentioned, the bipolar devices and resistors shown infigure 1.24 (b) are parasitic, that is an unwanted byproduct of producingpMOS and nMOS transistors. From the figure 1.24(a) reveals how thesedevices are constructed. The figure shows a cross-sectional view of atypical (n-well) CMOS process. The (vertical) pnp-transistor has itsemitter formed by the p+ source/drain implant used in the pMOStransistors. Note that either the drain or source may act as the emitteralthough the source is the only terminal that can maintain the latchupcondition. The base is formed by the n-well, while the collector is the p-Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 26 
  41. 41. VLSI DESIGN CMOS TECHNOLOGYsubstrate. The emitter of the (lateral) npn-transistor is the n+ source/drainimplant, while the base is the p-substrate and the collector is the n-well. Inaddition, substrate resistance R substrate and well resistance R well are due tothe resistivity of the semiconductors involved.Figure 1.24 The origin model, and VI characteristics of CMOS LatchupConsider the circuit shown in figure 1.24(b). If a current is drawn from thenpn-emitter, the emitter voltage becomes negative with respect to the base untilthe base emitter voltage is approximately 0.7 volts. At this point the npn-transistor turns on and a current flows in the well resistor due to common emittercurrent amplification. This raises the base emitter voltage of the pnp-transistor, which turns on when the pnp Vbe = - 0 . 7 volts. This in turnraises the npn base voltage causing a positive feedback condition, whichhas the characteristic shown in figure 1.24(c). At a certain npn-base-emitter voltage, called the trigger point, the emitter voltage suddenly"snaps back" and enters a stable state called the ON state. This state willpersist as long as the voltage across the two transistors is greater than theholding voltage shown in the figure. As the emitter of the npn is thesource/drains of the n-transistor, these terminals are now at roughly 4volts. Thus there is about 1 volt across the CMOS inverter, which willVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 27 
  42. 42. VLSI DESIGN CMOS TECHNOLOGYmost likely cause it to cease operating correctly. The current drawn isusually destructive to metal lines supplying the latched up circuitry. Latchup TriggeringFor latchup to occur the parasitic npn-pnp circuit has to be triggered andthe holding state has to be maintained. Latchup can be triggered bytransient cur-rents or voltages that may occur internally to a chip duringpower-up or externally due to voltages or currents beyond normaloperating ranges. Radiation pulses can also cause latchup. Two distinctmethods of triggering are possible, lateral triggering and verticaltriggering.Lateral triggering occurs when a current flows in the emitter of the lateralnpn-transistor. The static trigger point is set byI ntrigger ~ V pnp-on (1.1) α npn R wellwhereV pnp _ on~ 0.7 volts the turn-on voltage of the vertical pnp-transistoranpn = common base gain of the lateral npn-transistorRwell = well resistance.Vertical triggering occurs when a sufficient current is injected into theemitter of the vertical-pnp transistor. Similar to the lateral case, thiscurrent is multiplied by the common-base-current gain, which causes avoltage drop across the emitter base junction of the npn transistor due tothe resistance, R substrate . When the holding or sustaining point is entered, itrepresents a stable operating point provided the current required to stay inthe state can he maintained.Current has to be injected into either the npn- or pnp-emitter to initiatelatchup. During normal circuit in internal circuitry this may occur due tosupply voltage transients, but this is unlikely. However, these conditionsmay occur at the I/O circuits employed on a CMOS chip, where theinternal circuit voltages meet the external world and large currents canflow. Therefore extra precautions need to be taken with peripheral CMOScircuits.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 28 
  43. 43. VLSI DESIGN CMOS TECHNOLOGY a b Figure 1.25 Externally included latchupFigure 1.25(a) illustrates an example where the source of an nMOS outputtransistor experiences undershoot with respect to Vss due to some externalcircuitry. When the output dips below Vss by more than 0.7V, the drain ofthe nMOS output driver is forward biased, which initiates latchup. Thecomplementary case is shown in figure 1.25(b) where the pMOS outputtransistor experiences an overshoot more than 0.7V beyond VDD . Whetheror not in these cases latchup occurs depends on the pulse widths andspeed of the parasitic transistors.1.4.6 Latchup PreventionFor latchup to occur an analysis of the circuit in figure 1.25(b) finds thefollowing inequality has to be trueβnpnβpnp> 1+ (βnpn+1 ) I Rsubstrate +I Rwellβpnp) (1.2) I DD - I RsubstrateWhereI Rsubstrate == Vbe npn R substrateI Rwell = Vbe pnp RwellIDD =total supply currentVerilog Course Team www.verilogcourseteam.com Dream IT, We make U to Deliver                                 29 
  44. 44. VLSI DESIGN CMOS TECHNOLOGYThis equation yields the keys to reducing latchup to the point where itshould never occur under normal circuit conditions. Thus, reducing theresistor values and reducing the gain of the parasitic transistors are thebasis for eliminating latchup.Latchup may be prevented in two basic ways:• Latchup resistant CMOS processes.• Layout techniques.A popular process option that reduces the gain of the parasitic transistorsis the use of silicon starting-material with a thin epitaxial layer on top of ahighly doped substrate. This decreases the value of the substrate resistorand also provides a sink for collector current of the vertical pnp-transistor.As the epi layer is thinned, the latchup performance improves until a pointwhere the up-diffusion of the substrate and the down-diffusion of anydiffusions in subsequent high-temperature procession steps thwartrequired device doping profiles. The so-called retrograde well structure isalso used. This well has a highly doped area at the bottom of the well,whereas the top of the well is more lightly doped. This preserves goodcharacteristics for the pMOS (or nMOS in p-well) transistors but reducesthe well resistance deep in the well. A technique linked to these twoapproaches is to increase the holding voltage above the VDD supply. Thisguarantees that latchup will not occur.It is hard to reduce the betas of the bipolar transistors to meet the condi-tion set above. Nominally, for a 1µ n-well process, the vertical pnp has abeta of 10-100, depending on the technology. The lateral npn-current-gain which is a function of n+ drain to n-well spacing , i s b e t w e e n 2and 5.1.5 LAYOUT DESIGN RULESLayout rules, also referred to as design rules, can be considered as a pre-scription for preparing the photomasks used in the fabrication ofintegrated circuits. The rules provide a necessary communication linkbetween circuit designer and process engineer during the manufacturingphase. The main objective associated with layout rules is to obtain acircuit with optimum yield (functional circuits versus nonfunctionalcircuits) in as small an area as possible without compromising reliabilityof the circuit.In general, design rules represent the best possible compromise betweenperformance and yield. The more conservative the rules are, the morelikely it is that the circuit will function. However, the more aggressive theVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 30 
  45. 45. VLSI DESIGN CMOS TECHNOLOGYrules are, the greater the probability of improvements in circuitperformance. This improvement may be at the expense of yield.Design rules specify to the designer certain geometric constraints on thelayout artwork so that the patterns on the processed wafer will preservethe topology and geometry of the designs. It is important to note thatdesign rules do not represent some hard boundary between correct andincorrect fabrication. Rather, they represent a tolerance that ensures veryhigh probability of correct fabrication and subsequent operation. Forexample, one may find that a layout that violates design rules may stillfunction correctly, and vice versa. Nevertheless, any significant orfrequent departure (design-rule waiver) from design rules will seriouslyprejudice the success of a design.Two sets of design-rule constraints in a process relate to line widths andinterlayer registration. If the line widths are made too small, it is possiblefor the line to become discontinuous, thus leading to an open circuit wire.On the other hand, if the wires are placed too close to one another, it ispossible for them to merge together; that is, shorts can occur between twoindependent circuit nets. Furthermore, the spacing between twoindependent layers may be affected by the vertical topology of a process.The design rules primarily address two issues: (1) The geometrical reproduction of features that can be reproduced bythe mask- making and litho-graphical process and(2) The interactions between different layers.There are several approaches that can be taken in describing the designrules. These include micron rules stated at some micron resolution, andlambda (λ) based rules. Micron designs rules are usually given as a listof minimum feature sizes and spacings for all masks required in a givenprocess.1.5.1 Layer RepresentationsThe advances in the CMOS processes are generally complex andsomewhat inhibit the visualization of all the mask levels that are used inthe actual fabrication process. Nevertheless the design process can beabstracted to a manageable number of conceptual layout levels thatrepresent the physical features observed in the final silicon wafer. At asufficiently high conceptual level all CMOS processes use the followingfeatures: • Two different substrates. • Doped regions of both p- and n-transistor-forming material. • Transistor gate electrodes.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 31 
  46. 46. VLSI DESIGN CMOS TECHNOLOGY • Interconnection paths. • Interlayer contacts.The layers for typical CMOS processes are represented in various figuresin terms of: • A color scheme proposed by JPL based on the Mead-Conway colors. • Other color schemes designed to differentiate CMOS structures (e.g., the colors as used on the from cover of this hook) • Varying stipple patterns. • Varying line styles.Some of these representations are shown in below table.1.5.2 CMOS n-well RulesIn this section a version of n-well rules based on the MOSIS CMOSScalable Rules and compares those with the rules for a hypotheticalcommercial 1µ CMOS process shown in below table. The MOSIC rulesare expressed in terms of λ. These rules allow some degree of scalingbetween processes as, in principal, we only need to reduce the value of λ andthe designs will be valid in the next process down in size. Unfortunately, historyhas shown that processes rarely shrink uniformly. Thus industry usually uses theactual micron-design rules and codes designs in terms of these dimensions, oruses symbolic layout systems to target the design rules exactly. At this time, theamount of polygon pushing is usually constrained to a number of frequently usedVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 32 
  47. 47. VLSI DESIGN CMOS TECHNOLOGYstandard cells or memories, where the effort expended is amortized over manydesigns. Alternatively, the designs are done symbolically, thus relieving thedesigner of having to deal directly with the actual design rules. The rules are defined in terms of: • Feature sizes. • Separations and overlaps.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 33 
  48. 48. VLSI DESIGN CMOS TECHNOLOGY1.5.3 Scribe LineThe scribe line is specifically designed structure that surrounds thecompleted chip and is the point at which the chip is cut with a diamondsaw. The construction of the scribe line varies from manufacturer tomanufactures1.5.4 SOI RulesSOI rules closely follow bulk CMOS rules except the n+ and p+ regionscan abut. This allows some interesting and latch circuits. A spacing rulebetween the poly and island edges. This can be caused by thin or facultyoxide covering over the islands.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 34 
  49. 49. VLSI DESIGN CMOS TECHNOLOGY1.5.5 Layer AssignmentsThe below table lists the MOSIS Scalable CMOS design-rule layerassignments for the Caltech Intermediate Form (CIF) and Calma streamformat.1.6. PHYSICAL DEISGN1.6.1 Basic ConceptFigure 1.26 shows part of the design flow, the physical design steps, foran ASIC (omitting simulation, test, and other logical design steps thathave already been covered). Some of the steps in Figure 1.26 might beperformed in a different order from that shown. For example, dependingon the size of the system, perform system partitioning before any designentry or synthesis. There may be some iteration between the differentsteps too. First to apply system partitioning to divide a microelectronicssystem into separate ASICs.In floorplanning sizes estimate and set the initial relative locations of thevarious blocks in our ASIC (sometimes we also call this chip planning).Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 35 
  50. 50. VLSI DESIGN CMOS TECHNOLOGYAt the same time to allocate space for clock and power w i r i n g a n ddecide on the location of the I/O and power pads. Placement defines thelocation of the logic cells within the flexible blocks and sets aside space forthe interconnect to each logic cell. Placement for a gate-array or standard-cell design assigns each logic cell to a position in a row. Figure 1.26 Part of ASIC Design FlowFor an FPGA, placement chooses which o f the fixed logic resources on thechip are used for which logic cells. Floorplanning and placement areclosely related and are sometimes combined in a single CAD tool.Routing makes the connections between logic cells. Routing is a hardproblem by itself is normally split into two distinct steps, called globaland local routing. Global routing determines where the interconnectionsbetween the placed logic cells and blocks will be situated. Only the routesto he used by the interconnections within the wiring areas.Global routing is sometimes called loose routing for this reason. Localrouting joins the logic cells with interconnections. Information on whichinterconnections areas to use comes from the global router. Only at thisstage o f layout d, finally decide on the width, mask layer, and exactlocation of the interconnections local routing is also known as detailedrouting.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 36 
  51. 51. VLSI DESIGN CMOS TECHNOLOGY1.6.2 CAD Tools setsIn order to develop a CAD tool it is necessary to convert each of thephysical do steps to a problem with well-defined goals and objectives. Thegoals for each physical design step are the things to achieve. Theobjectives for each step things to meet goals. Some examples of goals andobjectives for each of the ASIC physical design steps are as explainedbelow,System partitioning• Goal: Partition a system into a number of ASICs.• Objectives: Minimize the number of external connections between theASICs. Keep each ASIC smaller than a maximum size.Floorplanning• Goal: Calculate the sizes of all the blocks and assign them locations.• Objective: Keep the highly connected blocks physically close to eachother.Placement• Goal: Assign the interconnect areas and the location of all the logiccells within the flexible blocks.• Objectives: Minimize the ASIC area and the interconnect density.Global routing• Goal: Determine the location of all the interconnect.• Objective: Minimize the total interconnect area used.Detailed routing• Goal: Completely route all the interconnect on the chip.• Objective: Minimize the total interconnect length used.There i s no magic recipe involved in the choice o f the ASIC physicaldesign steps. These steps have been chosen simply because, as tools andtechniques have developed historically, these steps proved to be theeasiest way to split up the larger problem if ASIC physical design.Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 37 
  52. 52. VLSI DESIGN CMOS TECHNOLOGY1.6.3 Physical Design-The Inverter1.6.4 Physical Design-The NORVerilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 38 
  53. 53. VLSI DESIGN CMOS TECHNOLOGY1.6.5 Physical Design-The NAND1.7 DESIGN STRATEGIESThe economic viability of an IC is in large part affected by the productivitythat can be brought to hear on the design. This in turn depends on theefficiency with which the design may be converted from concept toarchitecture, to logic and memory, to circuit and hence to a physical layout.A good VLSI design system should provide for consistent in all threedescription domains (behavioral, structural and physical) and at all relevantlevels of abstraction (architecture, RTL, logic, circuit). The means by whichthis is accomplished may be measured in various terms that differ inimportance based on the application. These design parameters may besummarized in terms of • Performance-speed, power, function, flexibility. • Size of die (hence cost of die). • Time to design (hence cost of engineering and schedule). • Ease of test generation and testability (hence cost of engineering and schedule).Design is a continuous trade-off to achieve adequate results for all of theabove parameters. As such, the tools and methodologies used for aparticular chip will be a function of these parameters. Certain end resultshave to be met (i.e., the chip must conform to performance specifications),but other constraints may be a function of economics (i.e., size of dieaffecting yield) or even subjectivity (i.e., what one designer finds easy,another might find incomprehensible).Verilog Course Team www.verilogcourseteam.comDream IT, We make U to Deliver                                 39