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Pdh and sdh1 Pdh and sdh1 Presentation Transcript

  • 1PDH and SDHRadio and Transmission Wing
  • 2Content• Introduction to Multiplexing• Asynchronous Network and SynchronousNetwork• PDH multiplexing• SDH multiplexing• Comparison with PDH and SDH
  • 3Introduction to Multiplexing-MultiplexingMultiplexing is the is the set of techniques that allows the simultaneoustransmission of multiple signals across a single data link. View slide
  • 4PCMMuxBasic Multiplexer (PCM MUX)AnalogueSignalDigitalSignalDigital Multiplexer ( Digital MUX)VCH 1VCH nDigitalMuxDigitalSignalDigitalSignalIntroduction to Digital Multiplexing View slide
  • 5• TDM (Time-Division Multiplexing)– is a digital process that can be applied whenthe data rate capacity of the transmissionmedium is greater than the data rate requiredby the sending and receiving device– TDM is a digital multiplexing technique tocombine data.Digital Multiplexing (TDM)
  • 6TDMIn a TDM, the data rate of the link is n times faster, and the unit duration is n times shorter.In a TDM, the data rate of the link is n times faster, and the unit duration is n times shorter.
  • 7Interleaving- InterleavingIt is the process that a single data bit or byte froman I/O port is released to the input of Multiplexer oroutput of multiplexer by a clock pulse.- Types of Interleaving- Bit by Bit InterleavingIt is much simpler because it is independent of framestructure and also requires less memory capacity.- Word by Word InterleavingIt sets some restraints on the frame structure of thetributaries and requires a greater amount of memorycapacity.
  • 8Ways of TDM• TDM can be implemented in two ways– Synchronous TDM– Asynchronous TDM
  • 9Tributaries• In Digital Multiplexer, this is done byinterleaving the bit stream of the inputs.Each individual input bit stream is called aTributary.
  • 10Aggregate
  • 11Synchronous Digital Multiplexer• Synchronous digital multiplexer havetributaries with the same clock frequency,and they are all synchronized to a masterclock.
  • 12Asynchronous Digital Multiplexer• Asynchronous digital multiplexer havetributaries which have the same nominalfrequency ( that means there can be asmall difference from one to another), butthey are not synchronized to each other.
  • 13Justification• In general incoming tributaries haveindependent clocks. The clock rate of atributary and the individual clock rate ofthe multiplexer are not the same. Withoutany precautions, the result will be slip. Slipcan cause lost bits or overlapped bits.• To avoid of this slip, there have a processof justification to justify between differentclocks.
  • 14Types of Justifications• Positive Justification• Negative Justification• Positive Negative Justification orZero Justification
  • 15Positive Justification• Input Tributary clock speed is slower thanthe divided multiplexer clock rate.• The reading process must be sloweddown or put the stuffing bit according tothe justification control bits.
  • 16Negative Justification• Input tributary clock rate is faster thanmultiplexer clock rate. Since we have nocontrol over the channel input information,our only solution must be to speed up thereading process .• This is achieved by reading the bufferduring a control time slot ‘Y’, in addition tothe normal information time slots withinthe frame.
  • 17Zero Justification• It is also called Positive NegativeJustification. Clock speed adaptation isrequired between two nominally equal bitrate with synchronous network.
  • 18PDH• ‘P’ means ‘Plesio” and it is greek name nearly(barely).• Its process is tributary clock speed and tributaryclock speed is allowable limit different. (nearlysame)• ‘D’ means Digital• ‘H’ means ‘Hierarchy (low bandwidth to higherbandwidth)’• Its process works in asynchronous Digitalnetwork and applies positive justification.
  • 19SDH• ‘S’ means ‘Synchronous’• Tributary clock and multiplexer clock mustwork with identical or with the one masterclock.• ‘D’ means ‘Digital’• ‘H’ means ‘Hierarchy (low bandwidth tohigher bandwidth’• Its process works in Synchronous DigitalNetwork and applies zero justification.
  • 20PDH Standards
  • 21European Standard with Input tributaries14034348821403434882140MLTECustomer34 Mbps8 Mbps2 Mbps140MLTE
  • 22The Main Characteristics of 2.048Mb/s(European Standard First Level)Nominal bit rate 2048 kbit/sTolerance 50 ppmLine code HDB3Frame length 256 bitsFrame rate 8000 frames/sBits per time interval 8 bitsMultiplexing method Byte-by-byte
  • 23PCM -30 E1 2.048 Mbps FRAME CONFIGURATIONTIME.SLOT --- 31 0 1 2 3 16 30 31 0 --- ---0 1 2 3 4 5 6 71 Frame ( 125 µ s )1bit 488.28125ns1 Speech Channel 3906.25 ns1Frame = 30 Speech Channels+2 Signalling Channels1 Channel = 8 Bits1 Second =8000 Frame =8000 Single Signal Samples
  • 24European Standard (8.448 Mbps Second Level)SubFrameSignal Number of Bits Bit Numbering1-Alignment Word1111010000-Service bits-Tributary Bits1022001 to 1011 to 1213 to 2122-Justification Control bits-Tributary bits4208213 to 216217 to 4243-Justification Control bits-Tributary bits4208425 to 428429 to 6364-Justification Control bits-Justification bits-Tributary bits44204637 to 640641 to 644645 to 848
  • 251 1 1 1 0 1 0 0 0 0 1 1Frame alignment word /Service bit12 200 4 208 208 44 4 2042122 41 3212 212 212848-100µsTributary bits Tributary bitsTributary bits Tributary bitsJustification bitsJCBJCB=Justification Control bitsJCBNo. of bitsBits/sub frameNo. of bits/frameNo. of sub frameTime for 1 frame8.448 Mbps Frame structure (positive stuffing/justification)
  • 26European Standard (34.368 Mbps Third Level)SubFrameSignal Number of Bits Bit Numbering1-Alignment Word1111010000-Service bits-Tributary Bits1023721 to 1011 to 1213 to 3842-Justification Control bits-Tributary bits4380385 to 388389 to 7683-Justification Control bits-Tributary bits4380769 to 772773 to 11524-Justification Control bits-Justification bits-Tributary bits443761153 to 11561157 to 11601161 to 1536
  • 270 0000 00 11111 █CJ1 CJ2 CJ3 SJc11 c12c31c22c41c32c13c42c21c43c33c23S1S4S3S2C11,C12,C13 = 1,1,1 -------------- S1 is a stuffing bitC21,C22,C23 = 1,0,0 ---------------S2 is an Information bitC31,C32,C33 = 0,0,1 --------------S3 is an information bitC41,C42,C43 = 0,0,0 --------------S4 is an Information BitThe Formation of a Stuffing message word
  • 2834Mbs frame structure (positive stuffing/justification)1 1 1 1 0 1 0 0 0 0 x xFrame alignment word /Service bit12 372 4 380 380 44 4 3763842 41 3384 384 3841536-44.69µsTributary bits Tributary bitsTributary bits Tributary bitsJustification bitsJCBJCB=Justification Control bitsJCBNo. of bitsBits/sub frameNo. of bits/frameNo. of sub frameTime for 1 frame
  • 29European Standard (139.264Mbps FourthLevel)SubFrameSignal Number of Bits Bit Numbering1-Alignment Word111110100000-Service bits(1 for Alarms)-Tributary Bits1244721 to 1213 to 1617 to 4882-Justification Control bits-Tributary bits4484489 to 497493 to 9763-Justification Control bits-Tributary bits4484977 to 980981 to 14644-Justification Control bits-Tributary bits44841465 to 14681469 to 19525-Justification Control bits-Tributary bits44841953 to 19561957 to 24406-Justification Control bits-Justification bits-Tributary bits444802441 to 24442445 to 24482449 to 2928
  • 301 1 1 1 1 0 1 0 0 0 0 0 x x x xFrame alignment word /Service bit16 472 4 484 484 44 4 4804882 61 3488 488 4882928-21.02µsTributary bits Tributary bitsTributary bits Tributary bitsJustification bitsJCBJCB=Justification Control bitsJCBNo. of bitsBits/sub frameNo. of bits/frameNo. of sub frameTime for 1 frame139.264 Mbps Frame Structure(positive stuffing/justification)
  • 31European Standard (565 Mbps fifth level)Sub Frame Signal Number of Bits Bit Numbering1-Alignment Word-Tributary Bits123721 to 1213 to 3842-Justification Control bits-Tributary bits4380385 to 388389 to 7683-Justification Control bits-Tributary bits4380769 to 772773 to 11524-Justification Control bits-Tributary bits43801153 to 11561157 to 15365-Justification Control bits-Tributary bits43801537 to 15401541 to 19206-Justification Control bits-Tributary bits43801921 to 19241925 to 23047-Justification Control bits-Justification bits-Tributary bits443762305 to 23082309 to 23122313 to 2688
  • 32565 Mbps Frame structure (positivestuffing/justification)1 1 1 1 0 1 0 0 0 0 x xFrame alignment word /Service bit12 372 4 380 380 44 4 3764882 61 3488 488 4882928-21.02µsTributary bits Tributary bitsTributary bits Tributary bitsJustification bitsJCBJCB=Justification Control bitsJCBNo. of bitsBits/sub frameNo. of bits/frameNo. of sub frameTime for 1 frame
  • 33ITU recommendations of PDH• G.701– Vocabulary of digital transmission and multiplexing, and pulse code modulation– (PCM) terms• G.702– Digital hierarchy bit rates• G.703– Physical/electrical characteristics of hierarchical digital interfaces• G.704– Synchronous frame structures used at 1544, 6312, 2048, 8448 and 44 736 kbit/s– hierarchical levels• G.705– Characteristics of plesiochronous digital hierarchy (PDH) equipment functional– blocks• G.706– Frame alignment and cyclic redundancy check (CRC) procedures relating to basic– frame structures defined in Recommendation G.704
  • 34LIMITATIONS IN PDH• Different Standards• Systems operates in its own Clock• Proprietary Coding Mechanisms MakingInter-Operas Ability of System BetweenDifferent Vendors• Not Transparent• Protection Schemes are not available• Ring, Hub Configuration not possible
  • 35PDH and SDH comparison• SONET/SDH’s goalsimplify interconnection between network operatorsexpand the compatibility• Imperfection of PDHThree different regional digital hierarchiesRate & Format conversion induces extra high cost to customers• Demanding broadband servicesTo the high speed signals, the processing time for performingconversion between PDH region is not long enough
  • 36SDH benefits• Reduce costssimplified standard interfaceseliminate vendor proprietary interfaces• Integrated network elementsenhanced operations capabilities• Survivabilitygrants upgradability (modularity)• No bandwidth bottlenecks
  • 37MAPPING OF PDH SIGNALINTO SDH SIGNAL
  • 38Multiplexing Structure of PDHSignal into SDH Signal
  • 39500µs32 byte 32 byte 32 byte 32 byte2.048 Mbps to STM-N signal2.048Mbps500µs34 byte 34 byte 34byte 34 byte500µs32 byte 32 byte 32 byte 32 byte500µs32 byte 32 byte 32 byte 32 byte2.048Mbps
  • 40ITU recommendations of SDH/1
  • 41ITU recommendations of SDH/2
  • 42T-1 hierarchy• DS0 64Kbps 1/24 of T-1 1 Channel• DS1 1.544Mbps 1 T-1 24 Channels• DS1C 3.152 Mbps 2 T-1 48 Channels• DS2 6.312 Mbps 4 T-1 96 Channels• DS3 44.736 Mbps 28 T-1 672 Channels• DS3C 89.472 Mbps 56 T-1 1344 Channels• DS4 274.176 Mbps 168 T-1 4032 Channels
  • 43• The fundamental frame of T1 is shown in figure• s = framing bit1 frame = 193 bits (192 data +1 framing ) 125µsTime slot 24---Time slot 2Time slot 187---8765432187654321sData bitsThe 1.544 Mbps Frame format
  • 44-43210-4321-4321F0C4X-43210-4321-43211F0C3M1-43210-4321-43211F0C2M1-43210-4321-43210F0C1M0-49 bitsmicroframe_____________ 294bits43211-4321-4321F1C4C4-43211-4321F1C3C3-43211-4321-4321F1C2C2-43211-4321-4321F1C1C1Time slot available for stuffed bitsSub frames ___________Master frame 1176 bits = 294 bits/sub frame X 4The 6.312 Mbps frame format
  • 45The 274.176 Mbps frame format96 bits microframe1 0 F1F10 1 P2P21 0 P1P1Sub frame 1 (196 bits) Sub frame 2 Sub frame 3X1 X1 P2P2X2 X2P1P1X2 X2P2P2Sub frame 4 Sub frame 5 Sub frame 6C1 C1 P1P1C2 C2P2P2C3 C3P1P1Sub frame 7 Sub frame 8 Sub frame 9C4 C4 P2P2C5 C5P1P1C6 C6P2P2Sub frame 8 Sub frame 9 Sub frame 9C7 C7 P1P1C8 C8P2P2C9 C9P1P1Sub frame 10 Sub frame 11 Sub frame 12C10C10P2P2C11C11P1P1P2P2Sub frame 13 Sub frame 14 Sub frame 15C13C13P1P1P2P2P1P1Sub frame 19 Sub frame 20 Sub frame 21C16C16P2P2C17C17P1P1C18C18P2P2Sub frame 22 Sub frame 23 Sub frame 24
  • 460410010Sub frame 7F1C7F0C7F0C7F110011Sub frame 6F1C6F0C6F0C6F1M11001Sub frame 5F1C5F0C5F0C5F1M01001Sub frame 4F1C4F0C4F0C4F1P031001Sub frame 3F1C3F0C3F0C3F1P021001Sub frame 2F1C2F0C2F0C2F1X011001Sub frame 1F1C1F0C1F0C1F1X01,02,03,04,05,06,07 are time slots available for stuffed bits85 bitMicroframe680 bit Sub frame050The 44.736 Mbps Frame format
  • 47The ADPCM difference principleCOMPARATOR Resultingdigital outputTraffic Input(8 bits word)Estimate(8 bits word)
  • 48ADPCM encoderNon-uniform touniform PCMconverterAdaptive levelQuantizerInverseAdaptiveQuantizerAdaptivePredictor64 kbpsinputdifferencesignalquantizeddifferencesignalReconstructedsignal32 KbpsoutputSignalEstimate+++-
  • 49CS ACELP encoderAdaptationcodebookAlgebraiccodebookVQ gaincodebookHighpassLPC analysisLSP Quantizer1/A(z)SynthesisfilterPerceptualweighting filterMinimumerrorGainadaptorAdaptivegainindexindexindexindex+++-inputspeech output
  • 50Cs-acelp decoder-LPC LSP1/A(z)SynthesisfilterGainadaptorAdaptivegainVQ gain codebook++inputPost filterOutputspeech
  • 51clockHigh StabilityOscillatorMasterclockTimingLogic----1 2 3 ------- n
  • 52The basic principles of TDMMultiplexchanneltimeslotChannel 1Channel 2Channel 3Channel 4Channel n
  • 53TIMEMultiplexed chn- - - -4321n- - - - -4321Timing signal nnnTiming signal 444Timing signal 333Timing signal 222Timing signal 111Time slot dedicated to channel 3The basic principles of TDM
  • 54Х 30(n=30)ch1Ch nХ 30(n=30)ch1Ch nХ 30(n=30)ch1Ch nХ 30(n=30)ch1Ch nХ 4 Х 4 Х 4 Х 42.048 MbpsCh 1Ch 2Ch 3Ch 4Ch 2Ch 3Ch 4Ch 2Ch 3Ch 48.448 MbpsCh 1139.264 MbpsCh 1565.992MbpsDigital Hierarchy CCITT Europe standard
  • 55Х 4MULTIPLEXER2.048 Mbps ± 50ppm2.048 Mbps ± 50ppm2.048 Mbps ± 50ppm2.048 Mbps ± 50ppmMUXoutputDigital Multiplexer
  • 56Tributary 1Tributary 2Tributary 3Tributary 4A/DclockD/D D/DclockD/AFrameAlignmentSelectorFrameAlignmentControlTribTribTribTribDeClockRegeneratorThe Frame Alignment Principle
  • 57123412341234TributaryinformationFramealignment8481Example of a higher order of TDM time frame
  • 58Tx Rx Tx Rx Tx RxPRBS- Tx 1 PRBS- Rx 1PRBS- Tx 2PRBS- Rx 2PRBS- Tx 3PRBS- Rx 3A (A (A (Location A Location B Location C Location D) B ( ) C (end to end (location A to D) P(e) = 10-10if there is no jitterend to end (location A to D) P(e) = 10-5if one section is faded toPr(e) = 10-5or the system end to end jitter is excessiveFig P(e) EVALUATION OF A THREE SECTION RADIO SYSTEM