FPGA Introduction
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FPGA Introduction

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field programmable gate array

field programmable gate array

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  • FPGAs are programmable semiconductor devices that are based around a matrix of Configurable Logic Blocks (CLBs) connected through programmable interconnects. As opposed to Application Specific Integrated Circuits (ASICs), where the device is custom built for the particular design, FPGAs can be programmed to the desired application or functionality requirements.
  • Although One-Time Programmable (OTP) FPGAs are available, the dominant type are SRAM-based which can be reprogrammed as the design evolves.
  • FPGAs have evolved far beyond the basic capabilities present in their predecessors, and incorporate hard (ASIC type) blocks of commonly used functionality such as RAM, clock management, and DSP. The following are the basic components in an FPGA:.
  • The CLB is the basic logic unit in a FPGA. Exact numbers and features vary from device to device, but every CLB consists of a configurable switch matrix with 4 or 6 inputs, some selection circuitry (MUX, etc), and flip-flops. The switch matrix is highly flexible and can be configured to handle combinatorial logic, shift registers or RAM. More architectural details can be found in the applicable device’s data sheet.
  • While the CLB provides the logic capability, flexible interconnect routing routes the signals between CLBs and to and from I/Os. Routing comes in several flavors, from that designed to interconnect between CLBs to fast horizontal and vertical long lines spanning the device to global low-skew routing for Clocking and other global signals. The design software makes the interconnect routing task hidden to the user unless specified otherwise, thus significantly reducing design complexity.
  • Today’s FPGAs provide support for dozens of I/O standards thus providing the ideal interface bridge in your system. I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards. Today’s leading FPGAs provide over a dozen I/O banks, thus allowing flexibility in I/O support.
  • Embedded Block RAM memory is available in most FPGAs, which allows for on-chip memory in your design. These allow for on-chip memory for your design. Xilinx FPGAs provide up to 10Mbits of on-chip memory in 36kbit blocks that can support true dual-port operation.
  • Digital clock management is provided by most FPGAs in the industry (all Xilinx FPGAs have this feature). The most advanced FPGAs from Xilinx offer both digital clock management and phase-looped locking that provide precision clock synthesis combined with jitter reduction and filtering.
  • Xilinx offers the broadest lineup of FPGAs providing advance features, low-power, high-performance, and high value for any FPGA design. Below is an overview of Xilinx leading FPGA families.
  • Due to their programmable nature, FPGAs are an ideal fit for many different markets. As the industry leader, Xilinx provides comprehensive solutions consisting of FPGA devices, advanced software, and configurable, ready-to-use IP cores for market and applications such as:

FPGA Introduction FPGA Introduction Presentation Transcript

  • FPGA By :- Kamlesh Kumar
  • WHAT IS A FPGA? Field Programmable Gate Array (FPGA)
  • Programmability Three programming methods:- 1. SRAM –Based (Xilinx, Altera) 2. Antifuse Technology (Actel, Quicklogic) 3. EPROM/EEPROM
  •  FPGAs allow designers to change their designs very late in the design cycle– even after the end product has been manufactured and deployed in the field. In addition, Xilinx FPGAs allow for field upgrades to be completed remotely, eliminating the costs associated with re-designing or manually updating electronic systems
  • FPGA Block Structure
  •  Configurable Logic Blocks (CLBs)  Interconnect  Select I/O (IOBs)  Memory  Complete Clock Management Common FPGA Features
  •  Primary resources for design Combinational functions Flip flops  CLB contains two slice  Connected to switch matrix for routing to other FPGA resources  Carry chain runs in vertically in a column from one slice to the one above Configurable Logic Blocks (CLBs)
  •  Two type of slices SLICEM:- Full Slice  LUT can be used for logic and memory/SRL  Has wide MUX and carry chain SLICEL:- logic and arithmetic slice  LUT can only be used for logic(Not memory)  Has wide MUX and carry chain
  •  FPGA Slice Resource  Four six-input look-up table  Wide MUX  Carry chain  Four Flip-flop/latches  Four addition Flip-flops
  • Basic Configurable Logic Block Structure
  •  The design software makes the interconnect routing task hidden to the user unless specified otherwise, thus significantly reducing design complexity.  XADC  AMS Interconnect
  •  I/O in FPGAs is grouped in banks with each bank independently able to support different I/O standards Select I/O (IOBs)
  • Basic Select I/O (IOBs) Structure
  •  Block RAM/FIFO  Fully Synchronous operation  Optional internal pipeline register for higher frequency operation.  Two independent port access common data Individual address, clock, write enable , clock enable  Multiple configuration option True dual-port, Simple dual-port, Single port Memory
  •  Global Clock Buffer(BUFG)  Vertical spins  Global clock network  BUFIO  i/o clock network Complete Clock Management
  • Xilinx FPGAs
  • By Market By Technology Aerospace and Defense Industrial Audio Automotive Medical Security Broadcast Wireless Communications Video and Imaging Consumer Electronics Wired Communications High Performance Computing FPGA Applications