Kai semi - Automated FPGA to ASIC Conversion expert
Automated FPGA to ASIC Conversion Experts<br />
FPGA to ASIC, <br />ASIC to ASIC,<br />DSP to ASIC<br />AUTOMATED<br />CONVERSIONs<br />
About <br />Kaisemi is a fabless semiconductor vendor providing reduced-cost chip replacements<br />KaiSemi is well established with FAB relationships<br />KaiSemi relies on a strong and firm financial footing of Kai-Tek Group and a massive proven successful conversion experience.<br />KaiSemi is focused on Automated conversion flow.<br />
Team<br /><ul><li>The KaiSemi team is built from experts, with vast experience in FPGAs & ASIC conversion projects, and full ASIC productization flow.
The team members have an experience of over 500 successful FPGAs & ASIC conversions. </li></li></ul><li>Why replace FPGA by ASIC ?<br /><ul><li>Cost reduction.
Performance-per-Cost Boost </li></li></ul><li>Auto tools:<br /> Exclusive In-House Automated set of tools convert FPGA-to-ASIC directly from netlist<br /> Automated tools converting any size of FPGA<br /> Wide variety of FAB libs optimizing cost and power, per design<br />
Netlist Conversion Concept<br /> Fast ASIC flow cycle<br /> No RTL touch: <br />ensures Quality and Guarantee<br /> Automated Gate level<br /> No intervention needed by the customer <br />
Multi FPGAsPeripherals to an ASIC<br /> into a single-die replacement<br /> or<br /> into a multi-die single package replacement <br />
End Of Life ASIC to ASIC<br /> Full Turnkey replacement without customer intervention<br /> Same business model of Functional Guarantee and “No NRE”<br />
Summary Discussion<br />Functionality Guaranteed (No Good No Pay!), because:<br />No RTL touch ! Functional source code is untouched. <br />Using ONLY the Netlist outcome of the proven working FPGA. <br />Proven in-house semi-automated developed conversion tool with experience limits human errors<br />No NRE Payment (No Risk), because: <br />Our business model is targeted to ease on the customer. Based on minimum quantity ordering.<br />Fastest cycle-time, because: <br />Shortening ASIC flow cycle by using automated process and by starting, higher, from netlist stage<br />Limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations.<br />Having well established coherent work flow with FABs.<br />Minimum customer intervention (Fire & Forget), because:<br /> Customer is required to provide 2 main receivables: <br />The FPGA netlist <br />A verification test vectors. <br />From that point on we proceed in posted mode, performing the whole ASIC process until providing a final working chip. <br />Any size FPGA, because:<br />KaiSemi conversion tool deals with any size and any type of FPGA with No limit on netlist size.<br />