Kai semi - Automated FPGA to ASIC Conversion expert


Published on

Functionality Guaranteed (No Good No Pay!),
No NRE Payment (No Risk),
Fastest cycle-time
Minimum customer intervention (Fire & Forget)
Any size FPGA

Published in: Technology
  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

Kai semi - Automated FPGA to ASIC Conversion expert

  1. 1. Automated FPGA to ASIC Conversion Experts<br />
  2. 2. FPGA to ASIC, <br />ASIC to ASIC,<br />DSP to ASIC<br />AUTOMATED<br />CONVERSIONs<br />
  3. 3. About <br />Kaisemi is a fabless semiconductor vendor providing reduced-cost chip replacements<br />KaiSemi is well established with FAB relationships<br />KaiSemi relies on a strong and firm financial footing of Kai-Tek Group and a massive proven successful conversion experience.<br />KaiSemi is focused on Automated conversion flow.<br />
  4. 4. Team<br /><ul><li>The KaiSemi team is built from experts, with vast experience in FPGAs & ASIC conversion projects, and full ASIC productization flow.
  5. 5. The team members have an experience of over 500 successful FPGAs & ASIC conversions. </li></li></ul><li>Why replace FPGA by ASIC ?<br /><ul><li>Cost reduction.
  6. 6. Power saving.
  7. 7. Secure fromcopy.
  8. 8. No Flash/EPROM Need .
  9. 9. NoPower-up Time.
  10. 10. EMI decreasing.
  11. 11. Performance-per-Cost Boost </li></li></ul><li>Auto tools:<br /> Exclusive In-House Automated set of tools convert FPGA-to-ASIC directly from netlist<br /> Automated tools converting any size of FPGA<br /> Wide variety of FAB libs optimizing cost and power, per design<br />
  12. 12. Netlist Conversion Concept<br /> Fast ASIC flow cycle<br /> No RTL touch: <br />ensures Quality and Guarantee<br /> Automated Gate level<br /> No intervention needed by the customer <br />
  13. 13. KaiSemi flow<br />Traditional flow<br />FPGARTL<br />FPGA Netlist<br />RTL fit to ASIC<br />Functional Simulation<br />Exclusive Workflow<br />Full ASIC Synthesis<br />KaiSemi<br />in-house tools<br />Timing + Functional Simulation<br />DFT insertions<br />ASIC Netlist<br />Layout P&R<br />Timing + Functional Simulation<br />FAB hand-off<br />
  14. 14. Full turnkey solution: <br />From FPGA stage to Chip replacement production<br />Automated Conversion with Full ASIC flow<br />Well established infrastructure with FAB houses<br />
  15. 15. Drop-in replacement: <br />Fully compatible: Pin-to-Pin 2nd source<br />or<br />Functional compatible : reduced package<br />
  16. 16. Exclusivity<br />
  17. 17. Business model <br />
  18. 18. Multi FPGAsPeripherals to an ASIC<br /> into a single-die replacement<br /> or<br /> into a multi-die single package replacement <br />
  19. 19. End Of Life ASIC to ASIC<br /> Full Turnkey replacement without customer intervention<br /> Same business model of Functional Guarantee and “No NRE”<br />
  20. 20. Summary Discussion<br />Functionality Guaranteed (No Good No Pay!), because:<br />No RTL touch ! Functional source code is untouched. <br />Using ONLY the Netlist outcome of the proven working FPGA. <br />Proven in-house semi-automated developed conversion tool with experience limits human errors<br />No NRE Payment (No Risk), because: <br />Our business model is targeted to ease on the customer. Based on minimum quantity ordering.<br />Fastest cycle-time, because: <br />Shortening ASIC flow cycle by using automated process and by starting, higher, from netlist stage<br />Limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations.<br />Having well established coherent work flow with FABs.<br />Minimum customer intervention (Fire & Forget), because:<br /> Customer is required to provide 2 main receivables: <br />The FPGA netlist <br />A verification test vectors. <br />From that point on we proceed in posted mode, performing the whole ASIC process until providing a final working chip. <br />Any size FPGA, because:<br />KaiSemi conversion tool deals with any size and any type of FPGA with No limit on netlist size.<br />