• Share
  • Email
  • Embed
  • Like
  • Save
  • Private Content
Kai semi  - Automated FPGA to ASIC Conversion expert
 

Kai semi - Automated FPGA to ASIC Conversion expert

on

  • 924 views

Functionality Guaranteed (No Good No Pay!),

Functionality Guaranteed (No Good No Pay!),
No NRE Payment (No Risk),
Fastest cycle-time
Minimum customer intervention (Fire & Forget)
Any size FPGA

Statistics

Views

Total Views
924
Views on SlideShare
923
Embed Views
1

Actions

Likes
0
Downloads
10
Comments
0

1 Embed 1

http://www.slashdocs.com 1

Accessibility

Categories

Upload Details

Uploaded via as Microsoft PowerPoint

Usage Rights

© All Rights Reserved

Report content

Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
  • Full Name Full Name Comment goes here.
    Are you sure you want to
    Your message goes here
    Processing…
Post Comment
Edit your comment

    Kai semi  - Automated FPGA to ASIC Conversion expert Kai semi - Automated FPGA to ASIC Conversion expert Presentation Transcript

    • Automated FPGA to ASIC Conversion Experts
    • FPGA to ASIC,
      ASIC to ASIC,
      DSP to ASIC
      AUTOMATED
      CONVERSIONs
    • About
      Kaisemi is a fabless semiconductor vendor providing reduced-cost chip replacements
      KaiSemi is well established with FAB relationships
      KaiSemi relies on a strong and firm financial footing of Kai-Tek Group and a massive proven successful conversion experience.
      KaiSemi is focused on Automated conversion flow.
    • Team
      • The KaiSemi team is built from experts, with vast experience in FPGAs & ASIC conversion projects, and full ASIC productization flow.
      • The team members have an experience of over 500 successful FPGAs & ASIC conversions.
    • Why replace FPGA by ASIC ?
      • Cost reduction.
      • Power saving.
      • Secure fromcopy.
      • No Flash/EPROM Need .
      • NoPower-up Time.
      • EMI decreasing.
      • Performance-per-Cost Boost
    • Auto tools:
      Exclusive In-House Automated set of tools convert FPGA-to-ASIC directly from netlist
      Automated tools converting any size of FPGA
      Wide variety of FAB libs optimizing cost and power, per design
    • Netlist Conversion Concept
      Fast ASIC flow cycle
      No RTL touch:
      ensures Quality and Guarantee
      Automated Gate level
      No intervention needed by the customer
    • KaiSemi flow
      Traditional flow
      FPGARTL
      FPGA Netlist
      RTL fit to ASIC
      Functional Simulation
      Exclusive Workflow
      Full ASIC Synthesis
      KaiSemi
      in-house tools
      Timing + Functional Simulation
      DFT insertions
      ASIC Netlist
      Layout P&R
      Timing + Functional Simulation
      FAB hand-off
    • Full turnkey solution:
      From FPGA stage to Chip replacement production
      Automated Conversion with Full ASIC flow
      Well established infrastructure with FAB houses
    • Drop-in replacement:
      Fully compatible: Pin-to-Pin 2nd source
      or
      Functional compatible : reduced package
    • Exclusivity
    • Business model
    • Multi FPGAsPeripherals to an ASIC
      into a single-die replacement
      or
      into a multi-die single package replacement
    • End Of Life ASIC to ASIC
      Full Turnkey replacement without customer intervention
      Same business model of Functional Guarantee and “No NRE”
    • Summary Discussion
      Functionality Guaranteed (No Good No Pay!), because:
      No RTL touch ! Functional source code is untouched.
      Using ONLY the Netlist outcome of the proven working FPGA.
      Proven in-house semi-automated developed conversion tool with experience limits human errors
      No NRE Payment (No Risk), because:
      Our business model is targeted to ease on the customer. Based on minimum quantity ordering.
      Fastest cycle-time, because:
      Shortening ASIC flow cycle by using automated process and by starting, higher, from netlist stage
      Limiting the need for customers cycles of RTL flow, synthesis, verifications and back-annotations.
      Having well established coherent work flow with FABs.
      Minimum customer intervention (Fire & Forget), because:
      Customer is required to provide 2 main receivables:
      The FPGA netlist
      A verification test vectors.
      From that point on we proceed in posted mode, performing the whole ASIC process until providing a final working chip.
      Any size FPGA, because:
      KaiSemi conversion tool deals with any size and any type of FPGA with No limit on netlist size.