My Presentation Park Lay


Published on

work career and training

  • Be the first to comment

  • Be the first to like this

No Downloads
Total views
On SlideShare
From Embeds
Number of Embeds
Embeds 0
No embeds

No notes for slide

My Presentation Park Lay

  1. 1. Profile Career & Contribution Artist Kevin Park Slide 1 Goal & Passion Oct 07, 2009
  2. 2. Personal Profile • Keen eye for detail since any mistakes are able to be a large loss of costs • B.Sc. degree- Electronics engineering background, with a deep understanding of semiconductor and design experience and technology concept • Knowledge of design methodology and strong debugging • Various products with Qimonda, Hynix, Enable, Nanya, Sony and ST micro • Experience in various tools and familiar with software for design and verification • Documentation & Report Physical Design Career Path Circuit Design Electronics Circuit Physical Physical Engineering Design Design Design Ulsan Univ. Hynix Semi. Enable Semi. Qimonda AG M. Service Korea Taiwan Munich 1989 1996 1999 2003 2004 09.2004 04.2009 Slide 2 Goal & Passion Oct 07, 2009
  3. 3. Background • Easily adaptable to a fast pace, rapidly growing environment • Passion to learn and work with new technologies • Diligent, open-minded and positive • Working under pressure is easy for me, enjoy taking the initiative • Flexible and innovative in problem solving, results oriented • Feel at home in an international work environment incl. remote teams • Strong international background and experience in interacting with different cultures • Strong time management skills • Good communication and teamwork skills Slide 3 Goal & Passion Oct 07, 2009
  4. 4. Detail Engineering history • Sept.2004~Mar.2009 Qimonda AG (Memory) – Senior Physical design  Responsibility: Physical Design, Generator Expert Leader Worldwide & Design Methodology • Generator Layout expert and worldwide Speaker (Leader) in Munich, US and China • Physical design over all analog/generator system from 90nm to 45nm technology • Local Group Leader for design methodology • Full chip verification for Graphics DRAM, DDR3,DDR2, DDR1 SDRAM • Experience as a Mentor and Trainer of physical design team  Achievement Excellent Senior Engineer Award, new verification method, time reduction for design Best Product Award and mass product worldwide Slide 4 Goal & Passion Oct 07, 2009
  5. 5. Detail Engineering history • Jan.2004~ Jul.2004 Enable Semiconductor – Senior Physical design  Responsibility : Physical Design Coordinator, Software development • Physical Design Coordinator • Analog/mixed signal layout for Pseudo SRAM and Low Power SDRAM • Created verification rule decks using Synopsys Hercules and Mentor Graphics Calibre  Achievement New tools’ evaluation and setting up, software development in new environment - Synopsys Hercules and Mentor Graphics Calibre as an administrator and Pilot-User - Cadence Skill programming Slide 5 Goal & Passion Oct 07, 2009
  6. 6. Detail Engineering history • Feb.1996~Dec.2003 Hynix Semiconductor – Circuit & Physical design  Responsibility : Circuit Design, Physical Design and Design Methodology • I. Circuit Design • Simulation of Analog/mixed signal, Power Generator, Cell core and Full chip simulation • Timing and signal integrity analysis for SRAM ,DDR1 and SDRAM • Failure Analysis and Test measurement, Signal Integrity • Chip architecture, Floor plan and Parasitic RC-extraction • II. Physical Design • Layout Coordinator, Analog/mixed signal Core and Periphery layout • Chip architecture, Floor plan for Graphics DRAM, DDR1, SDRAM and Flash • Created rule decks for the verification (Calibre, Hercules and Assura ) • Layout Auto Place & Rout, Physical Design Methodology  Achievement Time and costs reduction min. 20% in the field of design Created In-House Tool for design automation, Distinguished Design Automation Award, Best Product Award and mass product Slide 6 Goal & Passion Oct 07, 2009
  7. 7. Training & Others • I. Training • IC-Compiler: Synopsys in Munich (03.2008) • Semiconductor Process: University Bundeswehr Mü nchen in Munich (10.2004) • Cadence software SKILL: Cadence in Seoul (04.1998) • Programming training: Mentor Graphics Calibre and Synopsys Hercules in Seoul (03.1997) • Semiconductor Design and Process: KAIST University in Daejeon (08.1996) • Intensive German course (05.2009 ~ 08.2009), German course (02.2005 ~ 09.2005) • Japanese course (01.1997 ~ 06.1997) • II. Language • Korean (mother tongue), English (fluent), German (intermediate), Japanese (basic) • III. Patent & Other experience • 2 US patents and 12 KR patents • MS Office, Unix, FrameMaker, Visio, SKILL, Software of Synopsys, Cadence and Mentor Graphics, HSPICE, HSIM, STAR-RCXT, EPIC, Nano-SIM, C/C++ and Perl Slide 7 Goal & Passion Oct 07, 2009
  8. 8. Expected Contribution 1. Efficient Analog/Mixed signal simulation and highest quality layout 2. Semi-custom layout of digital circuit and verification 3. Fail Analysis and strong debugging, test measurement 4. Cost & time reduction, design flow development and software improvement 5. New design methodology for circuit and layout design 6. Contribution with strong electrical engineering background 7. Documentation, presentation and requirement feedback 8. I do more Slide 8 Goal & Passion Oct 07, 2009
  9. 9. Danke Schö n We love what we do because we do what we love. Slide 9 Goal & Passion Oct 07, 2009