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S emb t7-arch_bus

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  • 1. Maths is not everything Embedded Systems 4 - Hardware Architecture CPU Input/Output mechanisms Memory Buses and Aux I/O Input/Output interfaces RMR©2012 Power Management
  • 2. Maths is not everything CPU Buses RMR©2012
  • 3. CPU bus Connects CPU to: memory; devices. Maths is not everything RMR©2012 3 © 2008 Wayne Wolf Protocol controls communication between entities.
  • 4. Bus protocol Determines who gets to use the bus at any particular time. Maths is not everything RMR©2012 4 © 2008 Wayne Wolf Governs length, style of communication.
  • 5. Four-cycle handshake Basis of many bus protocols. Uses two wires: enq (enquiry); ack (acknowledgment). Maths is not everything RMR©2012 © 2008 Wayne Wolf enq dev1 data ack dev2
  • 6. Four-cycle example enq 1 3 2 data 4 Maths is not everything RMR©2012 © 2008 Wayne Wolf ack time
  • 7. Typical bus signals Maths is not everything RMR©2012 © 2008 Wayne Wolf Clock. R/W’: true when bus is reading. Address: a-bit bundle. Data: n-bit bundle. Data ready’.
  • 8. Timing diagrams one rising A zero falling 10 ns stable B changing Maths is not everything RMR©2012 © 2008 Wayne Wolf C time
  • 9. Typical bus timing for read CPU: set R/W’=1; asserts address, address enable. Memory: Maths is not everything RMR©2012 © 2008 Wayne Wolf asserts data; asserts data ready’. CPU: deasserts address, address enable.
  • 10. Bus read state diagram Get data Done Maths is not everything RMR©2012 © 2008 Wayne Wolf See ack Adrs Wait
  • 11. Transaction types Wait state: state in a bus transaction to wait for acknowledgment. Disconnected transfer: bus is freed during wait state. Burst: Maths is not everything RMR©2012 © 2008 Wayne Wolf multiple transfers.
  • 12. Maths is not everything Auxiliary Mechanisms Timers RMR©2012
  • 13. Timers and counters Very similar: a timer is incremented by a periodic signal; a counter is incremented by an asynchronous, occasional signal. Maths is not everything RMR©2012 © 2008 Wayne Wolf Rollover causes interrupt.
  • 14. Timers The main applications of timers are to: generate events of fixed time-period allow periodic wakeup from sleep of the device count transitional signal edges replace delay loops allowing the CPU to sleep between operations, consuming less power maintain synchronization clocks Maths is not everything RMR©2012 14
  • 15. Timers (MSP430) System timing is fundamental for real-time applications The MSP430F2274 has 2 timers, namely Timer_A and Timer_B The timers may be triggered by internal or external clocks Maths is not everything RMR©2012 Timer_A and Timer_B also include multiple independent capture/compare blocks that are used for applications such as timed events and Pulse Width Modulation (PWM)
  • 16. Timers (MSP430) - TxCTL Control Register 15 14 13 12 11 10 (Used by Timer_B) Bit 9 8 TxSSELx 7 6 IDx 5 4 MCx 3 2 1 0 - TxCLR TxIE TxIFG Description 9-8 0 0 ⇒ TxCLK 0 1 ⇒ ACLK 1 0 ⇒ SMCLK 1 1 ⇒ INCLK IDx Clock signal divider: 00⇒/1 01⇒/2 10⇒/4 11⇒/8 5-4 MCx Clock timer operating mode: 0 0 ⇒ Stop mode 0 1 ⇒ Up mode 1 0 ⇒ Continuous mode 1 1 ⇒ Up/down mode 2 TxCLR Timer_x clear when TxCLR = 1 1 TxIE Timer_x interrupt enable when TxIE = 1 0 RMR©2012 Timer_x clock source: 7-6 Maths is not everything TxSSELx TxIFG Timer_x interrupt pending when TxIFG = 1
  • 17. Timers (MSP430) - 4 Modes of Operation Timer reset by writing a 0 to TxR Clock timer operating modes: MCx Mode Description 00 Up The timer repeatedly counts from 0x0000 to the value in the TxCCR0 register. 10 Continuous The timer repeatedly counts from 0x0000 to 0xFFFF. 11 RMR©2012 The timer is halted. 01 Maths is not everything Stop Up/down The timer repeatedly counts from 0x0000 to the value in the TxCCR0 register and back down to zero.
  • 18. Timers (MSP430) - Timer Modes Up Mode Continuous Mode Maths is not everything RMR©2012 Up/Down Mode
  • 19. Timers (MSP430): Timer_A Example Use Timer A to interrupt every 1 ms SMCLK .set TIME_1MS .set 1200000 1000 TA_CTL TA_FREQ TASSEL_2+ID_0+MC_1+TAIE ; SMCLK, /1, UP, IE SMCLK/TIME_1MS ; clocks / 1 ms .set .set clr.w mov.w mov.w bis.w jmp Maths is not everything RMR©2012 &TAR #TA_CTL,&TACTL #TA_FREQ,&TACCR0 #LPM0+GIE,SR $ ; 1200000 clocks / second ; 1 ms = 1/1000 s ; ; ; ; ; reset timerA set timerA control reg set interval (frequency) enter LPM0 w/interrupts will never get here! TA_isr: ; timer A ISR bic.w #TAIFG,&TACTL ; acknowledge interrupt ; <<add interrupt code here>> reti .sect .word ".int08" TA_isr ; timer A section ; timer A isr
  • 20. Watchdog timer Watchdog timer is periodically reset by system timer. If watchdog is not reset, it generates an interrupt to reset the host. interrupt Maths is not everything RMR©2012 © 2008 Wayne Wolf host CPU reset watchdog timer
  • 21. Watchdog Timer (MSP430) The primary function of the watchdog timer+ (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. Maths is not everything RMR©2012 If the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals.
  • 22. Watchdog Timer (MSP430) Features of the watchdog timer+ module include: Four software-selectable time intervals Watchdog mode Interval mode Access to WDT+ control register is password protected Control of RST/NMI pin function Selectable clock source Maths is not everything Can be stopped to conserve power Clock fail-safe feature RMR©2012
  • 23. Watchdog Timer (MSP430) - Watchdog Power-up After a power-up clear (PUC), the WDT+ module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK. The user must setup or halt the WDT+ prior to the expiration of the initial reset interval. Maths is not everything RMR©2012
  • 24. Watchdog (MSP430) example: stoping it In Assembly RESET: ! mov.w ! mov.w ! bis.b ! mov.w ... In C Maths is not everything RMR©2012 passwd = 0x5A #0x0300,SP #WDTPW+WDTHOLD,&WDTCTL #0x0f,&P1DIR #0,r14 ; Initialize stack pointer ; Stop WDT ; Set P1.0-3 output
  • 25. Maths is not everything Auxiliary I/O Buttons & Displays RMR©2012
  • 26. Switch debouncing Maths is not everything RMR©2012 © 2008 Wayne Wolf A switch must be debounced to multiple contacts caused by eliminate mechanical bouncing:
  • 27. Encoded keyboard An array of switches is read by an encoder. N-key rollover remembers multiple key depressions. Maths is not everything RMR©2012 © 2008 Wayne Wolf row
  • 28. LED Maths is not everything RMR©2012 © 2008 Wayne Wolf Must use resistor to limit current:
  • 29. Maths is not everything Auxiliary I/O DAC & ADC RMR©2012
  • 30. Digital-to-analog conversion Use resistor tree: R bn bn-1 Maths is not everything RMR©2012 © 2008 Wayne Wolf bn-2 bn-3 2R 4R 8R Vout
  • 31. Flash A/D conversion N-bit result requires 2n comparators: Vin Maths is not everything RMR©2012 © 2008 Wayne Wolf encoder ...
  • 32. Dual-slope conversion Use counter to time required to charge/ discharge capacitor. Charging, then discharging eliminates nonlinearities. Maths is not everything RMR©2012 © 2008 Wayne Wolf Vin timer
  • 33. Sample-and-hold Required in any A/D: Maths is not everything RMR©2012 © 2008 Wayne Wolf Vin converter