High Speed Electrical Testing  Jim Choate Intel Corporation
Agenda <ul><li>Electrical Testing Goals </li></ul><ul><li>Test Modes </li></ul><ul><li>Electrical Testing Procedures </li>...
Goals of the Electrical Compliance Program <ul><li>High Quality USB Products </li></ul><ul><li>Stable, Repeatable, Well Do...
New Testing Areas <ul><li>Electricals </li></ul><ul><ul><li>High Speed Signal Quality </li></ul></ul><ul><ul><li>Time Doma...
USB HS Electrical Test Modes <ul><li>High-speed Capable Devices/Hubs Must Support Test Modes  </li></ul>
General HS Electrical Test Procedure <ul><li>Connect Device Under Test To Test Port on Fixture </li></ul><ul><li>Configure...
New Test Fixture(s) <ul><li>Signal Quality </li></ul><ul><li>TDR </li></ul><ul><li>Receiver Sensitivity </li></ul><ul><li>...
New Test Fixture(s) High Speed Device Signal Quality Test Fixture Test Port Init Port To Host  Controller To Device  Under...
HS Signal Quality Test Procedure <ul><li>Put Device in Test Mode Test_Packet </li></ul><ul><ul><li>Flip Test Fixture Relay...
Eye Pattern Generation <ul><li>Time vs. voltage test packet data is transferred from scope to PC through GPIB </li></ul>
Eye Pattern Generation <ul><li>Signal analysis scripts determine data rate from zero volt crossovers  </li></ul><ul><ul><l...
Eye Pattern Generation <ul><li>Reference frame position is optimized by minimizing least squares error between reference f...
Eye Pattern Generation <ul><li>Data is parsed into bit time internals using optimized reference frame </li></ul><ul><li>Ey...
Passing Eye Pattern <ul><li>Example of passing High Speed Eye - Host Controller at TP2 </li></ul>
Failing Eye Patterns <ul><li>Min/Max voltage level failure </li></ul><ul><li>Caused by out of spec HS termination </li></u...
HS Device Receiver Sensitivity and Squelch Test Procedure <ul><li>DUT is Placed In Test_SEO_NAK Test Mode using Test Mode ...
HS Device Receiver Sensitivity and Squelch Test Results <ul><li>Device response to nominal packets </li></ul><ul><li>Devic...
TDR Test Procedure <ul><li>Device Under Test Placed In Test_SEO_NAK Mode </li></ul><ul><li>Relay Switches Idle Data Lines ...
TDR Test Procedure <ul><li>Determining connector reference location </li></ul><ul><ul><li>TDR connected to test fixture </...
TDR Test Procedure <ul><li>Measuring TDR response </li></ul>ZHSTHRU 70 to 110 Ohms (red cursors) ZHSTERM 80 to 100 Ohms (y...
TDR Test Procedure <ul><li>TDR Test Fails </li></ul><ul><ul><li>Cause: Using a ribbon cable between the PCB & USB connecto...
Other Test Modes <ul><li>Test_J & Test_K </li></ul><ul><ul><li>Port enters and remains in the high-speed J or K state </li...
Conclusions <ul><li>High Speed Electrical Testing is Comprehensive  </li></ul><ul><ul><li>Electrical Testing </li></ul></u...
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Choate hs elec_test_final

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  • Test modes enable repeatable testing The first assertion in the test spec is test mode support high speed electrical testing is much more comprehensive because of test modes
  • Testing at TP2
  • Choate hs elec_test_final

    1. 2. High Speed Electrical Testing Jim Choate Intel Corporation
    2. 3. Agenda <ul><li>Electrical Testing Goals </li></ul><ul><li>Test Modes </li></ul><ul><li>Electrical Testing Procedures </li></ul><ul><li>Problems to Avoid </li></ul><ul><li>Summary </li></ul>
    3. 4. Goals of the Electrical Compliance Program <ul><li>High Quality USB Products </li></ul><ul><li>Stable, Repeatable, Well Documented Tests </li></ul><ul><ul><li>Documented Equipment Setups </li></ul></ul><ul><ul><li>Documented Test Procedures </li></ul></ul><ul><ul><li>Documented Test Assertions and Descriptions </li></ul></ul><ul><li>Leverage USB FS/LS Electrical Tests </li></ul><ul><ul><li>FS and LS Electrical Testing (LS for downstream ports) </li></ul></ul><ul><ul><li>Inrush </li></ul></ul><ul><ul><li>Drop and Droop </li></ul></ul>
    4. 5. New Testing Areas <ul><li>Electricals </li></ul><ul><ul><li>High Speed Signal Quality </li></ul></ul><ul><ul><li>Time Domain Reflectometry (TDR) </li></ul></ul><ul><ul><li>Receiver Sensitivity and Squelch </li></ul></ul><ul><ul><li>J and K Voltage Levels </li></ul></ul><ul><ul><li>ChIRP </li></ul></ul><ul><ul><li>Disconnect thresholds </li></ul></ul><ul><ul><li>Packet Parameters </li></ul></ul><ul><ul><li>Suspend/Resume </li></ul></ul><ul><ul><li>High Speed Hub Parameters </li></ul></ul><ul><ul><ul><li>Sync truncation </li></ul></ul></ul><ul><ul><ul><li>EOP dribble </li></ul></ul></ul><ul><ul><ul><li>etc </li></ul></ul></ul><ul><li>USB High Speed Electrical Testing Starts at a High Level </li></ul>HS Electrical Test Spec On USB-IF Members Site
    5. 6. USB HS Electrical Test Modes <ul><li>High-speed Capable Devices/Hubs Must Support Test Modes </li></ul>
    6. 7. General HS Electrical Test Procedure <ul><li>Connect Device Under Test To Test Port on Fixture </li></ul><ul><li>Configure DUT With Test Mode SW </li></ul><ul><li>Isolate DUT from Host with High Speed Relay </li></ul><ul><li>Make Appropriate Electrical Measurements </li></ul>
    7. 8. New Test Fixture(s) <ul><li>Signal Quality </li></ul><ul><li>TDR </li></ul><ul><li>Receiver Sensitivity </li></ul><ul><li>ChIRP </li></ul><ul><li>J and K Levels </li></ul><ul><li>Disconnect threshold </li></ul><ul><li>Packet parameters </li></ul><ul><li>Suspend & Resume </li></ul><ul><li>Test Modes </li></ul>USB HS Test Fixture HS Relay Test Port Initialization Port Diff Probe Data Generator 90 Ohms Power Selection Ckt Vbus1 Vbus2 Vcc Gnd
    8. 9. New Test Fixture(s) High Speed Device Signal Quality Test Fixture Test Port Init Port To Host Controller To Device Under Test Isolation relay power Test Switch Diff Probe Test Point
    9. 10. HS Signal Quality Test Procedure <ul><li>Put Device in Test Mode Test_Packet </li></ul><ul><ul><li>Flip Test Fixture Relays To Route Output to 90 Ohm Termination </li></ul></ul><ul><ul><li>Capture Waveform on oscilloscope </li></ul></ul><ul><ul><li>Analyze data </li></ul></ul><ul><li>Data analysis is performed by generating an eye pattern </li></ul>90  Oscilloscope USB HS Test Fixture HS Relay Test Mode SW Differential Probe Device Under Test
    10. 11. Eye Pattern Generation <ul><li>Time vs. voltage test packet data is transferred from scope to PC through GPIB </li></ul>
    11. 12. Eye Pattern Generation <ul><li>Signal analysis scripts determine data rate from zero volt crossovers </li></ul><ul><ul><li>Crossovers indicated at zero crossings below </li></ul></ul><ul><li>Mean bit time calculated </li></ul><ul><li>Reference frame created from mean </li></ul>
    12. 13. Eye Pattern Generation <ul><li>Reference frame position is optimized by minimizing least squares error between reference frame and actual crossovers </li></ul>Reference points between runs ignored Optimized reference point Actual crossover
    13. 14. Eye Pattern Generation <ul><li>Data is parsed into bit time internals using optimized reference frame </li></ul><ul><li>Eye pattern created from bit time intervals </li></ul>1 bit time
    14. 15. Passing Eye Pattern <ul><li>Example of passing High Speed Eye - Host Controller at TP2 </li></ul>
    15. 16. Failing Eye Patterns <ul><li>Min/Max voltage level failure </li></ul><ul><li>Caused by out of spec HS termination </li></ul><ul><li>Jitter failure </li></ul><ul><li>Caused by noise from power supply </li></ul>
    16. 17. HS Device Receiver Sensitivity and Squelch Test Procedure <ul><li>DUT is Placed In Test_SEO_NAK Test Mode using Test Mode SW </li></ul><ul><li>The test fixture replaces the host by switching the connection to the Data Generator </li></ul><ul><li>Data Generator Generates IN Packets </li></ul><ul><li>Device Must Respond for In Spec Packets </li></ul><ul><li>Device Must Not Respond to Out of Spec Data Generator Output </li></ul>Data Generator Test Mode SW USB 2.0 Test Fixture HS Relay SMA Device under test
    17. 18. HS Device Receiver Sensitivity and Squelch Test Results <ul><li>Device response to nominal packets </li></ul><ul><li>Device response to minimum packets </li></ul><ul><li>Device must not respond to packets below squelch threshold </li></ul>DG packet Device Response No Device Response Minimum Receiver sensitivity threshold
    18. 19. TDR Test Procedure <ul><li>Device Under Test Placed In Test_SEO_NAK Mode </li></ul><ul><li>Relay Switches Idle Data Lines to TDR </li></ul><ul><li>TDR Broadcasts Test Signal </li></ul><ul><li>TDR Measures Signal Reflections To Determine Termination And PCB Impedance </li></ul>TDR Test Mode SW USB 2.0 Test Fixture HS Relay SMA Device Under Test
    19. 20. TDR Test Procedure <ul><li>Determining connector reference location </li></ul><ul><ul><li>TDR connected to test fixture </li></ul></ul><ul><ul><li>Test fixture disconnected from device under test </li></ul></ul><ul><ul><li>Voltage step occurs at connector end (open step) </li></ul></ul>Open voltage step indicates connector reference location
    20. 21. TDR Test Procedure <ul><li>Measuring TDR response </li></ul>ZHSTHRU 70 to 110 Ohms (red cursors) ZHSTERM 80 to 100 Ohms (yellow region) USB connector Excursion of ZHSTHRU passes using exception window
    21. 22. TDR Test Procedure <ul><li>TDR Test Fails </li></ul><ul><ul><li>Cause: Using a ribbon cable between the PCB & USB connector </li></ul></ul>Violates ZHSTHRU for > 800ps
    22. 23. Other Test Modes <ul><li>Test_J & Test_K </li></ul><ul><ul><li>Port enters and remains in the high-speed J or K state </li></ul></ul><ul><ul><li>Allows testing of output voltage and impedance when each output is high or low </li></ul></ul><ul><li>Test Force Enable </li></ul><ul><ul><li>Allows testing disconnect </li></ul></ul>
    23. 24. Conclusions <ul><li>High Speed Electrical Testing is Comprehensive </li></ul><ul><ul><li>Electrical Testing </li></ul></ul><ul><ul><ul><li>HS Signal Quality </li></ul></ul></ul><ul><ul><ul><li>TDR </li></ul></ul></ul><ul><ul><ul><li>Receiver Sensitivity </li></ul></ul></ul><ul><ul><ul><li>Suspend/Resume </li></ul></ul></ul><ul><ul><li>Repeater Testing </li></ul></ul><ul><ul><ul><li>Sync truncation, EOP dribble, etc </li></ul></ul></ul><ul><li>Well Documented Tests </li></ul><ul><ul><li>Test Procedures </li></ul></ul><ul><ul><li>Test Specifications </li></ul></ul>

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