J. Marc Edwards 214 Creststone Drive Cary, NC 27519Cell Phone (919) email@example.com
QUALIFICATIONSHOME • Innovative and entrepreneurial professional withQUALIFICATIONS diverse background in: – High-tech private equity markets & venture capitalEDUCATION – Cloud computing SaaS/PaaS/IaaS services & business strategy – Semiconductor and software business developmentEXPERIENCE – RnD managementPUBLISHED – Electrical engineeringARTICLES – Computer networking, microprocessors & embedded systems. • Possesses keen sense of advanced technology strengths,PATENTS & weaknesses and market potentials with operationalLICENSING experience in startup and transnational companies • Firm grasp on M&A logistics • Demonstrated capacity to propel hi-tech ventures toward realization • Highly adept technical writing, executive-level presentation, and communications skills
EDUCATIONHOMEQUALIFICATIONS •University of North Carolina Chapel Hill Chapel Hill, NC Master of Business Administration (MBA) August 2007EDUCATION •MBA Project: •“Chips and Salsa-Cadence Design Systems and the Electronic Design Automation Industry”EXPERIENCE •Georgia Institute of Technology Atlanta, Georgia Master of Science in Electrical Engineering (MSEE) March 1986PUBLISHEDARTICLES •Concentration Areas: •Digital signal processing, analog electronics and control systems. •Master’s Project:PATENTS & •HW implementation of time-division switch based on sorting, emphasizing gallium arsenideLICENSING performance Clemson University Clemson, South Carolina •Bachelor of Science in Electrical Engineering (BSEE) May 1983 •Tau Beta Pi & Eta Kappa Nu Engineering/Electrical Engineering Honor Fraternity
PROFESSIONAL EXPERIENCE (1)HOME •Nimbis Services – McLean, Virginia October 2009 – Present Lead Architect – Semiconductor Design PortalsQUALIFICATIONS Conceived & materialized a completely new market for the application of cloud computing in the high performance computing manufacturing & design of semiconductor components for the $250B/yr semiconductor market, the “Trusted Silicon Stratus (TSS)”. TSS cloud is a business model thatEDUCATION reallocates critical valuation points within the semiconductor supply chain. Generated market demand across nineteen (19) DoD organizations and IBM (Federal Systems & Microelectronics) culminating in my chairmanship and coordination of a highly regarded, 2-day TSS requirements workshop. MarketEXPERIENCE insight and vision in dissecting complex supply chains defined the need for (1) vertical software workflows (integration of heterogeneous ISV applications), (2) the use of “identity profiles” for separation of authentication and certification rights for supply chain stakeholders, and (3) quantitative,PUBLISHED executable business models, e.g. DoDAF & SysML. Delivered SysML financial and parametric “cloudonomic” models for cloud ROI case analyses. Established value proposition for WorkFlow-as-a-ARTICLES Service (WFaaS) as the crystallization and refinement of IaaS, PaaS, SaaS service offerings. Research-grade innovation includes development of an aspect-oriented XML Schema for Digital- Rights-as-a-Service (DRaaS) as applied to advances in DRM & LCM for multimedia to technology-PATENTS & based intellectual property.LICENSING •Synopsys – Mountain View, California April 2008 – October 2009 Principal Engineer - Member of Technical Staff Lead Corporate Applications, Technical Staff Member for Verification Group BU (VGBU) for Low Power product design, requirements, and strategy. Close interaction with end-customer and RnD teams for next-generation product requirements. Provided sales account managers with inside perspective on complex software products for aligning technical scope with customer needs. Interacted with customer accounts to quickly and efficiently resolve software issues and serve as technical intermediary with company research and development. Conducted new-product, customer-training seminars. Proposed three (3) separate low power products, two (2) of which were funded for development. VGBU standards committee representative for IEEE 1801 Unified Power Standard. Developed initial IEEE 1801 architectural extensions for IEEE 1685/IP-XACT 1.5, SoC IP-Reuse XML Schema standards. Proposed three (3) separate low power products (architecture SNPS confidential), two (2) of which are under development. Three (3) conference/technical publication papers accepted during first nine months.
PROFESSIONAL EXPERIENCE (2)HOME •Cadence Design Systems – San Jose, California February 2005 – April 2008QUALIFICATIONS Senior Technical Lead Consulting Engineer •Joined Electronic Design Automation (EDA) software company with about 4,800 employees and $1.6 billion per year, providing engineering consultation to sales division while attending demandingEDUCATION business school. Provide sales account managers with inside perspective on complex software products for aligning technical scope with customer needs. Interact with customer accounts to quickly and efficiently resolve software issues and serve as technical intermediary with company research andEXPERIENCE development. Conduct customer-training seminars. Develop yearly sales and marketing strategies. Author technical papers for marketing and sales. •Define new applications of existing software product methodologies for hardware and softwarePUBLISHED verification and design, one of company’s key technical sales programs.ARTICLES •Leveraged prior experience in defense research sector to prove market worthiness of receiving large grants for advanced research in electronic design automation industry.PATENTS & •Proved merit of research grant initiative to company’s Vice President by showing customer success with potential partners and estimating $20 million per year potential in grants from Department ofLICENSING Defense. •Research proposal resulting in $6 million defense grant offer in conjunction with Raytheon Space and Airborne Systems group to develop secure design methodology flow. •Accepted technical paper at Cadence Technical Conference (30% submitted papers accepted) lauded by marketing group. •Drove variety of coordination efforts between marketing, sales and research and development that helped identify gaps in low-power product offerings. •Took multiple projects to their first customer engagement including $15 million per year PCI Express Verification Intellectual Property and Incisive Unified Simulator Common Power Format feature. •Enabled company to close approximately $20 million in business with Cisco and supported account managers with enterprise level customers such as Ericsson, IBM and Philips.
PROFESSIONAL EXPERIENCE (4) •Modular Networks – Cary, North Carolina June 2004 – December 2004HOME Director of Engineering •Accepted challenges of helping form technology company with three engineers and of securing ventureQUALIFICATIONS capital funding for open-standard Advanced Telecom Computing Architecture IP switching/packet processing blade subsystems used in carrier-grade telecom TDM-2-IP network migration. Initiated company’s founding charter. Recruited key industry-leading founders. Conducted extensive productEDUCATION positioning and market research. Drove company from startup to ramp-up phase by forming customer relationships. Codeveloped initial project architecture. •Acquired $6 million Series A term sheet from Highland Capital in Boston after securing endorsementsEXPERIENCE from Nokia and Lucent Technologies agreeing to consider using company’s embedded software systems. •Developed marketing strategy of embedding industry-standard ATCA telecommunications platform architecture into numerous network processor architectures under minimal redesign.PUBLISHEDARTICLES •ISIC Corporation – Cary, North Carolina October 2002 – April 2004 Director of EngineeringPATENTS & Co-founded venture-funded search-engine technology company with novel algorithm for searching long,LICENSING fixed-key data structures. Led company to develop low-cost search engine for low- to medium-range network router market. Engaged in applied research and refined design to patent technology. Marketed design to Cisco Systems and maintained close relationships with target product teams. Led architectural specifications for low-cost classification coprocessor component development. •Secured endorsement of technology from Cisco Systems engineering director that enabled company to receive initial seed funding of $1.5 million from venture capitalists. •Submitted patented scheme for producing ultra-fast 256-bit modular polynomial divider that resulted in 0.5-nanosecond propagation delay. •Incorporated new software development methodology using Unified Modeling Language (UML). •Negotiated customer and supply manufacturing relationships and potential acquisition by leading publicly traded semiconductor company through direct interaction with decision makers. •Designed low-end chip architecture that met Cisco’s mid-range router needs and invented critical enhancement to base technology that resulted in faster performance improvements than expected by others.
PROFESSIONAL EXPERIENCE (6)HOME •Protean Devices – Cary, North Carolina September 2001 – October 2002QUALIFICATIONS Director of Engineering •Started fabless semiconductor company specialized in producing novel, reconfigurable SoC architecture from NEC Silicon Systems Research. Secured venture capital to fund business. Prepared presentations; negotiatedEDUCATION licensing agreements with NEC; and set up venture capital meetings in Silicon Valley, Atlanta, Europe and Japan. Grew company to 26 employees charged with designing, marketing and supporting data communication ASSPs.EXPERIENCE •Negotiated engineering contracting agreements with NEC Research to complete company’s initial prototype systems that used NEC’s Dynamic Reconfigurable Processor prototype chip.PUBLISHED •Passionately channeled stream of venture investors, NEC executives, potential customers and market opportunities toward venture to fulfill company’s mission statement and business model.ARTICLES •Envisioned technologys architecture, devised requirements for final manufacturing and extrapolated market applications for numerous engineering problems.PATENTS & •Secured term sheet from Intersouth Partners and The Wakefield Group for Series-A financing of up to $10 million; boldly persuaded NEC executives in Japan to fund initial start up costs with $1.3 million.LICENSING •Gained valuable experience negotiating with mega-corporations and gained preparedness to move forward in future negotiations with transnational corporations using industry experience and pragmatic strategies. •Achieved solicitation from DARPA Polymorphous Computing Architecture program manager to submit research proposal on architecture transition to high performance network processing applications.
PROFESSIONAL EXPERIENCE (7)HOME •Cisco Systems – Research Triangle Park, North Carolina November 1995 – September 2001 Technical Lead Engineer November 2000 – September 2001QUALIFICATIONS Promoted to lead engineering technical teams on new project engagements at research headquarters with about 3,000 personnel for $25 billion per year mega-corporation. Managed project status and coordinated and assigned tasks to team engineers. Assessed design methodologies and engineering specifications. Ensured overall technical merit and drove engineering successes. Directed and trained senior engineers andEDUCATION managers in quality system reference models for ASICs and system-level architectural validations of function and performance. •Led Internet Services Business task force to formulate and consolidate multiple leading-edge parallel opticalEXPERIENCE technologies including optical networks/waveguides and WDM/tunable lasers •Directed design of multiple system-level verification model architectures for QOS/scheduling ASIC used in 50 MPPS IP forwarding engine. •Implemented architectural models used in complex data switching fabrics, PL/4 link interfaces and L2/L3/L4PUBLISHED forwarding ASICs.ARTICLES Hardware Engineer IV November 1995 – November 2000 Joined company’s Interworks Business Unit to design and debug token ring front end switching subsystemPATENTS & for Catalyst 5000 switching hub. Collaborated on design, analysis, integration, synthesis, simulation and verification with colleagues on projects including Ethernet 10/100 ASIC core and token ring inter-switcher-LICENSING link, 8-bit CRC generator FPGA, packet memory DRAM logic, MIPS R4xxx processor/bus model, packet- over-SONET (OC-48/192) and SMP coherency, consistently discovering new technical solutions to engineering problems at hand. •Wrote system design requirements for high-speed HyperTransport I/O processor bus subsystem, designed and integrated FPGAs and developed overall strategy for system level verification. •Trained and guided two internal engineers and four third-party engineers in object-oriented modeling and verification; designed coherency requirements specifications that saw wide use in SMP development. •Initiated and managed research that produced ‘e’-2 Verilog translation tool as basis for establishing object- oriented RTL design verification methodology. •Brought research paper on parallel CRC generation to fruition by implementing proposed algorithm in hardware and corrected two algorithmic flaws in research design. •Recognized by management due to fast implementation of SPECMAN testbench for Catalyst 5000 token ring card in three days; accomplished feat by discovering design bug that had eluded card’s designer. •Saved over $10 million in component costs and far exceeded all expectations of critical power and board space requirements with novel SH-3 design point, prompting 60% cost reductions on FPGA shipments. •Initiated used of Verisity’s SPECMAN ‘e’ verification language for enhanced verification coverage, which re- defined Cisco’s ASIC verification methodology.
PROFESSIONAL EXPERIENCE (8)HOME •IBM Corporation – Research Triangle Park, North Carolina July 1984 – November 1995QUALIFICATIONS Advisory Engineer August 1994 – November 1995 Promoted to lead design of source routing filter/forwarding logic for token ring switching ASIC at majorEDUCATION company research centers in Research Triangle Park, NC & Austin, TX. •Designed unique and innovative implementation of source-routing technology called tank-circuit that company classified as trade secret during projects to avoid disclosure to competitors.EXPERIENCE Staff Engineer October 1989 – August 1994 Designed, developed and tested Indus Microchannel I/O controller for RS/6000 Model 220/230 workstations and progressed to design and develop cache line and buffer management logic for Ionian I/O controller andPUBLISHED local area network switch. Created high-level design methodology, performance requirements and designARTICLES implementation of ASICs for asynchronous transfer mode data mover and processor. •Innovated partitioning method for synthesis of ASIC with super macro structures that achieved sub 17.6 nanosecond target without logic tuning and passed all verification on first round. •Demonstrated intense determination to utilize one design architecture with ability to enhance teamwork byPATENTS & seeing technology through to fruition and production from initial lab environment.LICENSING Senior Associate Engineer October 1987 – October 1989 Promoted to senior engineering design teams developing fiber-distributed data interface adapter card for PS/2 and interface concentrator. Designed, implemented and tested digital circuits used to interface to Microchannel. Created and implemented Microchannel slave interface and design tool methodologies. •Conceptualized, evaluated risks of and implemented first use of Field Programmable Gate Array (FPGA) technology at IBM, effectively introducing useful and novel advance in technology prototyping. •Associate Engineer July 1984 – October 1987 Hired to develop communications controllers and electronic imaging hardware. Developed and verified telecommunications switching system with multiplexing architecture. Remapped CMOS of front-end scanner subsystem. Designed and debugged I/O interface gate array for image processor to ISA low-end parallel bus. Architected high-performance, multi-processor imaging system using parallel-processing array.
PUBLISHED ARTICLESHOME •G. Delp, J. Marc Edwards, R. Rachamim, J. Swanson, ‘e’ ESL-Specification, Generation & Visualization Using IEEE-1801 Power-Managed SoCs (PM-SOCS) – DVCON 2009,QUALIFICATIONS San Jose, CA. •T. Kuhn, T. Oppold, M. Winterholer, W. Rosenstiel, M. Edwards , Y. Kashai, “A Framework for Object-oriented Hardware Specification, Verification, & Synthesis”,EDUCATION Proceedings of the 38th conference on Design automation, p.413-418, June 2001, Las Vegas, Nevada, United States.EXPERIENCE •T. Kuhn , T. Oppold , C. Schulz-Key , M. Winterholer , W. Rosenstiel , M. Edwards , Y. Kashai, “Object-oriented Hardware Synthesis & Verification”, Proceedings of the 14th international symposium on Systems synthesis, September 30-October 03, 2001,PUBLISHED Montréal, P.Q., Canada.ARTICLES •T. Anderson, J. Decker, C. Dietrich, J. Marc Edwards, R. Juliano, C. Komar, “Assertion- Based Verification for Power-Cycled Systems-on-Chip”, DVCon 2009. •G. Hall, J. Marc Edwards, “Application of Functional Coverage-Driven-PATENTS & Verification (CDV) Methodology to Real-Time Embedded Systems-on-ChipLICENSING (SoC) for HW/SW State-Space Co-verification and Architectural Exploration”, High Performance Embedded Computing Conference (HPEC 2005), MIT Lincoln Labs. • J. Marc Edwards, “IEEE 1801 Power Specification Standard”, Portable Design, November, 2008. •K. Kranen, (Ghost Writer, J. Marc Edwards), “UPF 2.0/IEEE 1801, A Next-Generation Low Power Specfication Standard”, EE Times, September, 2008. •J. Marc Edwards, M. Bezdany, “Cadence Design Systems and the EDA Software Industry (B) – Chips-n-Salsa”, UNC-Chapel Hill, Kenan-Flagler School of Business, June, 2007.
HOME PATENTS & LICENSESQUALIFICATIONSEDUCATION •“Method and apparatus for generating error detection data for encapsulated frames”EXPERIENCE • Cisco SystemsPUBLISHED •Novel Polynomial Modular DividerARTICLES (awaiting submission); ISIC CorporationPATENTS &LICENSING •State of North Carolina Raleigh, North Carolina Registered Professional Engineer