Network on ChipStructure and Design Methodologies1
• Introduction• Network-on-Chip Architecture and Function Layers• Network-on-Chip Design Methodologies• Bidirectional Network-on-Chip (BiNoC)Architecture• Conclusion2Content
•The next generation of multiprocessor system onchip (MPSoC) and chip multiprocessors (CMPs)will contain hundreds or thousands of cores.Such a many-core system requires high-performance interconnections to transfer dataamong the cores on the chip.3Abstract
•As the density of VLSI design increases, thecomplexity of each component in a systemraises rapidly.•Today’s SoC designers face a new challengein the design of the on-chip interconnectsbeyond the evolution of an increasingnumber of processing elements4Introduction
Why we need of it ?..• Power efficient processors combined with hardwareaccelerators are the preferred choice for mostdesigners to deliver the best trade off betweenperformance and power consumption.• Hoc methods of selecting few blocks may work basedon a designer’s experience, this may not work astoday’s MPSoC and CMP designs which becomes moreand more complex.5Content
Network-on-Chip Architecture and Function Layers•A typical NoC architecture consists ofmultiple segments of wires and routers.•The NoC function can be classified intoseveral layers: application, transport,network, data link, and physical layers.6
NI-Network Interface R-Routers7Typical NoC architecture in a mesh topology.
• Application Layer: At the application layer, target applications willbe broken down into a set of computation.• Transport Layer: Prevent buffer overflow and avoid trafficcongestion.• Network Layer: Deal with the routing data between processingelements.• Data Link: Increase the reliability of the link up to a minimumrequired level.• Physical Layers: Transfer the data from node to node.8Network-on-Chip Function Layers