DESIGN AND ANALYSIS OF VOLTAGE CONTROLLED OSCILLATORA Mid Term Report for major project submitted in for approvalMASTER OF...
ABSTRACTOur Project is to design of complementary oxide semiconductor voltage controlled oscillator(CMOS VCO) with improve...
LIST OF ABBRIVATIONS1. VCO : Voltage controlled oscillator2. C-MOS : Complementary Metal Oxide Semiconductor3. I.C. : Inte...
LIST OF FIGURES1. Fig 3.1 : Design Process Flowchart………………………………………………………92. Fig 3.2 : The cadence virtuoso command interf...
List of TablesSNo. Table No. Title Page No.1 1 Results of VCO Design 20
TABLE OF CONTENT1. CHAPTER I…………………………………………………………………………………...2INTRODUCTION………………………………………………………………………..…...21.1 Motivatio...
CHAPTER IINTRODUCTION1.1 MotivationA lot of research work has been done on Wireless Communication in the past few years an...
CHAPTER IITHEORETICAL BACKGROUND AND LITERATURE REVIEW2.1 INTRODUCTIONOscillators are a fundamental part in many electroni...
power. A low power design will increase the battery life and low power designs are seen in manyof the recent publications....
of the inductor, the closer it approaches the behavior of an ideal, lossless, inductor. The Q factorof an inductor can be ...
2.5 Design of VCO2.5.1 VCO Circuit DesignThere are two types of VCO that one may choose to designa. Wave Form Oscillatorb....
c. tuning range in percentage = max− min/ o× 100%d. αmin > 1e. chip areaf. Frequency of operation ( o)The goal of the desi...
CHAPTER IIIINTRODUCTION TO DESIGN TOOL3.1 CADENCE VirtuosoCadence Virtuoso Spectre Circuit Simulator provides fast, accura...
3.1.2 IC Design FlowCadence Design Systems provides tools for different design styles. Here we will learn to usethree Cade...
3.2 Getting started with CADENCE VirtuosoFirst of all login as a root user in a linux system(RED HAT).Open the TERMINAL wr...
From the CIW menus, all Cadence main tools, online help and options can be accessed. In thewindow area, all kind of messag...
3.3 Designing of VCO in VirtuosoCreation of Schematic CellviewWe are going to create a schematic. From the CIW or from the...
Adding Components to schematic1. In the schematic window, click the Instance menu icon to display the Add Instance form.Ti...
3. Follow the prompts at the bottom of the design window and click left on the destination pointfor your wire. A wire is r...
2. Verify that the From View Name field is set to schematic, and the To View Name field is setto symbol, with the Tool/Dat...
SimulationWe will run the simulation for VCO and plot the transient, DC characteristics and we will doParametric Analysis ...
Setting the Model Libraries (optional default lib set)The Model Library file contains the model files that describe the NM...
Fig 3.8: Recordings of Trans AnalysisFig 3.9: Simulation Results of VCOI inputV out2Vout1VcontSpectral Power
Calculating Spectral Power1. For calculating spectral power click on Tools-Calculator on ADE-L window, A new windowis open...
BASE PAPER“Layout Design of LC VCO with Current Mirror Using 0.18 μm Technology” By NamrataPrasad and Radheshyam GamadPres...
Fig 4.1: Simulation Response of output responseFig 4.2:Simulation Result on Phase noise @ 1MHzWe are trying to minimized t...
SOFTWARE SPECIFICATIONSpecifications of CADENCE virtuosoINTERACTIVE SIMULATION ENVIRONMENT• Easy to learn and enter data• ...
SCOPE OF MAJOR PROJECTThis project has a huge future scope. Now a day’s VCO’s are being widely used invarious applications...
REFERENCES[1.] Namrata Prasad and Radheshyam Gamad, ―Layout Design of LC VCO with CurrentMirror Using 0.18 μm Technology‖,...
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  1. 1. DESIGN AND ANALYSIS OF VOLTAGE CONTROLLED OSCILLATORA Mid Term Report for major project submitted in for approvalMASTER OF TECHNOLOGYININFORMATION AND COMMUNICATION TECHNOLOGY(for Engineering Graduates)Specilization(VLSI DESIGN)Submitted by:Mr. Sharad Sharma Enrollment No: 12/PIT/054Mr. Vaibhav Jindal Enrollment No: 12/PIT/055Mr. Saurabh Kumar Enrollment No: 12/PIT/068Supervised by:Mr. Navaid Zafar Rizvi-SCHOOL OF INFORMATION AND COMMUNICATION TECHNOLOGYGAUTAM BUDDHA UNIVERSITYGAUTAM BUDH NAGAR, GREATER NOIDAMARCH, 2013
  2. 2. ABSTRACTOur Project is to design of complementary oxide semiconductor voltage controlled oscillator(CMOS VCO) with improved phase noise and lower power consumption. Design is supposed to be areaefficient and power efficient. We have completed the study and analysis part of VCO, and have startedthe designing of VCO in cadence and schematic editor using 180 nm technology. We successfullycompleted the circuit diagram, symbol creation part. Then we moved on to test circuit verification andanalysis. In this report we have also included the results which we got till test circuit simulation. Thelayout part is still remaining, which is very important and main part in governing the power analysis.Thus we can say that we have completed about one third part of Simulation and overall performanceresults are yet to be reported.
  3. 3. LIST OF ABBRIVATIONS1. VCO : Voltage controlled oscillator2. C-MOS : Complementary Metal Oxide Semiconductor3. I.C. : Integrated Chip4. LC : Inductor and Capacitor5. RF : Radio Frequency6. CIW : Command Interface Window7. TRANS : Transient8. DC : Direct Current9. AC : Alternating Current10. ADE : Analog Design Environment11. PAW : Parameter Analyses Window12. µm : Micro Meter
  4. 4. LIST OF FIGURES1. Fig 3.1 : Design Process Flowchart………………………………………………………92. Fig 3.2 : The cadence virtuoso command interface window(CIW)……………………..103. Fig 3.3 : Cadence New library Create …………………………………………………..114. Fig 3.4 : Schematic Cellview ……………………………………………………………125. Fig 3.5 : VCO Schematic Design………………………………………………………...146. Fig 3.6 : VCO Test Schematic…………………………………………………………...157. Fig 3.7 : ADE window…………………………………………………………………..168. Fig 3.8 : Recordings Of Trans analysis…………………………………………………..189. Fig 3.9 : Simulation Results of VCO…………………………………………………….1810. Fig 3.10 : Parameter Analysis Window(Calculator)……………………………………….1911. Fig 4.1 : Simulation Response of output response………………………………………..2112. Fig 4.2 : Simulation Result on Phase noise @ 1MHz…………………………………….21
  5. 5. List of TablesSNo. Table No. Title Page No.1 1 Results of VCO Design 20
  6. 6. TABLE OF CONTENT1. CHAPTER I…………………………………………………………………………………...2INTRODUCTION………………………………………………………………………..…...21.1 Motivation……………………………………………………………………………..21.2 Report Structure…………………………………………………………………….…22. CHAPTER II………………………………………………………………………………….3THEORETICAL BACKGROUND AND LITERATURE REVIEW……………………..…32.1 Introduction to VCO…………………………………………………………………..32.2 VCO Metrics…………………………………………………………………………..32.3 VCO for Frequency Translation……………………………………………………….42.4 VCO Basic…………………………………………………………………………….42.5 Design of VCO………………………………………………………………………..62.5.1 VCO Circuit Design2.5.2 Advantages of LC tank VCO Circuit3. CHAPTER III……………………………………………………………..………………….8INTRODUCTION TO DESIGN TOOL………………………………………………..……83.1 CADENCE Virtuoso…………………………………………………………………83.1.1 Features/Benefits Of CADENCE Virtuoso3.1.2 IC Design Flow3.2 Getting started with CADENCE Virtuoso…………………………………………..103.2.1 Library creation and selection of technology3.3 Designing of VCO in Virtuoso………………………………………………………124. Base Paper……………………………………………………………………………………205. Software Specification………………………………………………………………...……..226. Scope of Major Project………………………………………………………………..……..23References……………………………………………………………………..……...…………24
  7. 7. CHAPTER IINTRODUCTION1.1 MotivationA lot of research work has been done on Wireless Communication in the past few years andmany applications have been developed. Today is increasing demand for wireless andmultimedia applications keeps pushing the CMOS integrated wire-less systems to support muchcommunication standards (WLAN, GSM, UWB and DVB etc). As gigahertz-bandcommunication is becoming more mature, the realization of a single chip transceiver becomesmore demanding, with the need for lower cost, reduced size and less power consumption. For thelocal oscillator signal generated from the integrated frequency synthesizer, the transceiversmatched these standards need excellent phase noise performance and wide tuning range solvingthe frequency offset due to the variations of process, temperature and voltage. As per demand formulti-band and multi-standard radios requires VCO’s operating over a wider frequency range.Wireless standards specify the minimum level of the received signal, the maximum level ofnoise, the channel bandwidth, and the spacing between adjacent channels. Therefore, themaximum amount of acceptable phase noise on the oscillator can be calculated using the re-quired signal to noise ratio after down conversion. We took this project so that we can achievelow phase noise, low power consumption and enlarged tuning range.1.2 Report StructureThis report is organized as follows. Chapter II discusses theoretical background andliterature review which was taken into consideration during our research. In chapter III wehave first introduced the Design tool which we are using to complete our project topic, thenwe have discussed how to start with the tool and finally we have shown that how we aredesigning our topic in this tool and the results achieved up till now. In chapter IV we havediscussed our base paper and its results. Then we have discussed the software specificationsand finally the scope of the Major Project.
  8. 8. CHAPTER IITHEORETICAL BACKGROUND AND LITERATURE REVIEW2.1 INTRODUCTIONOscillators are a fundamental part in many electronic systems. Applications utilizeoscillators from clock generation in microprocessors to frequency translation in mobile phones.Different application also requires different set of oscillator performance parameters. As today’sintegrated circuits are converging towards CMOS, the design of robust and high-performanceCMOS oscillators, more specifically, voltage-controlled oscillators (VCOs), has becomeextremely important. A Voltage controlled oscillator is a circuit that provides a varying outputsignal (typically a square wave or triangular wave forms) whose frequency can be adjusted overa range controlled by a dc voltage. An example of a VCO is the IC 566 IC unit which contain thecircuitry to generate both square and triangular wave signals we are designing the same IC usingC-MOS having low power dissipation and low phase noise.2.2 VCO MetricsThe key metrics of a VCO consist of: oscillation frequency, tuning range, phase noise, andpower consumption. The frequency of oscillation is determined by the application in which theVCO is used in, such as microprocessor or cellular phone. The tuning range is determined by thenecessity of the application and the variation on oscillation frequency due to process andtemperature variation. The center frequency of some CMOS oscillators may vary by a factor oftwo at the extremes of process and temperature, thus a wide tuning range is very desirable. Thedesign of low phase noise VCOs has become another major direction of research. The recenthuge growth in wireless communication has demanded more available channels. As a result thephase noise requirement in the local oscillator becomes more stringent. In digitalmicroprocessors, the phase noise of the oscillator will directly affect the jitter of the clock signaland the timing margin, thus limits system performance. Lastly, power consumption is extremelyimportant for mobile applications such as cellular phones and laptops where a battery supply the
  9. 9. power. A low power design will increase the battery life and low power designs are seen in manyof the recent publications.2.3 VCOs for Frequency TranslationAnother common application for VCOs is frequency translation. In this type of application, suchas radio and cellular phone, base band data needs to be up converted to the carrier frequency fortransmission, or received data down converted to base band for processing. Typically, frequencytranslation requires the VCO to have very high oscillation frequency, on the order of gigahertz, andmore recently, tens of gigahertz, due to the fact that carrier frequencies are becoming higher andhigher. As a result, VCOs used for frequency translation typically uses inductor and capacitor (LC)tank VCO topology for its relatively high oscillation frequency and low phase noise.2.4 Voltage Controlled Oscillator BasicNoise is injected into an oscillator by the devices that constitute the oscillator itself includingthe active transistors and passive elements. This noise will disturb both the amplitude andfrequency of oscillation. Amplitude noise is usually unimportant because non-linearties that limitthe amplitude of oscillation also stabilize the amplitude noise. Phase noise, on the other hand, isessentially a random deviation in frequency which can also be viewed as a random variation inthe zero crossing points of the time-dependent oscillator waveform.CMOS voltage controlled oscillator (VCO) will be challenging RF block. Especially, thehigher close in phase noise due to higher 1/f noise in CMOS continues to be a challenge. As perdemand for multi-band and multi-standard radios requires VCO’s operating over a widerfrequency range. Wireless standards specify the minimum level of the received signal, themaximum level of noise, the channel bandwidth, and the spacing between adjacent channels.Therefore, the maximum amount of acceptable phase noise on the oscillator can be calculatedusing the required signal to noise ratio after down conversion or VCO architecture should havelow phase noise, low power consumption and enlarged tuning range. The low phase noise andenlarged tuning range are accomplished by adding capacitors which is forming frequency tuningnetwork. The phase noise is mainly deter-mined by the quality value of tank higher the Q factor
  10. 10. of the inductor, the closer it approaches the behavior of an ideal, lossless, inductor. The Q factorof an inductor can be found through the following formulaRWoLQ (1)The oscillation frequency of oscillator is given by:LCFosc21( 2 )where L is the inductance of LC-tank and C is the capacitance.Phase Noise is calculated by following formula Equation 3mct ffQffofmfoPavsFKTfmL 1212log10202( 3)WhereL(fm) : phase noise in dBc/Hz.Q : loaded Q of the circuit,fm : frequency from the carrier,fc : flicker noise corner frequency,fo : carrier (oscillator) frequency,T : temperature in Kelvin,Pavs : power through the resonator,F : noise factor of the active device,K : Boltzmann constant.An important concern in the design of VCOs’ is the variation of the output phase and frequencyas a result of noise on the control line. For a given noise in the output frequency is proportionalto Kvco asWout=Wo+Kvco.Vcontwhere, Wo is the intercept at Vcont = 0,Kvco is the gain or sensitivity of the circuit,Wout is output.Maximum d.c power dissipation = Vsupply × Ibias
  11. 11. 2.5 Design of VCO2.5.1 VCO Circuit DesignThere are two types of VCO that one may choose to designa. Wave Form Oscillatorb. Resonant OscillatorWave Form OscillatorThese type of oscillator are designed as Ring Oscillator and Relaxation Oscillator. There islow power consumption but on the other hand it gives poor phase noise performanceResonant OscillatorThese type of oscillator are designed as LC tank oscillator topology and using crystaloscillator. The main disadvantage in this topology is that it neither integrated nor tunable.Ideal VCO has following specificationa. Low noiseb. Low powerc. Integratedd. Wide tuning rangee. Small dice area occupancyf. High frequencyIt is not easy to design VCO with above specification as it is for ideal VCO specification.We have to reduce power consumption and make low phase noise. We will make it by using LCtank Oscillator Design Topology.2.5.2 Advantages of LC tank VCO CircuitIt gives outstanding performance at high frequency of Phase noise as we can tune frequency byusing LC tank circuit. We designed our circuit on virtuoso tool by ―CADENCE‖ as on this toolwe can check our circuit by simulate it and can do power and other analysis.Certain design specifications must be given for designing VCOa. max D.C. power dissipation = Vsupply×Ibiasb. min output voltage swing (single-ended) = Vtank
  12. 12. c. tuning range in percentage = max− min/ o× 100%d. αmin > 1e. chip areaf. Frequency of operation ( o)The goal of the design is then to develop a VCO that meets the above constraints withminimum phase noise. An alternative strategy may be to design a VCO with a pre-specifiedphase noise but where the d.c. power dissipation is minimized.Design Procedure Steps1. Set Ibias = Pd.c. max/Vsupply2. Determine max of inductors for a given process at required frequency o. This can bedetermined in many ways includingi. Already known from previous design experience in that particular process.ii. Read from model elements in design kit.iii. Determined through exhaustive design and optimization of inductor using electromagneticsimulation packages.iv. Measured data taken from test inductors already fabricated in the same process.3. Using = L, set L so that is at the minimum required voltageswing for the design. , o and area already known.Where values of L must be chosen such that it is in a practical value range to be fabricated aswell as being at a value that results in a practical value of capacitance, C, for the varactor.4. Using Where = effective series resistance of inductor, calculatethe required value of C for the LC tank with o being the center frequency of the VCO.5. Given the minimum closed loop gain min α > 1 calculate the minimum transconductanceof each NMOS transistor gm such that gm = αmin RC/L.
  13. 13. CHAPTER IIIINTRODUCTION TO DESIGN TOOL3.1 CADENCE VirtuosoCadence Virtuoso Spectre Circuit Simulator provides fast, accurate SPICE-levelsimulation for tough analog, radio frequency (RF) and mixed-signal circuits. It is tightlyintegrated with the Virtuoso custom design platform and provides detailed transistor-levelanalysis in multiple domains. Its superior architecture allows for low memory consumption andhigh capacity analysis.3.1.1 Features/Benefits Of CADENCE VirtuosoIt provides high-performance, high-capacity SPICE-level analog and RF simulation with out-of-the-box tuning for accuracy and convergence.Facilitates the tradeoff between accuracy and performance through user-friendly simulationsetup applicable to the most complex analog and custom-digital ICs Enables accurate andefficient post-layout simulation with RLC parasitic, S-Parameter models (n-port), and lossycoupled transmission lines.Performs application-specific analysis of RF performance parameters (spectral response, gaincompression, inter-modulation distortion, impedance matching, stability, isolation).Includes advanced statistical analysis (Smart, MonteCarlo, DCmatch) to help designcompanies improve the manufacturability and yield of ICs at advanced process nodeswithout sacrificing time to market.Delivers fast interactive simulation set-up, cross-probing, visualization, and post-processingof simulation results through tight integration with Virtuoso Analog Design Environment.Ensures higher design quality using silicon-accurate, foundry-certified device models sharedwithin Virtuoso Multi-Mode Simulation
  14. 14. 3.1.2 IC Design FlowCadence Design Systems provides tools for different design styles. Here we will learn to usethree Cadence products: Composer Symbol, Composer Schematic and the Virtuoso LayoutEditor. We will also learn how to get started with Cadence and successfully create symbol,schematic and layout views. The final check will be seeing whether our layout matches yourschematic.Fig 3.1: Design Process Flowchart
  15. 15. 3.2 Getting started with CADENCE VirtuosoFirst of all login as a root user in a linux system(RED HAT).Open the TERMINAL write the following commands : mount -t nfs cadenceserver:/root/cadence /mnt/cadence(To mount the cadence database from the server) cd cadence (to access the cadence directory) csh (to work in c shell as cadence is compatible to c shell) source cshrc (to activate the changes in c shell) cd cadencedb (to access the cadence database directory) cd cadence_ms_labs_613 (to access the version installed) virtuoso (to open cadence virtuoso)This will open a window like this:Fig 3.2: The cadence virtuoso command interface window(CIW)
  16. 16. From the CIW menus, all Cadence main tools, online help and options can be accessed. In thewindow area, all kind of messages (info, errors, warnings, etc) generated by the differentCadence tools appear.3.2.1 Library creation and selection of technologyIt is recommended that we use a library to store related cell views; e.g., use a library to hold allthe cellviews for a single project (that can involve a complete chip design). In our example, weare going to create a new library for our design. From the CIW or from the Library Managerwindow,a) Select File -> New -> Library. A new window appears following screen.b) Enter a library name, e.g., projectc) Enter the absolute path name if we want the library created somewhere else than the workingdirectory.d) Choose the Attach to an existing technology file option.e) Choose your technology.This will be the technology chosen for your design (that we will employ eventually forfabrication). Now all the designs made in this library are technology-dependent (e.g., theschematic MOS symbol save by default the model for this technology, the available layout layerscorrespond to this technology, etc.).Fig 3.3: Cadence New library Create
  17. 17. 3.3 Designing of VCO in VirtuosoCreation of Schematic CellviewWe are going to create a schematic. From the CIW or from the Library Manager window,a) Select the library name that we just created, e.g., mydesignlibb) Select File -> New -> Cellviewc) Enter a cell name, for instance, VCOd) Choose Composer - Schematic as the Tool. View name should be schematic.e) Click OK.An empty blank Composer - schematic window should open. In this window we will create yourschematic.Fig 3.4: Schematic Cellview
  18. 18. Adding Components to schematic1. In the schematic window, click the Instance menu icon to display the Add Instance form.Tip: You can also execute Create — Instance or press i.2. Click on the Browse button. This opens up a Library browser from which you can selectcomponents and the symbol view. You will update the Library Name, Cell Name, and theproperty values given in the table on the next page as you place each component.3. After you complete the Add Instance form, move your cursor to the schematic window andclick left to place a component. If you place a component with the wrong parameter values, usethe Edit—Properties— Objects command to change the parameters. Use the Edit— Movecommand if you place components in the wrong location. You can rotate components at the timeyou place them, or use the Edit— Rotate command after they are placed.4. After entering components, click Cancel in the Add Instance form or press Esc with yourcursor in the schematic window.Adding pins to Schematic1. Click the Pin fixed menu icon in the schematic window. We can also execute Create — Pin orpress p. The Add pin form appears.2. Type the following in the Add pin form in the exact order leaving space between the pinnames. Make sure that the direction field is set to input/output/input-output when placing theinput/output/in-out pins respectively and the Usage field is set to schematic.3. Select Cancel from the Add – pin form after placing the pins. In the schematic window,execute Window— Fit or press the f bind key.Adding Wires to a SchematicAdd wires to connect components and pins in the design.1. Click the Wire (narrow) icon in the schematic window. We can also press the w key, orexecute Create — Wire (narrow).2. In the schematic window, click on a pin of one of your components as the first point for yourwiring. A diamond shape appears over the starting point of this wire.
  19. 19. 3. Follow the prompts at the bottom of the design window and click left on the destination pointfor your wire. A wire is routed between the source and destination points.4. Complete the wiring as shown in figure and when done wiring press ESC key in the schematicwindow to cancel wiring.Saving the Design1. Click the Check and Save icon in the schematic editor window.2. Observe the CIW output area for any errors.Fig 3.5: VCO Schematic DesignSymbol Creation1. In the schematic window, execute Create — Cellview— From Cellview.The Cellview From Cellview form appears. With the Edit Options function active, you cancontrol the appearance of the symbol to generate.
  20. 20. 2. Verify that the From View Name field is set to schematic, and the To View Name field is setto symbol, with the Tool/Data Type set as Schematic Symbol.3. Click OK in the Cellview from Cellview form. The Symbol Generation Form appears.4. Modify the Pin Specifications if any.5. Click OK in the Symbol Generation Options form.6. A new window displays an automatically created symbol of schematic cellview.7. The symbol can be modified to a desired symbol using geometrical tools available in thedesign window.Building the Test DesignWe will create Test cellview that will contain an instance of our cellview for which we will runSimulation.1. In the CIW or Library Manager, execute File— New— Cellview.2. Set up the new cellview, name it and select the type Schematic.3. Click OK when done. A blank schematic window for the Test design appears.4. Build the test circuit according to needs by which simulation can be done.Fig 3.6: VCO Test Schematic
  21. 21. SimulationWe will run the simulation for VCO and plot the transient, DC characteristics and we will doParametric Analysis after the initial simulation. For this we can launch various Analog DesignEnvironments such as ADE L-The analog design environment window display the designinformation on the title bar and the design variables, Analyses, and outputs in different panes.ADE XL- is the new design environment in IC 6.1 for mixed signal design.ADE XL is providesis support to run multiple tests in parallel and storing all results in a central location. ADE GXL-you can perform optimization, characterization and modeling tasks, and multi technologysimulation on your designs in the ADE GXL environment.Starting the Simulation Environment1. In the Test schematic window, execute: Launch – ADE LThe Virtuoso Analog Design Environment (ADE) simulation window appears.Fig 3.7: ADE windowChoosing a Simulator (optional, default is spectre)Set the environment to use the Spectre® tool, a high speed, highly accurate analog simulator.Use this simulator with the Test design, which is made-up of analog components.1. In the simulation window (ADE), execute Setup— Simulator/Directory/Host.2. In the Choosing Simulator form, set the Simulator field to spectre (NotspectreS) and click OK.
  22. 22. Setting the Model Libraries (optional default lib set)The Model Library file contains the model files that describe the NMOS and PMOS devicesduring Simulation.1. In the simulation window (ADE),: Execute Setup - Model Libraries. The Model Library Setupform appears. Click the browse button to add gpdk.scs if not added by defaultas shown in the Model Library Setup form. Remember to select the section type as stat in frontof the gpdk.scs file. To view the model file, highlight the expression in the Model Library Filefield and Click Edit File.2. To complete the Model Library Setup, move the cursor and click OK. The Model LibrarySetup allows you to include multiple model files. It also allows you to use the Edit button toview the model file.Choosing Analyses1. In the Simulation window (ADE), click the Choose - Analyses icon.The Choosing Analysis form appears. This is a dynamic form, the bottom of the form changesbased on the selection above.2. To setup for transient analysisa. In the Analysis section select ―tran‖.b. Set the stop time for example 2nc. Click at the moderate or enabled button at the bottom, and then click Apply.3. Click OK in the Choosing Analyses Form.Selecting Outputs for Plotting1. Execute Outputs – To be plotted – Select on Schematic in the simulation window.2. Follow the prompt at the bottom of the schematic window, Click on output net Vout1 & Vout2, input net Vcont & Iin of the VCO. Press ESC with the cursor in the schematic after selecting it.Running the Simulation1. Execute Simulation – Netlist and Run in the simulation window to start the Simulation or theIcon, this will create the netlist as well as run the simulation.2. When simulation finishes, the Transient plots automatically will be popped up along withlog file.
  23. 23. Fig 3.8: Recordings of Trans AnalysisFig 3.9: Simulation Results of VCOI inputV out2Vout1VcontSpectral Power
  24. 24. Calculating Spectral Power1. For calculating spectral power click on Tools-Calculator on ADE-L window, A new windowis opened.2. Choose All parameters and in that choose spectral power.3. Select input voltage and current wave forms from plotted waves.4. Click on calculated button.5. Choose All parameters and in that choose average.6. Select spectral power wave forms from plotted waves.7. Click on calculated button.By the above steps power is calculated and that is WattsFig 3.10: Parameter Analysis Window(Calculator)
  25. 25. BASE PAPER“Layout Design of LC VCO with Current Mirror Using 0.18 μm Technology” By NamrataPrasad and Radheshyam GamadPresented At: Conference of Wireless Engineering and Technology, 2011This paper presents a new design of complementary oxide semiconductor voltagecontrolled oscillator (CMOS VCO) for improve tuning range and phase noise with low powerconsumption. Design is area efficient and easy to implement. Design is carried out in cadenceand schematic editor using 180 nm technology.In base paper work is carried out under the environment of cadence software andschematic editor is used for design entry, by using UMC 0.18 μm technology. In that design theyhave applied 2V as a supply at the center frequency of 3.3 GHz. Simulation have been done andobtained values are: the band width of 1.625 GHz, phase noise of –155.78 dBc/Hz @ 1MHz and–156.89 dBc/Hz @ 100 MHz and phase margin of 180° given in Table 1. Simulated outputvoltage responses of this design are presented in Figure 4.1. Phase noise is given in Figure 4.2with the power consumption of 7.40 mW at supply volt-age of 2V and FOM is 367 dBF.Table 1 Results of VCO DesignParameters Namrata Prasad et alGeneral VCO(Without current mirror)Propose VCO(With current mirror)Operating Voltage 2V 2VTechnology(CMOS) 0.18um 0.18umPower Consumption 12.72mW 7.40mWOperating Frequency 3.3GHz 3.3GHzTuning Range 29.8% 4.20%Phase Noise (dBc/Hz) 63.7 at 1MHz -155.78 at 1MHzBandwidth(GHz) 1.611 1.625FOM(dBF) 141 367Phase Margin 180 180
  26. 26. Fig 4.1: Simulation Response of output responseFig 4.2:Simulation Result on Phase noise @ 1MHzWe are trying to minimized the power consumption of general VCO (with currentmirrors) by varying the channel length of MOS.
  27. 27. SOFTWARE SPECIFICATIONSpecifications of CADENCE virtuosoINTERACTIVE SIMULATION ENVIRONMENT• Easy to learn and enter data• Simulation set-ups can be reused• Quick analysis of multiple simulation data• Cross probing support for both schematics and layouts• Multiple measurement syntaxes supported• Batch scripting waveform display• Supports multiple Y-axes, strip plots, and Smith Charts• Built-in waveform calculator• Independent sub window displays• Horizontal and vertical measurement markers• Independent pan and zoom capability• Signal browser distributed processing• Parallel analysis option• Job monitoring and controlling functionsDESIGN INPUTS• Open Access data objects• Cadence CDBA data objects• SPICEDESIGN OUTPUTS• SPICE• PSF Waveform format• Perl language• HTMLPLATFORM/OS• Sun/Solaris• HP-UX• Linux
  28. 28. SCOPE OF MAJOR PROJECTThis project has a huge future scope. Now a day’s VCO’s are being widely used invarious applications like VCOs for Phase Locked Loops., VCOs for Frequency Translation forwireless communication, as a result of which the demand of VCO will go on ever increasing inengineering domain.This project also aims at developing a VCO that has a lower phase noise comparable toother present VCO’s. VCO’s with lower phase noise found great applications in wirelesscommunication. As the domain of communication has broad opportunities of research anddevelopment, VCO’s will always be required and taken into account for research anddevelopment. Another aim of this project is to develop a Low Power VCO. Nowadays electronicmarket is growing with huge pace. A huge number of electronic devices like mobile phones,function generator etc deploy VCO in there circuitry. But in the future scarcity of power is goingto be a great problem. A famous proverb says that ―The Electricity saved is Electricity created‖.So to save our electricity and to increase the life of batteries we need to minimize the powerlosses in the electronic and electrical equipments. A power efficient VCO will prove to be a greatstep in this direction of power saving as it will help in minimizing the power losses.
  29. 29. REFERENCES[1.] Namrata Prasad and Radheshyam Gamad, ―Layout Design of LC VCO with CurrentMirror Using 0.18 μm Technology‖, Scientific Research Journal on Wireless Engineeringand Technology, 2011.[2.] H. Y. Wang, N. J. Wu and G. L. Shou, ―A Novel CMOS Low Phase Noise VCO withEnlarged Tuning Range,‖ International Conference on Microwave and Millimeter WaveTechnology, Nanjing, 2008.[3.] N. Prasad, R. S. Gamad and C. B. Kushwah, ―Design of a 2.2 - 4.0 GHz Low Phase Noiseand Low Power LC VCO,‖ International Journal of Computer and NetworkSecurity, 2009.[4.] P. Dudulwar, K. Shah, H. Le and J. Singh, ―Design and Analysis of Low Power LowPhase Noise VCO,‖ 13th IEEE International Conference on Mixed Design of IntegratedCircuits and Systems,2006.[5.] B. Razavi, ―Deign of Analog Complementary MOS Integrated Circuits, Edition 3‖ TataMcGraw-Hill, Delhi, 2002.[6.] M. Al-Azab, ―Modeling and Characterization of a 5.2 GHz VCO for WirelessCommunication,‖ 26th National Radio Science Conference, Cairo, 2009.[7.] H. Y. Wang, N. J. Wu and G. L. Shou, ―A Novel CMOS Low Phase Noise VCO withEnlarged Tuning Range,‖ International Conference on Microwave and Millimeter WaveTechnology, Nanjing, 2008.[8.] Man-Long Her, Pao-Hsun Wu, Chun-Yuan Huang, ―Design and Implementation of aLow Power VCO for K-Band Application‖, Cross Strait Quad-Regional Radio Scienceand Wireless Technology Conference, 2012.[9.] Qiong Zou, Kaixue Ma, Kiat Seng Yeo and Wei Meng Lim, ―Design of a Ku-band Low-Phase-Noise VCO Using the Dual LC Tanks‖, IEEE Transactions on Circuits andSystem, 2012.[10.] Larry B. Li, Jiang Cao, Scott Wu, and Victor Kong, ―Fast Settling and Low Phase NoiseSynthesizer and VCO Design‖2001.[11.] T. H. Lee and A. Hajimiri, ―Oscillator Phase Noise: A Tutorial,‖ IEEE Journal of Solid-State Circuits, 2000.

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