K J Somaiya College of Engineering                    Vidyavihar, Mumbai 400 077                   Department: Electronics...
KJSCE/BE/ETRX/VII-SEM/2011-12Basic constructs and commands of VerilogVerilog Constructs:Basic Gates(and, or, xor):These im...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:     4:1 Multiplexer , 3:8 DecoderAim:         To understand the conditio...
endConditional Operator: “?”Conditional operator is like those in C/C++. They evaluate one ofthe two expressions based on ...
The input is controlled by a set of select inputs. The figure showsa block diagram of a 4:1 multiplexer. The truth table i...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:T- flip flop, counter (structural)Aim:To understand behavioral and struct...
KJSCE/BE/ETRX/VII-SEM/2011-12Logic and diagram for T- flip-flopLogic and diagram for counter using T- flip-flopsRoll No:Si...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:State machines a) Moore b) MealyAim:To describe sequential circuits in ve...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Study of NMOS invertersAim:To describe NMOS inverters in spice and compar...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Inverter layout using magic and simulation using spiceAim:To create an in...
KJSCE/BE/ETRX/VII-SEM/2011-12the region that is to be painted. This can be used to paintany layer or contact or a via.The ...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:NAND/NOR layout and simulation using Magic andSpice3Aim:To extract and si...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Boolean Expression layout and simulation usingMicrowindAim:To simulate Bo...
KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Transmission gate layout and simulation usingMicrowindAim:To simulate tra...
transistors, there is no reason to differentiate betweensource and drain in a T-gate.                                     ...
Upcoming SlideShare
Loading in …5
×

Vlsiexpt 11 12

511
-1

Published on

Published in: Education, Technology, Design
0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
511
On Slideshare
0
From Embeds
0
Number of Embeds
0
Actions
Shares
0
Downloads
7
Comments
0
Likes
0
Embeds 0
No embeds

No notes for slide

Vlsiexpt 11 12

  1. 1. K J Somaiya College of Engineering Vidyavihar, Mumbai 400 077 Department: Electronics EngineeringName of the Laboratory: VLSIYear: Final year Semester: VIIBranch: ElectronicsSubject: VLSI Design List of Experiments 1. Spice simulation of NMOS inverter with a)Resistive load b) Enhancement load c) Depletion load d) PMOS load 2. CMOS inverter layout and simulation using Magic and Spice3 3. NAND/NOR layout and simulation using Magic and Spice3 4. Boolean Expression layout and simulation using Microwind 5. Transmission gate layout and simulation using Microwind 6. Verilog programming and simulation :a) 4:1 mux b) 3:8 Decoder 7. Verilog programming and simulation : T- flip flop, counter (structural) 8. Verilog programming and simulation : State machines a) Moore b) Mealy
  2. 2. KJSCE/BE/ETRX/VII-SEM/2011-12Basic constructs and commands of VerilogVerilog Constructs:Basic Gates(and, or, xor):These implement the basic logic gates. They have one output and one or more inputs.In the gate instantiation syntax shown below, GATE stands for one of the keywordsand, nand, or, nor, xor, xnor.Syntax:GATE(drive strength)#(delays)instance_name1(output, input_1,input_2, …, input_N),instance_name2(output,in1,in2,…,inN);Wire:A wire represents a physical wire in a circuit and is used to connect gates or modules.The value of a wire can be read, but not assigned to, in a function or block A wire doesnot store its value but must be driven by a continuous assignment statement or byconnecting it to the output of a gate or module. Other specific types of wires include:1. wand(wired and);: The value of a wand depends on logical AND of all the driversconnected to it.2. wor(wired-or);: The value of a wor depends on logical OR of all the driversconnected to it.3. tri(three-state);: All drivers connected to a tri must be z, except one (whichdetermines the value of the tri).Syntax:wire[msb:lsb]wire_variable_list;wand[msb:lsb]wand_variable_list;wor[msb:lsb]wor_variable_list;tri[msb:lsb]tri_variable_list;Reg:A reg(register) is a data object that holds its value from one procedural assignment tothe next. They are used only in functions and procedural blocks. A reg is a Verilogvariable type and does not necessarily imply a physical register. In multi-bit registers,data is stored as unsigned numbers and no sign extension is done for what the usermight have thought were two’s complement numbers.
  3. 3. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title: 4:1 Multiplexer , 3:8 DecoderAim: To understand the conditional constructs and commands of VerilogTheory: Continuous assignment statement assign A continuous assignment statement is the most basic statement in dataflow modeling, used to drive a value onto net. This assignment replaces gates in the description of the circuit and describes the circuit at a higher level of abstraction. Continuous assignment is done with an explicit assign statement or by assigning a value to a wire during its declaration. Note that continuous assignment statements are concurrent and are continuously executed during simulation. The order of assign statements does not matter. Any change in any of the right-hand side inputs will immediately change a left-hand side output. The syntax of the assign statement is as follows: continuous_assign ::=assign[drive_strength][delay]net_assignment list_of_net_assignment ::= net_assignment {net_assignment} net_assignment ::= net_value = expression Always Block The always block is the primary construct in RTL modeling. Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation. This also means that all always blocks in a module execute simultaneously. This is very unlike conventional programming languages, in which all statements execute sequentially. The always block can be used to imply latches, flip-flops or combinational logic. If the statements in the always block are enclosed within begin … end, the statements are executed sequentially. If enclosed within the fork … join, they are executed concurrently (simulation only). Syntax 1 always@(event_1 or event_2 or…) begin … statements … end Syntax 2 always@(event_1 or event_2 or …) begin: name_for_block … statements …
  4. 4. endConditional Operator: “?”Conditional operator is like those in C/C++. They evaluate one ofthe two expressions based on condition. It will synthesize to amultiplexer.Syntax(cond)?(result if cond true):(result if cond false)CaseThe case statement allows a multi-path branch based oncomparing the expression with a list of case choices. Statementsin the default block executes when none of the case choicecomparisons are true (similar to the else blockin the if … else if…else). If no comparisons, including default, are true,synthesizers will generate unwanted latches. Good practice saysto make a habit of putting in a default whether you need it or not.If the defaults are don’t cares, define them as ‘x’ and the logicminimize will treat them as don’t cares. Case choices may be asimple constant or expression, or a comma-separated list ofsame.case(expression)case_choice1:begin… statements …enddefault:begin… statements …endendcaseif … else if … elseThe if … else if … else statements execute a statement or blockof statements depending on the result of the expression followingthe if. If the conditional expressions in all the if’s evaluate to false,then the statements in the else block, if present, are executed.There can be as many else if statements as required, but onlyone if block and one else block. If there is one statement in ablock, then the begin … end statements may be omitted. Boththe else if and else statements are optional. However if all thepossibilities are not specifically covered, synthesis will generateextra latches.Syntaxif (expression)KJSCE/BE/ETRX/VII-SEM/2010-11begin… statements …endelse if (expression)begin… statements …endThe multiplexer is a special combinational circuit that is one of themost widely used standard circuit in digital design. The multiplexeris a logic circuit that gates out several inputs to a single output.
  5. 5. The input is controlled by a set of select inputs. The figure showsa block diagram of a 4:1 multiplexer. The truth table is shownbelow.Select Inputs OutputS1 S2 Y0 0 I00 1 I11 0 I21 1 I3Y = S1’ S0’ I0 + S1’ S0 I1 + S1 S0’ I2 + S1 S0 I3BlockDiagram:4:1 MultiplexerKJSCE/BE/ETRX/VII-SEM/2010-11A decoder performs the reverse function of the multiplexer. It hasone input and several outputs. The truth table of 3:8 decoder isshown below.Input Control OutputS0 S1 S20 0 0 111111100 0 1 111111010 1 0 111110110 1 1 111101111 0 0 111011111 0 1 110111111 1 0 101111111 1 1 01111111BlockDiagram:3: 8 DecoderRoll No: Signature of faculty in-chargeConclusion:
  6. 6. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:T- flip flop, counter (structural)Aim:To understand behavioral and structural architecturedescription in verilogTheory: Need for behavioral descriptionNeed for structural description
  7. 7. KJSCE/BE/ETRX/VII-SEM/2011-12Logic and diagram for T- flip-flopLogic and diagram for counter using T- flip-flopsRoll No:Signature of faculty in-chargeConclusion:
  8. 8. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:State machines a) Moore b) MealyAim:To describe sequential circuits in verilog and compareperformances of moore and mealy machines in terms ofareaTheory: 1) Design of sequence detector : Mealy typeKJSCE/BE/ETRX/VII-SEM/2010-112) Design of sequence detector : Moore typeMachine Area Delay1)Comparison :2)Roll No: Signature of faculty in-chargeConclusion:
  9. 9. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Study of NMOS invertersAim:To describe NMOS inverters in spice and compare theirperformances in terms of VOH,VOL values and slope ofthe transfer curveTheory: 1) Resistive load inverter2) Enhancement load inverterKJSCE/BE/ETRX/VII-SEM/2010-113)Depletion load inverter4) PMOS load( CMOS) inverterComparison :VOH VOLComment ontransfer curveResistive loadEnhancementloadDepletion loadCMOSRoll No: Signature of faculty in-chargeConclusion:
  10. 10. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Inverter layout using magic and simulation using spiceAim:To create an inverter layout using magic and simulateusing spice.Theory: The inverter circuit is a circuit which inverts the input andgives it as output. The inverter made over here is a CMOSinverter. The CMOS inverter contains the PMOS transistorin the pull up section and NMOS transistor in the pulldown section. The input is given to the gates of the twotransistors. and the output is taken at the junction of drainof PMOS and drain of NMOS.What is Magic?Magic is an interactive system for creating andmodifying VLSI circuit layouts. With Magic you use a colorgraphics display and a mouse or graphics tablet to designbasic cells and to combine them heirarchy into largestructures. Magic is different from other layout editors youmay have used. The most important difference is thatmagic is more than just a color painting tool: itunderstands quite a bit about the nature of the circuits anduses this information to provide you with additionaloperations. For example, magic has built in knowledge oflayout rules; as you are editing, it continuously checks forrule violations. Magic also knows about connectivity andtransistors and contains a built in heirarchial circuitextractors. Magic also has a plow operation that you canuse to stretch or compact cells. Lastly Magic has routingtools that you can use to make the global interconnectionsin the circuits.Magic is based on the Mead-Conway style of design.This means that it uses simplified design rules and circuitstructures. The simplifies make it easier for you to designcircuits and permit magic to provide powerful assistancethat would not be possible otherwise. However they resultin slightly less dense circuits that you could get usingmore complex rules and structures. For example, magicpermits on manhattan designs (those whose edges arevertical and horizontal). Circuit designers tell us thatconservative design rules cost 5 - 10 in density. We thinkthat the density sacrifice is compensated for by reduceddesign time.‘paint’ :- The ‘paint’ command is used to paint a selectedbox in the layout window. This is followed by the name of
  11. 11. KJSCE/BE/ETRX/VII-SEM/2011-12the region that is to be painted. This can be used to paintany layer or contact or a via.The syntax is as follows :: paint layer‘stretch’:-This command is used to increase or decreasethe size of selected layer. This command is followed by‘up’ or ‘down’. And the size by which the layer is to bechanged.‘save’ :- This command is used to save the current layoutmagic file.‘label’ :- This command is used to label a particular layerin the layout. For this, left and right mouse button isclicked in the same place and then command is typed;followed by the label wanted.Example- :label VDD‘delete’ :- this command will delete the selected cell in thelayout.:save filename – saves the file:extract all – extracts electrical parameters from the layoutto enable simulationSpiceLinux prompt> ext2spice -f spice3 filenameThis command creates filename.spice file with the netlistof active devices and node capacitances with sizes andparameters corresponding to the Magic layout.Additional cir file is created to give inputs to the nodes.Input voltage is specified as a 0-to-5V pulsating voltage(with 0-to-5V transition delayed by 1ns, rise time of 0.1ns,fall time of 0.1ns, pulse width of 2ns, and period of 4ns)Roll No:Signature of faculty in-chargeConclusion:The inverter layout was created using MAGIC. It is aninteractive system used for modifying and creating VLSIcircuit layouts. It continuously checks for rule violationsas the user is editing. The various commands used argrid,paint, label, save, stretch, etc.The CMOS inverter was extracted and simulated usingSPICE3. To get proper VTC the (W/L)pmos_ 2.5(W/L)nmosIf you do not maintain the above proportion then theproper VTC is not obtained.
  12. 12. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:NAND/NOR layout and simulation using Magic andSpice3Aim:To extract and simulate NAND/NOR layout andsimulation using Magic and Spice3Theory: NAND/NOR gate using CMOSStick diagramsRoll No:Signature of faculty in-chargeConclusion:
  13. 13. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Boolean Expression layout and simulation usingMicrowindAim:To simulate Boolean Expression layout usingMicrowindTheory: Boolean expression using CMOSStick diagramRoll No:Signature of faculty in-chargeConclusion:
  14. 14. KJSCE/BE/ETRX/VII-SEM/2011-12EXPERIMENT NO:Title:Transmission gate layout and simulation usingMicrowindAim:To simulate transmission gate layout and simulationusing MicrowindTheory: While both N-type and P-type transistors indeed have avery large resistance between source and drain whenswitched off, a detailed analysis reveals that theresistance between source and drain depends on thesource and drain voltages when switched on. Especially,there is a voltage drop across a conducting N-typetransistor when the source voltage is near VCC, and avoltage drop across a conducting P-type transistor whenits source voltage is near GND. (Note that this poses noproblem in the static CMOS gates, where all sourcecontacts of N-type transistors are connected to GND andall source contacts of P-type transistors are connected toVCC.)Therefore, the use of single N-type or P-type transistors asswitches is limited to circuits where the voltage dropacross the conducting transistors is not critical. A seriesconnection of transistors used as switches is usually notpossible in digital circuits.But a combination of N-type and P-type transistors allowsto realize efficient switches in CMOS technology. Thecircuit consists of one N-type and one P-type transistorconnected in parallel and controlled by inverted gatevoltages. This circuit, called a transmission gate (T-gate)A T-gate requires that the N-type and P-type transistorshave inverted gate voltages.If the gate voltage of the N-type transistor is GND, the Ptypetransistor has a gate voltage of VCC and bothtransistors are non-conducting. On the other hand, if thegate voltage of the N-type transistor is VCC and the gatevoltage of the P-type transistor is GND, both transistorsare conducting. If the source voltage is near VCC, there isa voltage drop across the N-type transistor but (almost) novoltage drop across the P-type transistor. If the sourcevoltage is near GND, the N-type transistor has (almost) novoltage drop. Because of the symmetry of standard MOS
  15. 15. transistors, there is no reason to differentiate betweensource and drain in a T-gate. KJSCE/BE/ETRX/VII-SEM/2011-12Stick diagram of transmission gateRoll No: Signature of faculty in-chargeConclusion:

×