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Radiation Hardening by Design

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Radiation Hardening by Design is one of the hardware based solution to one of the most troublesome problem faced by digital circuits in the space. …

Radiation Hardening by Design is one of the hardware based solution to one of the most troublesome problem faced by digital circuits in the space.
RHBD provides varieties of techniques to make the circuit resilient towards such effects and ensures proper malfunctioning of the circuit.

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  • 1. Yash Tilvawala 10BEC099 Jay Baxi 10BEC115 Under the Guidance of Prof. Usha Mehta Professor, Nirma University
  • 2.        Introduction to Radiation Hardening Radiation Effect on Semiconductors Types of Radiation Hardening by Design RHBD – Gate Sizing A Novel Gate Approach References Conclusion
  • 3.   In physics radiation is a process in which energetic particles or energy or waves travel through a medium or space. Radiation hardening is a method of designing and testing electronic components and systems to make them resistant to damage or malfunctions caused by ionizing radiation(particle radiation and highenergy electromagnetic radiation).
  • 4.  Major causes of radiation are 1.) Trapped Electrons 2.) Trapped Protons 3.) Solar Protons 4.) Cosmic Rays
  • 5.  Trapped electrons are negatively charged particles that are relatively low in mass, but they are also extremely energetic. Due to their small masses, they are typically found is very high orbits such as the Geosynchronous orbits (or GEO orbits) that are approximately 36,000 km above the earth.
  • 6.  Trapped protons are positively charged particles held captive by a planet’s gravitation field. They are less energetic that electrons, but they are approximately 2000 times more massive than electrons. They exist in high concentrations at low altitudes. For example, Low Earth Orbits (LEOs), such as those located 1400km – 2000km from the earth’s surface, are proton-dominated orbits.
  • 7.  Solar protons are similar to trapped protons except they are ejected from the Sun during a solar fare event and are therefore not trapped in the planet’s gravitation field.
  • 8.  Cosmic rays are the final source of natural space-borne radiation. They are comprised of alpha particles, heavy ions and protons. Heavy ions are the primary concern when considering the effects of cosmic rays on semiconductors because these massive, highly charged particles can cause severe damage to devices.
  • 9.  TID:  SEL:  SEU: Total Ionizing Dose is the amount of radiation or energy that a semiconductor can absorb before it stops functioning. It is measured in rad(Si), or radiation absorbed relative to silicon. Measured in MeV, it is defined as the event in which the highly energized particle collides with the device and the current dramatically increases beyond the specification value. Digitally, SEU is mainly responsible for changing of a0 to a1. In analog circuits, it produces a spike in the output. Measured in MeV.
  • 10.       Possible methods: 1) Error correcting memory 2) Redundant elements 3) Watchdog timer 4) Gate sizing 5) Novel Approach
  • 11. It utilizes extra parity bits to check for and possibly correct the corrupted data.  Radiation Effects may destroy the memory content even if the system is not accessing the RAM, the so called scrubber circuit should be used to continuously sweep the RAM. Following three steps are involved.  1.) Reading out the DATA  2.) Checking the PARITY of the data-errors  3.) Writing back any correction to the RAM APPLICATIONS: The error correcting memory is especially suitable for high tolerant applications such as servers as well as deep space applications due to cosmic radiations. 
  • 12. Redundancy is the duplication of critical components of the system so as to enhance system reliability typically in the case of a backup or a fail-safe.  An error in one component can be outvoted by the other two.  In a triply redundant system three subcomponents must fail before the system does. Since each one seldom fails and is expected to fail independently.  The probability that all three fail is calculated to be extremely small. 
  • 13.  There are four major types of redundancies as follows:  1.) Hardware Redundancy. Eg. DMR (Dual Module Redundancy) and TMR (Triple Module Redundancy)  2.) Information Redundancy. Eg. Error Detection and correction methods.  3.) Time Redundancy. Eg. Transient fall detection methods such as alternate logic.  4.) Software Redundancy. Eg. N version programming.
  • 14. A watchdog timer will perform a hard reset of a system unless some sequence is performed that generally indicates the system is alive, such as a write operation from an on board processor.  During normal operations software schedules a write the watchdog timer at regular intervals to prevent the timer from running out.  So if the system is detected to be affected by radiation the timer will time out and the system will perform hard reset. 
  • 15.   In this method we modify the W/L ratio of the transistor so that we can have desired current handling capacity. The proposed algorithm uses an efficient fault simulation-based technique to identify and rank the critical nodes that contribute significantly to the soft error failure rate of a combinational logic block.
  • 16.  Part 1: Gate Level SEU protection  Approach A: PN Junction Diode based SEU Clamping Circuits  Approach B: Diode-connected Device based SEU Clamping Circuits  Part 2: Logic Block Level Protection  Radiation hardening for all gates  Fixed depth protection  Variable depth protection
  • 17. PN Junction Diode based SEU Clamping Circuits V (out) Radiation Strike 1V in out G 0V D2 1.4V GP Shadow Gate 0.8 0.6 0.4 0.2 0 D1 V (outP) outP -0.4V time Higher VT device 0.8 0.6 0.4 0.2 0 -0.4 time 17
  • 18. Diode-connected Device based SEU Clamping Circuits V (out) Radiation Strike 1V in out G 0V D2 Ids 1.4V GP 0.8 0.6 0.4 0.2 0 D1 V (outP) outP -0.4V time Higher VT device 0.8 0.6 0.4 0.2 0 -0.4 time 18
  • 19. Performed layout and spice level simulation Approach A has higher area penalty than B But performance of approach A is slightly better than B Therefore, selected approach B
  • 20.  ABSTRACT:  This employs cost effective methodology for soft error reduction.  Experiments were performed for various technologies ranging from 180 nm - 70nm. On average 38.1% , 27.1%, 38% radiation hardening was observed in area, power reduction and delay were observed for worst case SEUs.
  • 21.  Proposed technique is used for radiation hardening that increases critical charge on node. Qcrit is the minimum charge required to develop SEU.  A node is hardened by adding capacitance (to increase Qcrit ) or drive (to dissipate the deposited charge) or combination of both. This can be achieved by altering the W/L ratio.
  • 22.  Proposed technique is compatible with other optimization techniques that specifically target area, delay or power reduction.  It can also be used to complement other fault avoidance and fault detection techniques, such as SOI (silicon-on-insulator) substrates, error detection and correction codes, etc.  By addressing SEU robustness earlier in design cycle, it aids the synthesis of inherently reliable circuits, thereby reducing the number of iterations.
  • 23.     The three interrelated factors that determine whether a particle strike at a node produces a SEU at that node are: 1) The total charge deposited at the node 2) The drive strength of the gate that drives the node 3) The capacitance of the node.
  • 24.  Consider a two-input NAND gate driving a lumped capacitance Cp at its output N in Fig. 1. The total capacitance at N is  The charge deposition due to a particle strike at N is modeled by a double exponential current pulse Iin at the site of the particle strike.  Where Q is the charge (positive or negative) deposited as a result of the particle strike, τα is the collection time constant of the junction, and τβ is the ion-track establishment time constant. τα and τβ are constants that depend on several process-related factors.
  • 25.   The limit to the peak value is set to 0.5Vdd. However it is to be kept in mind that the following method is equally applicable for all the values of peak. The output voltage is obtained as a solution to the following equation: Where Ctotal is the total capacitance at N (Eq. 1), Iin is the current from the particle strike (Eq. 2), and (W/L) is the aspect ratio of a single nMOS transistor in the gate.  Id is the effective drain current through the nMOS transistor network in the gate and is a function of Vout. 
  • 26. In each subfigure, it is clear that as the size of the nMOS transistors (which dissipate the deposited charge) increases, the magnitude and duration of the SEU transient diminish rapidly.
  • 27. Output waveform during a radiation event on output
  • 28.  The first condition is that the slope dVout/dt must equal 0 at tmax, i.e.,  The second condition is given by the charge conservation.
  • 29.   Since ID is a nonlinear equation that depends on Vout, the following approximation is used to simplify the integral. It is assumed that the voltage Vout rises from 0 to the peak value of 0.5VDD linearly, i.e.,
  • 30.     Gate Sizing technique implemented has the characteristic of compatibility, also complements the fault avoidance and detection/tolerance. It also emphasizes on reliability by reducing the number of iterations. We have presented a novel circuit design approach for radiation hardened circuit design. We use shadow gates and protecting diodeconnected devices to protect the primary gate from a radiation strike.
  • 31.        1.) M. Dowd, “How Rad Hard do you need? The Changing Approach”, Maxwell Technologies Microelectronics. 2.)http://en.wikipedia.org/wiki/Radiation_hardening 3.)http://www.militaryaerospace.com/articles/2011/05/radiationhardened-electronics.html 4.) Ron Locoe, Aerospace Corp., “Designing Radiation Hardened CMOS Microelectronic Components At Commercial Foundries: Space and Terrestrial Radiation Environments and Device and Circuit Techniques to mitigate Radiation Effects” 5.) G.U. Youk, N. H. Lee, B.S. Kim, Y.B. Lee, Seungho Kim, “Technology Development for the Radiation Hardening of Robots”, Proceedings of the 1999 IEEERSJ International Conference on Intelligent Robots and Systems 6.) H. Hatano, “Radiation hardened high performance CMOS VLSI circuit designs”, Ph.D 7.) Z. Hu, Z. Liu, H. Shao, Z. Zhang, B. Ning, M. Chen, D. Bi and S. Zou,“Radiation Hardening by Applying Substrate Bias”, IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 58, NO. 3, JUNE 2011, pp. 1355-1360.