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  • 1. MHMilil arbidePower FlB JRYflllT BflllGfl
  • 2. EMiTim CarbidePower Devices
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  • 4. Carbide Power Devices B jnvnnT BRLIGR North Carolina State University, USA [p World ScientificN E W JERSEY • L O N D O N • SINGAPORE • BEIJING • S H A N G H A I • HONG KONG • T A I P E I • C H E N N A I
  • 5. Published byWorld Scientific Publishing Co. Pte. Ltd.5 Toh Tuck Link, Singapore 596224USA office: 27 Warren Street, Suite 401-402, Hackensack, NJ 07601UK office: 57 Shelton Street, Covent Garden, London WC2H 9HEBritish Library Cataloguing-in-Publication DataA catalogue record for this book is available from the British Library.SILICON CARBIDE POWER DEVICESCopyright © 2005 by World Scientific Publishing Co. Pte. Ltd.All rights reserved. This book, or parts thereof, may not be reproduced in any form or by any means,electronic or mechanical, including photocopying, recording or any information storage and retrievalsystem now known or to be invented, without written permission from the Publisher.For photocopying of material in this volume, please pay a copying fee through the CopyrightClearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, USA. In this case permission tophotocopy is not required from the publisher.ISBN 981-256-605-8Printed in Singapore by B & JO Enterprise
  • 6. DedicationThe author would like to dedicate this book to his family- his wife, Pratima and his sons, Avinash and Vinay - fortheir support of his commitment to create a world-wideeffort on the development and commercialization ofpower devices based upon wide band-gapsemiconductors. V
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  • 8. PrefacePower semiconductor devices are a key component of all powerelectronic systems. It is estimated that at least 50 percent of theelectricity used in the world is controlled by power devices. With thewide spread use of electronics in the consumer, industrial, medical, andtransportation sectors, power devices have a major impact on theeconomy because they determine the cost and efficiency of systems.After the initial replacement of vacuum tubes by solid state devices in the 1950s, semiconductor power devices have taken a dominant role withsilicon serving as the base material. Bipolar power devices, such as bipolar transistors and thyristors,were first developed in the 1950s. Their power ratings and switchingfrequency increased with advancements in the understanding of theoperating physics and availability of more advanced lithographycapability. The physics underlying the current conduction and switchingspeed of these devices has been described in several textbooks12. Sincethe thyristors were developed for high voltage DC transmission andelectric locomotive drives, the emphasis was on increasing the voltagerating and current handling capability. The ability to use neutrontransmutation doping to produce high resistivity n-type silicon withimproved uniformity across large diameter wafers enabled increasing theblocking voltage of thyristors to over 5000 volts while being able tohandle over 2000 amperes of current in a single device. Meanwhile,bipolar power transistors were developed with the goal of increasing theswitching frequency in medium power systems. Unfortunately, thecurrent gain of bipolar transistors becomes low when it is designed forhigh voltage operation at high current density. The popular solution tothis problem, using the Darlington configuration, had the disadvantage ofincreasing the on-state voltage drop resulting in an increase in the powerdissipation. In addition to the large control currents required for bipolartransistors, they suffered from second breakdown failure modes. These vu
  • 9. VU1 SILICON CARBIDE POWER DEVICESissues produced a cumbersome design with snubber networks, whichraised the cost and degraded the efficiency of the power control system. In the 1970s, the power MOSFET product was first introducedby International Rectifier Corporation. Although initially hailed as areplacement for all bipolar power devices due to its high inputimpedance and fast switching speed, the power MOSFET hassuccessfully cornered the market for low voltage (< 100 V) and highswitching speed (> 100 kHz) applications but failed to make seriousinroads in the high voltage arena. This is because the on-state resistanceof power MOSFETs increases very rapidly with increase in thebreakdown voltage. The resulting high conduction losses, even whenusing larger more expensive die, degrade the overall system efficiency. In recognition of these issues, I proposed two new thrusts in 1979 for the power device field. The first was based upon the merging ofMOS and bipolar device physics to create a new category of powerdevices3. My most successful innovation among MOS-Bipolar deviceshas been the Insulated Gate Bipolar Transistor (IGBT). Soon aftercommercial introduction in the early 1980s, the IGBT was adopted for allmedium power electronics applications. Today, it is manufactured bymore than a dozen companies around the world for consumer, industrial,medical, and other applications that benefit society. The triumph of theIGBT is associated with its huge power gain, high input impedance, widesafe operating area, and a switching speed that can be tailored forapplications depending upon their operating frequency. The second approach that I suggested in the early 1980s forenhancing the performance of power devices was to replace silicon withwide band gap semiconductors. The basis for this approach was anequation that I derived relating the on-resistance of the drift region inunipolar power devices to the basic properties of the semiconductormaterial. This equation has since been referred to as Baligas Figure ofMerit (BFOM). In addition to the expected reduction in the on-stateresistance with higher carrier mobility, the equation predicts a reductionin on-resistance as the inverse of the cube of the breakdown electric fieldstrength of the semiconductor material. In the 1970s, there was a dearth of knowledge of the impactionization coefficients of semiconductors. Consequently, an associationof the breakdown electric field strength was made with the energy bandgap of the semiconductor4. This led to the conclusion that wide band gapsemiconductors offer the opportunity to greatly reduce the on-stateresistance of the drift region in power devices. With a sufficiently low
  • 10. Preface IX on-state resistance, it became possible to postulate that unipolar power devices could be constructed from wide band gap semiconductors with lower on-state voltage drop than bipolar devices made out of silicon. Since unipolar devices exhibit much faster switching speed than bipolar devices because of the absence of minority carrier stored charge, wide band gap based power devices offered a much superior alternative to silicon bipolar devices for medium and high power applications. Device structures that were particularly suitable for development were identified as Schottky rectifiers to replace silicon P-i-N rectifiers, and power Field Effect Transistors to replace the bipolar transistors and thyristors prevalent in the 1970s. The first attempt to develop wide band gap based power devices was undertaken at the General Electric Corporate Research and Development Center, Schenectady, NY, under my direction. The goal was to leverage a 13-fold reduction in specific on-resistance for the drift region predicted by the BFOM for Gallium Arsenide. A team of 10 scientists was assembled to tackle the difficult problems of the growth of high resistivity epitaxial layers, the fabrication of low resistivity ohmiccontacts, low leakage Schottky contacts, and the passivation of the GaAs surface. This led to an enhanced understanding of the breakdown strength5 for GaAs and the successful fabrication of high performanceSchottky rectifiers6 and MESFETs7. Experimental verification of thebasic thesis of the analysis represented by BFOM was thereforedemonstrated during this period. Commercial GaAs based Schottkyrectifier products were subsequently introduced in the market by severalcompanies. In the later half of the 1980s, the technology for the growth of silicon carbide was developed with the culmination of commercialavailability of wafers from CREE Research Corporation. Although dataon the impact ionization coefficients of SiC was not available, earlyreports on the breakdown voltage of diodes enabled estimation of thebreakdown electric field strength. Using these numbers in the BFOMpredicted an impressive 100-200 fold reduction in the specific on-resistance of the drift region for SiC based unipolar devices. In 1988, Ijoined North Carolina State University and subsequently founded thePower Semiconductor Research Center (PSRC) - an industrialconsortium - with the objective of exploring ideas to enhance powerdevice performance. Within the first year of the inception of theprogram, SiC Schottky barrier rectifiers with breakdown voltage of 400volts were successfully fabricated with on-state voltage drop of about 1
  • 11. X SILICON CARBIDE POWER DEVICESvolt and no reverse recovery transients . By improving the edgetermination of these diodes, the breakdown voltage was found to increaseto 1000 volts. With the availability of epitaxial SiC material with lowerdoping concentrations, SiC Schottky rectifiers with breakdown voltagesover 2.5 kV have been fabricated at PSRC9. These results have motivatedmany other groups around the world to develop SiC based powerrectifiers. In this regard, it has been my privilege to assist in theestablishment of national programs to fund research on silicon carbidetechnology in the United States, Japan, and Switzerland-Sweden.Meanwhile, accurate measurements of the impact ionization coefficientsfor 6H-SiC and 4H-SiC in defect free regions were performed at PSRCusing an electron beam excitation method10. Using these coefficients, aBFOM of over 1000 is predicted for SiC providing even greatermotivation to develop power devices from this material. Although the fabrication of high performance, high voltageSchottky rectifiers has been relatively straight-forward, the developmentof a suitable silicon carbide MOSFET structure has been moreproblematic. The existing silicon power D-MOSFET and U-MOSFETstructures do not directly translate to suitable structures in siliconcarbide. The interface between SiC and silicon dioxide, as a gatedielectric, needed extensive investigation due to the large density of trapsthat prevent the formation of high conductivity inversion layers. Evenafter overcoming this hurdle, the much higher electric field in the silicondioxide when compared with silicon devices, resulting from the muchlarger electric field in the underlying SiC, leads to reliability problems.Fortunately, a structural innovation, called the ACCUFET, to overcomeboth problems was proposed and demonstrated at PSRC11. In thisstructure, a buried P+ region is used to shield the gate region from thehigh electric field within the SiC drift region. This concept is applicableto devices that utilize either accumulation channels or inversionchannels. Devices with low specific on-resistance have beendemonstrated at PSRC using both 6H-SiC and 4H-SiC with epitaxialmaterial capable of supporting over 5000 volts12. This device structurehas been subsequently emulated by several groups around the world. Although many papers have been published on silicon carbidedevice structures and process technology, no comprehensive bookwritten by a single author is available that provides a unified treatment ofsilicon carbide power device structures. This book has been prepared tofill this gap. The emphasis in the book is on the physics of operation ofthe devices elucidated by extensive two-dimensional numerical analysis.
  • 12. Preface XIThe simulations were done for 4H-SiC, rather than 6H-SiC, because itslarger breakdown strength results in superior device performance. Thisanalysis provides general guidelines for understanding the design andoperation of the various device structures. For designs that may bepertinent to specific applications, the reader should refer to the paperspublished in the literature, the theses of my M.S. and Ph.D. students, aswell as the work reported by other research groups. Comparison withsilicon devices is provided to enable the reader to understand the benefitsof silicon carbide devices. In the introduction chapter, the desired characteristics of powerdevices are described with a broad introduction to potential applications.The second chapter provides the properties of silicon carbide that haverelevance to the analysis and performance of power device structures.Issues pertinent to the fabrication of silicon carbide devices are reviewedhere because the structures analyzed in the book have been constructedwith these process limitations in mind. The third chapter discussesbreakdown voltage, which is the most unique distinguishingcharacteristic for power devices, together with edge terminationstructures. This analysis is pertinent to all the device structures discussedin subsequent chapters of the book. The fourth chapter provides a brief analysis of P-i-N rectifiersfollowed by a detailed analysis of the Schottky rectifier structure inchapter five. The sixth chapter introduces the concept and explains thebenefits of shielding the Schottky contact. This approach is essential formitigating the generation of high leakage current in silicon carbideSchottky rectifiers arising from Schottky barrier lowering and tunnelingcurrents. The next chapter describes power JFET and MESFETstructures with planar and trench gate regions. These normally-onstructures can be used to construct the Baliga-Pair circuit13, described inchapter eight, which has been shown to be ideally suitable for motorcontrol applications. This represents a near term solution to takingadvantage of the low specific on-resistance of the silicon carbide driftregion while awaiting resolution of reliability issues with the gate oxidein silicon carbide power MOSFET structures. Chapter nine provides a description of silicon carbide powerMOSFET structures with emphasis on problems associated with simplyreplicating structures originally developed in silicon technology.Innovative approaches to prevent high electric field in the gate oxide ofsilicon carbide power MOSFETs are then discussed in chapter ten. In thischapter, accumulation-mode structures are shown to provide the
  • 13. Xll SILICON CARBIDE POWER DEVICESadvantages of larger channel mobility and lower threshold voltageleading to a reduction in the specific on-resistance. In chapter eleven,issues with adopting the silicon UMOSFET structure to silicon carbideare enunciated followed by analysis of solutions to these problems inchapter twelve. Once again, methods for shielding the gate oxide areshown to enable reduction of the electric field in the gate oxide toacceptable levels. The shielding is also demonstrates to ameliorate thebase reach-through problem allowing a reduction of the base width andhence the channel resistance contribution. The application of the charge-coupling concept to silicon carbideis explored in chapter thirteen to reduce the resistance of the drift region.This approach is applicable to very high voltage structures with blockingvoltage capability exceeding 3000 volts. In chapter fourteen, theoperation of the integral diode within the silicon carbide power MOSFETstructures is analyzed for utilization as a fly-back rectifier in motorcontrol applications. A unique mode of current conduction in the siliconcarbide power MOSFET in the third quadrant of operation is identifiedhere which allows for a reduction of the on-state voltage drop of theintegral diode. Although the emphasis in this book has been on discrete verticalsilicon carbide structures, for the sake of completeness, the fifteenthchapter describes high voltage lateral silicon carbide structures that aresuitable for integration with CMOS circuits. In the concluding sixteenthchapter, the performance of silicon carbide devices is compared with thatof silicon devices using a typical motor control application as an exampleto provide the reader with a perspective on the benefits of using siliconcarbide devices. From an applications perspective, it is demonstrated thatthe replacement of the silicon P-i-N rectifier with the silicon carbide JBSrectifier provides a significant reduction in the power losses for thesystem as well as the stress experienced by the silicon IGBT. Thisapproach is already becoming a commercially viable option due to theavailability of silicon carbide Schottky rectifier products from severalcompanies. Throughout the book, experimental results are includedwhenever pertinent to each chapter. This provides a historical contextand a brief summary of the state of the art for silicon carbide devices.Issues that must be addressed before commercialization of siliconcarbide structures becomes viable are pointed out in these sections of thebook.
  • 14. Preface xin I am hopeful that this book will be used for the teaching ofcourses on solid state devices and that it will make an essential referencefor the power device industry. To facilitate this, analytical solutions areprovided throughout the book that can be utilized to understand theunderlying physics and model the structures. Comparison of the siliconcarbide structures with their silicon counterparts is also includedwhenever pertinent to the discussion. Ever since my identification of the benefits of utilizing wideband gap semiconductors for the development of superior power devicestwenty-five years ago, it has been my mission to resolve issues thatwould impede their commercialization. I wish to thank the sponsors ofthe Power Semiconductor Research Center and the Office of NavalResearch for supporting this mission during the last fifteen years. Thishas been essential to providing the resources required to create manybreakthroughs in the silicon carbide technology which I hope will enablecommercialization of the technology in the near future. I look forward toobserving the benefits accrued to society by adopting the silicon carbidetechnology for conservation of fossil fuel usage resulting in reducedenvironmental pollution. Prof. B. Jayant Baliga 2005
  • 15. XIV SILICON CARBIDE POWER DEVICESReferences1 B.J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.2 S. K. Ghandhi, "Semiconductor Power Devices", John Wiley andSons, 1977.3 B. J. Baliga, "Evolution of MOS-Bipolar Power SemiconductorTechnology", Proceedings IEEE, pp. 409-418, April 1988.4 B.J. Baliga, "Semiconductors for High Voltage Vertical Channel FieldEffect Transistors", J. Applied Physics, Vol. 53, pp. 1759-1764, March1982.5 B.J. Baliga, R. Ehle, J.R. Shealy, and W. Garwacki, "BreakdownCharacteristics of Gallium Arsenide", IEEE Electron Device Letters,Vol. EDL-2, pp. 302-304, November 1981.6 B. J. Baliga, A.R. Sears, M.M. Barnicle, P.M. Campbell, W.Garwacki, and J.P. Walden, "Gallium Arsenide Schottky PowerRectifiers", IEEE Transactions on Electron Devices, Vol. ED-32, pp.1130-1134, June 1985.7 P.M. Campbell, W. Garwacki, A.R. Sears, P. Menditto, and B.J.Baliga, Trapezoidal-Groove Schottky-Gate Vertical-Channel GaAsFET", IEEE Electron Device Letters, Vol. EDL-6, pp. 304-306, June1985.8 M. Bhatnagar, P.K. McLarty, and B.J. Baliga, "Silicon-Carbide High-Voltage (400 V) Schottky Barrier Diodes", IEEE Electron DeviceLetters, Vol. EDL-13, pp.501-503, October 1992.9 R.K. Chilukuri and B.J. Baliga, "High Voltage Ni/4H-SiC SchottkyRectifiers", International Symposium on Power Semiconductor Devicesand ICs, pp. 161-164, May 1999.10 R. Raghunathan and B.J. Baliga, Temperature dependence of HoleImpact Ionization Coefficients in 4H and 6H-SiC", Solid StateElectronics, Vol. 43, pp. 199-211, February 1999.11 P.M. Shenoy and B.J. Baliga, "High Voltage Planar 6H-SiCACCUFET", International Conference on Silicon Carbide, Ill-Nitrides,and Related Materials, Abstract Tu3b-3, pp. 158-159, August 1997.12 R.K. Chilukuri and B.J. Baliga, PSRC Technical Report TR-00-007,May 2000.13 B.J. Baliga, See Chapter 7 in "Power Semiconductor Devices", pp.417-420, PWS Publishing Company, 1996.
  • 16. ContentsPreface viiChapter 1 Introduction 11.1 Ideal and Typical Power Device Characteristics 31.2 Unipolar Power Devices 61.3 Bipolar Power Devices 81.4 MOS-Bipolar Power Devices 91.5 Ideal Drift Region for Unipolar Power Devices 111.6 Summary 13 References 14Chapter 2 Material Properties and Technology 152.1 Fundamental Properties 16 2.1.1 Energy Band Gap 17 2.1.2 Impact Ionization Coefficients 21 2.1.3 Electron Mobility 232.2 Other Properties Relevant to Power Devices 25 2.2.1 Donor and Acceptor Ionization Energy Levels 25 2.2.2 Recombination Lifetimes 26 2.2.3 Metal-Semiconductor Contacts 262.3 Fabrication Technology 28 2.3.1 Diffusion Coefficients and Solubility of Dopants 28 2.3.2 Ion Implantation and Annealing 29 2.3.3 Gate Oxide Formation 29 2.3.4 Reactive Ion Etching of Trenches 322.4 Summary 32 References 33 XV
  • 17. xvi SILICON CARBIDE POWER DEVICESChapter 3 Breakdown Voltage 373.1 One-Dimensional Abrupt Junction 373.2 Schottky Diode Edge Termination 44 3.2.1 Planar Schottky Diode Edge Termination 44 3.2.2 Planar Schottky Diode with Field Plate Termination 45 3.2.3 Schottky Diode with Floating Metal Rings 50 3.2.4 Schottky Diode Edge Termination with Argon Implant ....50 3.2.5 Schottky Diode Edge Termination with RESP Region 523.3 P-N Junction Edge Termination 53 3.3.1 Planar Junction Edge Termination 53 3.3.2 Planar Junction Edge Termination with Field Plate 57 3.3.3 Planar Junction Edge Termination with Floating Rings 61 3.3.4 Planar Junction Edge Termination with P-Extension 623.4 Summary 68 References 69Chapter 4 PiN Rectifiers 714.1 One-Dimensional PiN Structure 714.2 Experimental Results 794.3 Summary 80 References 81Chapter 5 Schottky Rectifiers 835.1 Schottky Rectifier Structure: Forward Conduction 84 5.1.1 Forward Conduction: Simulation Results 88 5.1.2 Forward Conduction: Experimental Results 905.2 Schottky Rectifier Structure: Reverse Blocking 915.3 Schottky Rectifier Structure: Impact of Defects 965.4 Reliability Issues 1005.5 Summary 100 References 101
  • 18. Contents xviiChapter 6 Shielded Schottky Rectifiers 1036.1 Junction Barrier Schottky (JBS) Rectifier Structure 104 6.1.1 JBS Rectifier Structure: Forward Conduction Model 106 6.1.2 JBS Rectifier Structure: Reverse Leakage Model 108 6.1.3 JBS Rectifier Structure: Simulation Results 109 6.1.4 JBS Rectifier Structure: Experimental Results 1186.2 Trench MOS Barrier Schottky (TMBS) Rectifier Structure 120 6.2.1 TMBS Rectifier Structure: Simulation Results 1216.3 Trench Schottky Barrier Schottky (TSBS) Rectifier Structure... 124 6.3.1 TSBS Rectifier Structure: Simulation Results 127 6.3.2 TSBS Rectifiers: Experimental Results 1386.4 Summary 138 References 139Chapter 7 Metal-Semiconductor Field Effect Transistors 1417.1 Trench Junction (Metal-Semiconductor) FET Structure 142 7.1.1 Forward Blocking 144 7.1.2 On-State 1487.2 Trench MESFET Structure: Simulation Results 151 7.2.1 On-State Characteristics 151 7.2.2 Blocking Characteristics 154 7.2.3 Output Characteristics 1637.3 JFET Structure: Simulation Results 1657.4 Planar MESFET Structure 168 7.4.1 Forward Blocking 170 7.4.2 On-State Resistance 1707.5 Planar MESFET Structure: Numerical Simulations 174 7.5.1 On-State Characteristics 174 7.5.2 Blocking Characteristics 177 7.5.3 Output Characteristics 187 7.5.4 Gate Contact Shielding 1897.6 Experimental Results: Trench Gate Structures 1917.7 Experimental Results: Planar Gate Structures 1947.8 Summary 195 References 196
  • 19. XVU1 SILICON CARBIDE POWER DEVICESChapter 8 The Baliga-Pair Configuration 1998.1 The Baliga-Pair Configuration 201 8.1.1 Voltage Blocking Mode 202 8.1.2 Forward Conduction Mode 203 8.1.3 Current Saturation Mode 203 8.1.4 Switching Characteristics 204 8.1.5 Fly-Back Diode 2048.2 Baliga-Pair: Simulation Results 205 8.2.1 Voltage Blocking Mode 206 8.2.2 Forward Conduction Mode 208 8.2.3 Current Saturation Mode 210 8.2.4 Switching Characteristics 211 8.2.5 Fly-Back Diode 2148.3 Baliga-Pair Configuration: Experimental Results 2178.4 Summary 217 References 218Chapter 9 Planar Power MOSFETs 2219.1 Planar Power MOSFET Structure 223 9.1.1 Blocking Characteristics 224 9.1.2 Forward Conduction 227 9.1.3 Threshold Voltage 234 9.1.4 Threshold Voltage Simulations 238 9.1.5 Hot Electron Injection 2419.2 Planar Power MOSFET Structure: Numerical Simulations 242 9.2.1 Blocking Characteristics 243 9.2.2 On-State Characteristics 247 9.2.3 Output Characteristics 2509.3 Planar Power MOSFET: Experimental Results 252 9.3.1 Silicon Carbide MOSFET: Inversion Layer Mobility 253 9.3.2 The 4H-SiC Planar MOSFET: Experimental Results 2549.4 Summary 254 References 256
  • 20. Contents xixChapter 10 Shielded Planar MOSFETs 25910.1 Shielded Planar MOSFET Structure 260 10.1.1 Blocking Mode 261 10.1.2 Forward Conduction 262 10.1.3 Threshold Voltage 267 10.1.4ACCUFET Structure: Threshold Voltage Simulations....27010.2 Planar Shielded Inversion-Mode MOSFET: Simulations 276 10.2.1 Blocking Characteristics 276 10.2.2On-State Characteristics 279 10.2.3 Output Characteristics 28110.3 Planar Shielded ACCUFET Structure: Simulations 282 10.3.1 Blocking Characteristics 283 10.3.2 On-State Characteristics 290 10.3.3 Output Characteristics 29510.4 Planar Shielded MOSFET Structures: Experimental Results 297 10.4.1 Silicon Carbide MOSFET: Accumulation Mobility 298 10.4.2Inversion-Mode MOSFET: Experimental Results 300 10.4.3 Accumulation-Mode MOSFET: Experimental Results....30110.5 Summary 303 References 304Chapter 11 Trench-Gate Power MOSFETs 30711.1 Trench-Gate Power MOSFET Structure 308 11.1.1 Blocking Characteristics 309 11.1.2 Forward Conduction 310 11.1.3 Threshold Voltage 31611.2 Trench-Gate Power MOSFET Structure: Simulations 318 11.2.1 Blocking Characteristics 318 11.2.2 On-State Characteristics 323 11.2.3 Output Characteristics 32511.3 Accumulation-Mode Trench-Gate Power MOSFET 32611.4 High Permittivity Gate Insulator 32811.5 Trench-Gate Power MOSFET: Experimental Results 33311.6 Summary 335 References 336
  • 21. XX SILICON CARBIDE POWER DEVICESChapter 12 Shielded Trench-Gate Power MOSFETs 33912.1 Shielded Trench-Gate Power MOSFET Structure 340 12.1.1 Blocking Characteristics 341 12.1.2Forward Conduction 342 12.1.3 Threshold Voltage 34812.2 Shielded Trench-Gate Power MOSFET: Simulations 348 12.2.1 Blocking Characteristics 349 12.2.2 On-State Characteristics 355 12.2.3 Output Characteristics 35712.3 Shielded Trench-Gate MOSFET: Experimental Results 35812.4 Summary 360 References 361Chapter 13 Charge Coupled Structures 36313.1 Charge Coupled Silicon Carbide Structures 36413.2 Ideal Specific On-Resistance 36713.3 Charge Coupled Schottky Rectifier Structure 371 13.3.1 Blocking Characteristics 372 13.3.20n-State Characteristics 37713.4 Enhanced Charge Coupled Schottky Rectifier Structure 379 13.4.1 Blocking Characteristics 380 13.4.20n-State Characteristics 385 13.4.3 Charge Optimization 386 13.4.4Charge Imbalance 39013.5 Charge Coupled JFET Structure 394 13.5.1 Blocking Characteristics 396 13.5.20n-State Characteristics 399 13.5.3 Output Characteristics 40313.6 Shielded Charge Coupled MOSFET Structure 404 13.6.1 Blocking Characteristics 406 13.6.2 On-State Characteristics 410 13.6.3 Output Characteristics 417 13.6.4 Switching Characteristics 41813.7 Summary 421 References 422
  • 22. Contents xxiChapter 14 Integral Diodes 42514.1 Trench-Gate MOSFET Structure 42714.2 Shielded Trench-Gate MOSFET Structure 43314.3 Planar Shielded ACCUFET Structure 43914.4 Charge Coupled MOSFET Structure 44114.5 Summary 444 References 445Chapter 15 Lateral High Voltage FETs 44715.1 Fundamental Analysis 44815.2 Lateral High Voltage Buried Junction FET Structure 45015.3 Lateral High Voltage MESFET Structure 45215.4 Lateral High Voltage MOSFET Structure 45315.5 Lateral MOSFET Structure with Field Plates 45715.6 Lateral High Voltage Shielded MOSFET Structure 46115.7 Lateral High Voltage MOSFET Structure Optimization 46515.8 Lateral HV-MOSFET Structure: Experimental Results 47115.9 Summary 472 References 474Chapter 16 Synopsis 47716.1 Typical Motor Control Application 47816.2 Motor Control Application: Silicon IGBT and P-i-N Rectifier ..48316.3 Motor Control Application: Silicon IGBT and SiC Rectifier 48616.4 Motor Control Application: SiC MOSFET and Rectifier 48816.5 Motor Control Application: Comparison of Cases 48916.6 Summary 490 References .491Index 493
  • 23. Chapter 1 IntroductionThe increasing dependence of modern society on electrical appliances forcomfort, transportation, and healthcare has motivated great advances inpower generation, power distribution and power managementtechnologies. These advancements owe their allegiance to enhancementsin the performance of power devices that regulate the flow of electricity.After the displacement of vacuum tubes by solid state devices in the 1950s, the industry relied upon silicon bipolar devices, such as bipolarpower transistors and thyristors. Although the ratings of these devicesgrew rapidly to serve an ever broader system need, their fundamentallimitations in terms of the cumbersome control and protection circuitryled to bulky and costly solutions. The advent of MOS technology fordigital electronics enabled the creation of a new class of devices in the1970s for power switching applications as well. These silicon powerMOSFETs have found extensive use in high frequency applications withrelatively low operating voltages (under 100 volts). The merger of MOSand bipolar physics enabled creation of yet another class of devices in the1980s. The most successful innovation in this class of devices has beenthe Insulated Gate Bipolar transistor (IGBT). The high power density,simple interface, and ruggedness of the IGBT have made it thetechnology of choice for all medium and high power applications withperhaps the exception of high voltage DC transmission systems. Power devices are required for systems that operate over a broadspectrum of power levels and frequencies. In Fig. 1.1, the applicationsfor power devices are shown as a function of operating frequency. Highpower systems, such as HVDC power distribution and locomotive drives,requiring the control of megawatts of power operate at relatively lowfrequencies. As the operating frequency increases, the power ratingsdecrease for the devices with typical microwave devices handling about100 watts. All of these applications are served by silicon devices.Thyristors are favored for the low frequency, high power applications, l
  • 24. 2 SILICON CARBIDE POWER DEVICESIGBTs for the medium frequency and power applications, and powerMOSFETs for the high frequency applications. 10" HVDC POWER DISTRIBUTION _ io 7 t 106 ELECTRIC TRAINS I UNINTERRUPTIBLE POWER SUPPLY i, 105 •B IO 4 i W FLUORESCENT LAMPS o 2 TELEVISION SWEEP ! 10 V3 CELLULAR COMMUNICATION 1 10 MICROWAVE OVEN 10° I I I I JL -U 2 3 4 s 6 7 10 10 10 10 10 10 10 108 10 System Operating Frequency (Hz) Fig. 1.1 Applications for Power Devices. Another approach to classification of applications for powerdevices is in terms of their current and voltage handling requirements asshown in Fig. 1.2. On the high power end of the chart, thyristors areavailable that can individually handle over 6000 volts and 2000 amperesenabling the control of over 10 megawatts of power by a singlemonolithic device. These devices are suitable for the HVDC powertransmission and locomotive drive (traction) applications. For the broadrange of systems that require operating voltages between 300 volts and3000 volts with significant current handling capability, the IGBT hasbeen found to be the optimum solution. When the current requirementsfall below 1 ampere, it is feasible to integrate multiple devices on asingle monolithic chip to provide greater functionality for systems suchas telecommunications and display drives. However, when the currentexceeds a few amperes, it is more cost effective to use discrete power
  • 25. Introduction 3MOSFETs with appropriate control ICs to serve applications such asautomotive electronics and switch mode power supplies. 10 4 HVDC TRANSMISSION 10 3 ELECTRIC TRAINS I MOTOR ELECTRONICS 10 2 AUTOMOTIVE SUPPLIES DRIVES POWER 00 ROBOTICS 10 1 I LAMP BALLAST 10° u TELECOM. a U IO-1 DISPLAY DRIVES io-2 1 10 1 IO2 IO3 IO4 Voltage Rating (Volts) Fig. 1.2 System Ratings for Power Devices.1.1 Ideal and Typical Power Device CharacteristicsAlthough silicon power devices have served the industry for well overfive decades, they cannot be considered to have ideal devicecharacteristics. An ideal power rectifier should exhibit the i-vcharacteristics shown in Fig. 1.3. In the forward conduction mode, thefirst quadrant of operation the figure, it should be able to carry anyamount of current with zero on-state voltage drop. In the reverseblocking mode, the third quadrant of operation in the figure, it should beable to hold off any value of voltage with zero leakage current. Further,the ideal rectifier should be able to switch between the on-state and theoff-state with zero switching time. Actual silicon power rectifiers exhibitthe i-v characteristics illustrated in Fig. 1.4. They have a finite voltage
  • 26. 4 SILICON CARBIDE POWER DEVICESdrop (V 0 N) when carrying current on the on-state leading to conductionpower loss. They also have a finite leakage current (IOFF) when blockingvoltage in the off-state creating power loss. In addition, the dopingconcentration and thickness of the drift region of the silicon device mustbe carefully chosen with a design target for the breakdown voltage(BV)1. The power dissipation in power devices increases when theirvoltage rating is increased due to an increase in the on-state voltage drop. ON-STATE OFF-STATE Fig. 1.3 Characteristics of an Ideal Power Rectifier. Fig. 1.4 Characteristics of a Typical Power Rectifier.
  • 27. Introduction 5 The i-v characteristics of an ideal power switch are illustrated inFig. 1.5. As in the case of the ideal rectifier, the ideal transistor conductscurrent in the on-state with zero voltage drop and blocks voltage in theoff-state with zero leakage current. In addition, the ideal device canoperate with a high current and voltage in the active region with theforward current in this mode controlled by the applied gate bias. Thespacing between the characteristics in the active region is uniform for anideal transistor indicating a gain that is independent of the forwardcurrent and voltage. i ACTIVE ON-STATE . REGION / L / , / vG OFF-STATE / vF Fig. 1.5 Characteristics of an Ideal Transistor. The i-v characteristics of a typical power switch are illustrated inFig. 1.6. This device exhibits a finite resistance when carrying current inthe on-state as well as a finite leakage current while operating in the off-state (not shown in the figure because its value is much lower than theon-state current levels). The breakdown voltage of a typical transistor isalso finite as indicated in the figure with BV. The typical transistor canoperate with a high current and voltage in the active region. This currentis controlled by the base current for a bipolar transistor while it isdetermined by a gate voltage for a MOSFET or IGBT (as indicated in thefigure). It is preferable to have gate voltage controlled characteristicsbecause the drive circuit can be integrated to reduce its cost. The spacingbetween the characteristics in the active region is non-uniform for atypical transistor with a square-law behavior for devices operating with
  • 28. 6 SILICON CARBIDE POWER DEVICESchannel pinch-off in the current saturation mode1. Recently, devicesoperating under a new super-linear mode have been proposed anddemonstrated for wireless base-station applications2. ACTIVE REGION Increasing Fig. 1.6 Characteristics of a Typical Transistor.1.2 Unipolar Power DevicesBipolar power devices operate with the injection of minority carriersduring on-state current flow. These carriers must be removed when theswitching the device from the on-state to the off-state. This isaccomplished by either charge removal via the gate drive current or viathe electron-hole recombination process. These processes introducesignificant power losses that degrade the power management efficiency.It is therefore preferable to utilize unipolar current conduction in a powerdevice. The commonly used unipolar power diode structure is theSchottky rectifier that utilizes a metal-semiconductor barrier to producecurrent rectification. The high voltage Schottky rectifier structure alsocontains a drift region, as show in Fig. 1.7, which is designed to supportthe reverse blocking voltage. The resistance of the drift region increasesrapidly with increasing blocking voltage capability as discussed later inthis chapter. Silicon Schottky rectifiers are commercially available withblocking voltages of up to 100 volts. Beyond this value, the on-statevoltage drop of silicon Schottky rectifiers becomes too large for practical
  • 29. Introduction 7applications1. Silicon P-i-N rectifiers are favored for designs with largerbreakdown voltages due to their lower on-state voltage drop despite theirslower switching properties. As shown later in the book, silicon carbideSchottky rectifiers have much lower drift region resistance enablingdesign of very high voltage devices with low on-state voltage drop. SCHOTTKY CONTACT METAL (ANODE) Y////SSSSSSA DRIFT REGION SUBSTRATE V//////////A OHMIC CONTACT METAL (CATHODE) Fig. 1.7 The Power Schottky Rectifier Structure and its Equivalent Circuit. The most commonly used unipolar power transistor is the siliconpower Metal-Oxide-Semiconductor Field-Effect-Transistor or MOSFET.Although other structures, such as JFETs or SITs have been explored3,they have not been popular for power electronic applications because oftheir normally-on behavior. The commercially available silicon powerMOSFETs are based upon the structures shown in Fig. 1.8. The D-MOSFET was first commercially introduced in the 1970s and contains aplanar-gate structure. The P-base region and the N+ source regions areself-aligned to the edge of the Polysilicon gate electrode by using ion-implantation of boron and phosphorus with their respective drive-inthermal cycles. The n-type channel is defined by the difference in thelateral extension of the junctions under the gate electrode. The devicesupports positive voltage applied to the drain across the P-base/N-driftregion junction. The voltage blocking capability is determined by thedoping and thickness of the drift region. Although low voltage (< 100 V)silicon power MOSFET have low on-resistances, the drift region
  • 30. SILICON CARBIDE POWER DEVICESresistance increases rapidly with increasing blocking voltage limiting theperformance of silicon power MOSFETs to below 200 volts. It iscommon-place to use the Insulated Gate Bipolar Transistors (IGBT) forhigher voltage designs. D-MOSFET U-MOSFET SOURCE SOURCE GATE W£3%$& N+ Z7 N-DRIFT REGION N-DRIFT REGION N+ SUBSTRATE N+ SUBSTRATE V////////////A DRAIN V////////////A DRAIN Fig. 1.8 Silicon Power MOSFET Structures. The silicon U-MOSFET structure became commerciallyavailable in the 1990s. It has a gate structure embedded within a trenchetched into the silicon surface. The N-type channel is formed on the side-wall of the trench at the surface of the P-base region. The channel lengthis determined by the difference in vertical extension of the P-base and N"1"source regions as controlled by the ion-implant energies and drive timesfor the dopants. The silicon U-MOSFET structure was developed toreduce the on-state resistance by elimination of the JFET componentwithin the D-MOSFET structure1.1.3 Bipolar Power DevicesThe commonly available silicon power bipolar devices are the bipolartransistor and the gate turn-off thyristor or GTO. These devices wereoriginally developed in the 1950s and widely used for power switchingapplications until the 1970s when the availability of silicon power
  • 31. Introduction 9MOSFETs and IGBTs supplanted them. The structures of the bipolartransistor and GTO are shown in Fig. 1.9. In both devices, injection ofminority carriers into the drift region modulates its conductivity reducingthe on-state voltage drop. However, this charge must be subsequentlyremoved during switching resulting in high turn-off power losses. Thesedevices require a large control (base or gate) current which must beimplemented with discrete components leading to an expensive bulkysystem design. Bipolar Transistor GTO BASE EMITTER GATE CATHODE i mm P N+ N-DRIFT REGION N-DRIFT REGION N+ SUBSTRATE P+ SUBSTRATE W//////////A COLLECTOR ///////////A ANODE Fig. 1.9 Silicon Bipolar Device Structures. Several groups have worked on the development of bipolartransistors4,56,7 and GTOs8,9 using silicon carbide. The large junctionpotential for silicon carbide results in a relatively high on-state voltagedrop for these devices when compared with commercially availablesilicon devices. For this reason, the focus of this book is on unipolarsilicon carbide structures.1.4 MOS-Bipolar Power DevicesThe most widely used silicon high voltage (>300 volt) device for powerswitching applications is the Insulated Gate Bipolar Transistor (IGBT)
  • 32. 10 SILICON CARBIDE POWER DEVICESwhich was developed in the 1980s by combining the physics of operationof bipolar transistors and MOSFETs10. The structure of the IGBT isdeceptively similar to that for the power MOSFET as shown in Fig. 1.10if viewed as a mere replacement of the N+ substrate with a P + substrate.This substitution creates a four-layer parasitic thyristor which can latchup resulting in destructive failure due to loss of gate control. Fortunatelythe parasitic thyristor can be defeated by the addition of the P+ regionwithin the cell1. The benefit of the P+ substrate is the injection ofminority carriers into the N-drift region resulting in greatly reducing itsresistance. This has enabled the development of high voltage IGBTproducts with high current carrying capability. D-MOS IGBT U-MOS IGBT EMITTER EMITTER GATE N-DRIFT REGION N-DRIFT REGION P+SUBSTRATE P+ SUBSTRATE V/////////////A Y/////////////A COLLECTOR COLLECTOR Fig. 1.10 IGBT Device Structures. The development of the IGBT in silicon carbide has beenanalyzed and attempted by a few research groups111213. The largejunction potential and high resistance of the P+ substrate for siliconcarbide results in a relatively high on-state voltage drop for these deviceswhen compared with commercially available silicon devices. Theirswitching speed is also compromised by the injected stored charge in theon-state. For these reasons, silicon carbide based IGBTs are notdiscussed in this book.
  • 33. Introduction 111.5 Ideal Drift Region for Unipolar Power DevicesThe unipolar power devices discussed above all contain a drift regionwhich is designed to support the blocking voltage. The properties(doping concentration and thickness) of the ideal drift region can beanalyzed by assuming an abrupt junction profile with high dopingconcentration on one side and a low uniform doping concentration on theother side, while neglecting any junction curvature effects by assuming aparallel-plane configuration. The resistance of the ideal drift region canthen be related to the basic properties of the semiconductor material14. ANODE ELECTRIC FIELD V///////////A DRIFT REGION Wn SUBSTRATE Y//////////M CATHODE Fig. 1.11 The Ideal Drift Region and its Electric Field Distribution. The solution of Poissons equation leads to a triangular electricfield distribution within a uniformly doped drift region1 with the slope ofthe field profile being determined by the doping concentration. Themaximum voltage that can be supported by the drift region is determinedby the maximum electric field (Em) reaching the critical electric field (Ec)for breakdown for the semiconductor material. The critical electric fieldfor breakdown and the doping concentration then determine themaximum depletion width (WD). The specific resistance (resistance per unit area) of the ideal driftregion is given by:
  • 34. 12 SILICON CARBIDE POWER DEVICES ( wD on.sp [1.1] W„ND.Since this resistance was initially considered to be the lowest valueachievable with silicon devices, it has historically been referred to as theideal specific on-resistance of the drift region. More recent introductionof the charge-coupling concept, described later in this chapter, hasenabled reducing the drift region resistance of silicon devices to belowthe values predicted by this equation. The depletion width underbreakdown conditions is given by: WD=-— [1.2] E cwhere BV is the desired breakdown voltage. The doping concentration inthe drift region required to obtain this breakdown voltage is given by: s ND = c [ 1.3] D 2.q.BVCombining these relationships, the specific resistance of the ideal driftregion is obtained: 4BV2 "on-ideal ~ ^3 *• * £ S^n^CThe denominator of this equation (es.|i.n-Ec3) is commonly referred to asBaligas Figure of Merit for Power Devices. It is an indicator of theimpact of the semiconductor material properties on the resistance of thedrift region. The dependence of the drift region resistance on the mobility(assumed to be for electrons here because in general they have highermobility values than for holes) of the carriers favors semiconductors suchas Gallium Arsenide. However, the much stronger (cubic) dependence ofthe on-resistance on the critical electric field for breakdown favors wideband gap semiconductors such as silicon carbide. The critical electricfield for breakdown is determined by the impact ionization coefficientsfor holes and electrons in semiconductors as discussed in the nextchapter. The change in the specific on-resistance for the drift region withcritical electric field and mobility is shown in Fig. 1.12 for the case of abreakdown voltage of 1000 volts. The location of the properties for
  • 35. Introduction 13silicon, gallium arsenide, and silicon carbide are shown in the figure bythe points. The improvement in drift region resistance for GaAs incomparison with silicon is largely due to its much greater mobility forelectrons. The improvement in drift region resistance for SiC incomparison with silicon is largely due to its much larger critical electricfield for breakdown. Based upon these considerations, excellent highvoltage Schottky rectifiers were developed from GaAs in the 1980s15.Much greater improvement in performance is clearly indicated for siliconcarbide devices which is the subject of this book. 10 1 I I I I I I I I I I Breakdown Voltage = 1000 V 10° fcSi | 10-1 ^ = 1000 cm2/Vs M obility I I I I I u Gc I A S ^ c 10-2 - Mobility = 2000 c m W s a 10 "to 10-3 0) SiC a. _ Mobility = 4000 cm2/V S c 10-« O I I I I I ! o IE Mobility = 8000 cm2/Vs 5 10-5 o Q. 10"6 10 5 10 6 W Critical Electric Field for Breakdown (V/cm) Fig. 1.12 Specific On-Resistance of the Ideal Drift Region.1.6 SummaryThe motivation for the development of silicon carbide unipolar deviceshas been reviewed in this chapter. Although excellent unipolar siliconSchottky rectifiers and power MOSFETs are commercially availablewith breakdown voltages below 200 volts, the resistance of their driftregion increases rapidly at higher breakdown voltages producingsignificant power losses in applications. This problem can be overcomeusing silicon carbide based unipolar devices.
  • 36. 14 SILICON CARBIDE POWER DEVICESReferences1 B.J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.2 B. J. Baliga, "Silicon RF Power Devices", World Scientific Press,2005.3 B. J. Baliga, "Modern Power Devices", John Wiley and Sons, 1987.4 E. Danielsson, et al, "Extrinsic base design of SiC bipolar transistors",Silicon Carbide and Related Materials, pp. 1117-1120, 2003.5 I. Perez-Wurfll, et al, "Analysis of power dissipation and hightemperature operation in 4H-SiC Bipolar Junction Transistors", SiliconCarbide and Related Materials, pp. 1121-1124, 2003.6 J. Zhang, et al, "High Power (500V-70A) and High gain(44-47) 4H-SiC Bipolar Junction Transistors", Silicon Carbide and RelatedMaterials, pp. 1149-1152, 2003.7 A. Agarwal, et al, "SiC BJT Technology for Power Switching and RfApplications", Silicon Carbide and Related Materials 2003, pp. 1141- 1144,2004.8 P. Brosselard, et al, "Influence of different peripheral protections onthe breakover voltage of a 4H-SiC GTO thyristor", Silicon Carbide andRelated Materials, pp. 1129-1132, 2003.9 A.K. Agarwal, et al, "Dynamic Performance of 3.1 kV 4H-SiCAsymmetrical GTO Thyristors", Silicon Carbide and Related Materials,pp.1349-1352, 2003.10 B. J. Baliga, "Evolution of MOS-Bipolar Power SemiconductorTechnology", Proceedings of the IEEE, pp. 409-418, 1988.11 T.P. Chow, N. Ramaungul, and M. Ghezzo, "Wide BandgapSemiconductor Power devices", Materials Research Society Symposium,Vol. 483, pp. 89-102, 1998.12 R. Singh, "Silicon Carbide Bipolar power Devices - Potentials andLimits", Materials Research Society Symposium, Vol. 640, pp. H4.2.1-12, 2001.13 J. Wang, et al, "Comparison of 5kV 4H-SiC N-channel and P-channelIGBTs", Silicon Carbide and Related Materials, pp. 1411-1414, 2000.14 B. J. Baliga, "Semiconductors for High Voltage Vertical ChannelField Effect Transistors", J. Applied Physics, Vol. 53, pp. 1759-1764,1982.15 B. J. Baliga, et al, "Gallium Arsenide Schottky Power Rectifiers",IEEE Transactions on Electron Devices, Vol. ED-32, pp. 1130-1134,1985.
  • 37. Chapter 2 Material Properties and TechnologyIn the previous chapter, it was demonstrated the resistance of the driftregion in unipolar vertical power devices is strongly dependent upon thefundamental properties of the semiconductor material. In this chapter, themeasured properties for silicon carbide are reviewed and compared withthose for silicon. These properties are then used to obtain otherparameters (such as the built-in potential) which are relevant to theanalysis of the performance of devices discussed in the rest of the book.The discussion is constrained to the 4H poly-type of silicon carbidebecause its properties are superior to those reported for the 6H poly-type.The parameters given in this chapter were used during two-dimensionalnumerical simulations to determine the characteristics of various devicesdiscussed in this book. Data on the 6H poly-type is sometimes includedto demonstrate the reasons that the 4H poly-type is preferred for powerdevice structures. The 4H-SiC material is commercially available fromseveral sources for the development and manufacturing of power devicesbecause of its superior properties. Manufacturers are continuallyreducing the micropipe density in this material while increasing thediameter of commercially available wafers. The second portion of this chapter provides a review of thetechnology developed for the fabrication of silicon carbide powerdevices. One of the advantages of silicon carbide is that, unlike galliumarsenide, its processing is compatible with silicon devices without theproblem of contamination of production lines. It is advantageous toimplement any available silicon process technologies, such as ion-implantation or reactive ion etching, to the fabrication of silicon carbidedevices. This approach has been generally successful with the exceptionof the need to anneal the implants at much higher temperatures.Empirical studies performed on the oxidation and passivation of thesilicon carbide surface, as well those on the formation of metal-contacts,are also reviewed in this portion of the chapter. 15
  • 38. 16 SILICON CARBIDE POWER DEVICES2.1 Fundamental PropertiesThis section provides a summary of the fundamental properties of siliconcarbide1,2,3 and compares them with those for silicon4. Only theproperties for the 4H poly-type have been included here as discussedabove. The basic properties of relevance to power devices are the energyband gap, the impact ionization coefficients, the dielectric constant, thethermal conductivity, the electron affinity, and the carrier mobility. Sincethe intrinsic carrier concentration and the built-in potential can beextracted by using this information, their values have also beencomputed and compared with those for silicon in this section. Properties Silicon 4H-SiC Energy Band Gap 1.10 3.26 (eV) Relative Dielectric 11.7 9.7 Constant Thermal Conductivity 1.5 3.7 (W/cm K) Electron Affinity 4.05 3.7 (eV) Density of States Conduction Band 2.80 x 1019 1.23 x 101 (cm"3) Density of States Valence Band 1.04 x 101 4.58 x 1018 (cm"3) Fig. 2.1 Fundamental Material Properties.
  • 39. Material Properties and Technology 172.1.1 Energy Band GapThe energy band gap of silicon carbide is much larger than that forsilicon allowing its classification as a wide band gap semiconductor. Theband gap for 4H-SiC is 3.26 eV, which is 3 times larger than that forsilicon. The band gap for 6H-SiC of 3.0 eV is slightly smaller. Since alarger band gap results in a smaller generation of carriers in the depletionregions of devices, it is favorable for reducing the leakage current ofdevices which utilize P-N junctions to support voltages. The larger bandgap is also favorable for producing Metal-Semiconductor contacts withlarger Schottky barrier heights. This enables reduction of the leakagecurrent in Schottky rectifiers and MESFETs. The intrinsic carrier concentration is determined by the thermalgeneration of electron hole pairs across the energy band gap of asemiconductor. Its value can be calculated by using the energy band gap(EG) and the density of states in the conduction (Nc) and valence (N v )bands: n. = ^ = pc.Nve-(Eo2kT) [ 2.1]where k is Boltzmanns constant (1.38 x 10"23 J/°K) and T is the absolutetemperature. For silicon, the intrinsic carrier concentration is given by: n, = 3.87xl0 1 6 r 3 , V ( ™ 2 * 1 ° 3 ) / 7 [2.2]while that for 4H-SiC, it is given by: n, = 1 . 7 0 x l 0 1 6 r 3 / V ( 2 0 8 * l o V r [2.3]Using these equations, the intrinsic carrier concentration can becalculated as a function of temperature. The results are plotted in Fig. 2.2and Fig. 2.3. The traditional method for making this plot is shown in Fig.2.2 by using an inverse temperature scale for the x-axis. The additionalFig. 2.3 is provided here because it is easier to relate the value of theintrinsic carrier concentration to the temperature with it plotted on the x-axis. It is obvious that the intrinsic carrier concentration for siliconcarbide is far smaller than for silicon due to the large difference in bandgap energy. At room temperature (300°K), the intrinsic carrierconcentration for silicon is 1.4 x 1010 cm"3 while that for 4H-SiC is only6.7 x 1 0 " cm 3 . This demonstrates that the bulk generation current isnegligible for the determination of the leakage current in silicon carbide
  • 40. 18 SILICON CARBIDE POWER DEVICESdevices. Surface generation currents may be much larger due to thepresence of states within the band gap. <5i * • I 4H-SIC V * • . 6H •SiC ^^^ * *» ^^^ * ^^ * 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1000/Temperature (1/K) Fig. 2.2 Intrinsic Carrier Concentration. ^-—" . *•- -** Si , " ».- ^ 1 —* 6H- SiC . ,* ^ 4 H SiC * * ^^ • > 300 350 400 450 500 550 600 650 700 Temperature (K) Fig. 2.3 Intrinsic Carrier Concentration.
  • 41. Material Properties and Technology 19 For silicon, the intrinsic carrier concentration becomes equal to atypical doping concentration of 1 x 1015 cm3 at a relatively lowtemperature of 540 °K or 267 °C. In contrast, the intrinsic carrierconcentration for 4H-SiC is only 3.9 x 107 cm"3 even at 700 °K or 427 °C.The development of mesoplasmas has been associated with the intrinsiccarrier concentration becoming comparable to the doping concentration5.Mesoplasmas create current filaments that have very high current densityleading to destructive failure in semiconductors. This is obviously muchless likely in silicon carbide. The built-in potential of P-N junctions can play an important rolein determining the operation and design of power semiconductor devices.As an example, the built-in potential determines the zero-bias depletionwidth which is important for calculation of the on-resistance in powerDMOSFETs. It has a strong impact on the on-state voltage drop in JBSrectifiers, and is an important parameter used for the design of normally-off accumulation mode MOSFETs. These structures are discussed indetail later in the book. The built-in voltage is given by: l y Auy D y«=—In [2.4]where NA" and ND+ are the ionized impurity concentrations on the twosides of an abrupt P-N junction. For silicon, their values are equal to thedoping concentration because of the small dopant ionization energylevels. This does not apply to silicon carbide because of the much largerdopant ionization levels as discussed later in this chapter. The calculated built-in potential is shown in Fig. 2.4 as afunction of temperature for a typical operating range for power devices.In making the plots, the product (NA".ND+) was assumed to be 1035 cm"6.This would be applicable for a typical doping concentration of 1 x 1019cm"3 on the heavily doped side of the junction and 1 x 1016 cm3 on thelightly doped side of the junction. The built-in potential for siliconcarbide is much larger than that for silicon due to the far smaller valuesfor the intrinsic carrier concentration. This can be a disadvantage due tothe larger zero bias depletion width for silicon carbide as shown later inthe chapter. As an example, the larger zero bias depletion widthconsumes space within the D-MOSFET cell structure increasing the on-resistance by constricting the area through which current can flow. Incontrast, the larger built-in potential for SiC and its associated larger zerobias depletion width can be taken advantage of in making innovative
  • 42. 20 SILICON CARBIDE POWER DEVICESdevice structures, such as the ACCUFET, that are tailored to the uniqueproperties of SiC. — i > 4H-SiC 3.0 6H-SiC 1 OH 2.0 •a C Si .9 250 300 350 400 450 500 550 600 650 Temperature (K) Fig. 2.4 Built-in Potential for a P-N Junction in Si and SiC. 102 g 10 I 10° 4H-SiC Si 10 i io-2 10" 1014 10" 10" 10" Doping Concentration (cm"3) Fig. 2.5 Zero-Bias Depletion Width in Si and SiC. The calculated zero bias depletion width is shown in Fig. 2.5 as afunction of the doping concentration on the lightly doped side of the
  • 43. Material Properties and Technology 21abrupt P-N junction. For the case of silicon, three lines are given for300°K, 400°K and 500°K with largest depletion width corresponding tothe lowest temperature. For silicon carbide, the lines for thesetemperatures are very close to each other. For both silicon and siliconcarbide, it can be seen that the zero bias depletion width can besubstantial in size at low doping concentrations making it important totake this into account during device design and analysis. The zero biasdepletion width for SiC is much (about 2x) larger than for silicon for thesame doping concentration. However, it is worth noting that the dopingconcentration in SiC is also much greater for a given breakdown voltagethan for silicon as discussed later in the chapter.2.1.2 Impact Ionization CoefficientsThe main advantage of wide band gap semiconductors for power deviceapplications is the greater breakdown voltage capability of thesematerials. The higher breakdown voltage for these materials is associatedwith the reduced impact ionization coefficients at any given electric fieldwhen compared with silicon. The impact ionization coefficients forsemiconductors is dictated by Chynoweths Law67: a = a.eb/E [2.5]where E is the electric field component in the direction of current flow.The parameters a and b are constants that depend upon thesemiconductor material and the temperature. For silicon, the impactionization rate is much larger for electrons than for holes. However, forsilicon carbide the opposite has been found to hold true. For silicon, theimpact ionization rates have been measured as a function of electric fieldand temperature489. The data can be modeled by using a = 7 x 105 percm and b = 1.23 x 106 V/cm at room temperature10. The impact ionization coefficients for silicon carbide have beenrecently measured as a function of temperature by using an electronbeam excitation method". This method allowed extraction of impactionization rates in defect free regions of the material by isolating diodescontaining defects with an EBIC (Electron Beam induced Current)image. This was important because substantially enhanced impactionization rates were discovered when the measurements were conductedat defect sites12. For defect free material, the extracted values for theimpact ionization coefficient parameters for holes in 4H-SiC were foundto be:
  • 44. 22 SILICON CARBIDE POWER DEVICES a(4H - SiC) = 6.46*10 6 - 1.07;cl04:r [ 2.6]with b(4H-SiC) = 1.15x10" [2.7]while for 6H-SiC: a(6H - SiC) = 4.6*10 6 - lAxlQ3 T [ 2.8]with b(6H-SiC) = l.5xl01 [2.9] 104 ^ / ~/ T Si 103 / - B •B 4H-SiC 10* 10 105 106 10 Electric Field (V/cm) Fig. 2.6 Impact Ionization Coefficients in 4H-SiC and Silicon. The impact ionization coefficients for 4H-SiC can be comparedwith those for silicon in Fig. 2.6. This behavior was incorporated in theanalytical models used for two-dimensional numerical simulations ofdevice structures discussed later in the book. It can be seen that the onsetof significant generation of carriers by impact ionization occurs at muchlarger electric fields in 4H-SiC when compared with silicon. As aconsequence, breakdown in 4H-SiC devices occurs when the electricfields are in the range of 2-3 x 106 V/cm - an order of magnitude largerthan that for silicon. This implies a much larger critical electric field Ec
  • 45. Material Properties and Technology 23for breakdown for 4H-SiC resulting in a big increase in the BaligasFigure of Merit. The critical electric field for breakdown is discussed inmore detail in the next chapter.2.1.3 Electron MobilityThe mobility for electrons is larger than that for holes in silicon carbide.It is therefore favorable to make unipolar devices using N-type driftregions rather than P-type drift regions. The conductivity of the driftregion is given by: 1 Pn = [2.10] WnNDwhere ^ n by the mobility for electrons which is a function of dopingconcentration (ND) and temperature (T). 1600 1400 1200 1000 1 s o u i 3 1015 10" 10" 1018 10" -3 Doping Concentration (cm ) Fig. 2.7 Bulk Mobility for Electrons in 4H-SiC and Silicon. For silicon, the measured data13 for mobility of electrons at roomtemperature as a function of the doping concentration can be modeledby:
  • 46. 24 SILICON CARBIDE POWER DEVICES ,„. x 5.1(M0 1 8 +92A^ 9 1 [2.11] 3.15xl015 +N 0.91For silicon carbide, the mobility of electrons at room temperature as afunction of the doping concentration can be modeled by3: 4.05X1013 + 20N°D61 jUn(4H-SiC) = [2.12] 3.55xl0 lu + Nr0.61This behavior has also been theoretically modeled taking into accountacoustic and polar optical phonon scattering as well as intervalleyscattering14. The electron mobility at room temperature is plotted in Fig.2.7 as a function of doping concentration for silicon and silicon carbide.In both cases, the mobility decreases with increasing doping due toenhanced Coulombic scattering of electrons by the ionized donors. Thisbehavior was incorporated in the analytical models used for two-dimensional numerical simulations of device structures discussed later inthe book. 1600 1400 1200 1000 800 Si o 600 s c 400 4H-SiC o w 200 300 400 500 Temperature (°K) Fig. 2.8 Bulk Mobility for Electrons in 4H-SiC and Silicon. The mobility decreases in semiconductors with increasingtemperature due to enhanced phonon scattering. This holds true for
  • 47. Material Properties and Technology 25silicon and 4H-SiC as shown in Fig. 2.8. For silicon, the temperaturedependence of the mobility at low doping concentrations can be modeledby15: ( T V2-42 //„ (Si) = 1360 [2.13] 300For 4H-SiC, the temperature dependence of the mobility at low dopingconcentrations can be modeled by3: . -2.70 / Mn(4H-SiC) = U40 [2.14] 300,This behavior was also incorporated in the analytical models used fortwo-dimensional numerical simulations of device structures discussedlater in the book. The variation of the mobility with temperature is shownin the above figure only up to 500 °K (227 °C). Although there isconsiderable interest in the performance of silicon carbide devices atmuch higher temperatures due to its wide band gap structure, theoperation of devices above 500 °K is problematic due to degradation ofthe ohmic contacts and the surface passivation.2.2 Other Properties Relevant to Power DevicesIn this section, other properties for 4H-SiC are provided, which arerequired for the analysis of power device structures. These properties arecompared with those for silicon whenever it is pertinent.2.2.1 Donor and Acceptor Ionization Energy LevelsIn silicon, the donor and acceptor ionization energy is small (50 meV)allowing the assumption that all the donors and acceptor impurities in thelattice are completely ionized at room temperature as well as at highertemperatures. This is not a valid assumption for silicon carbide due to therelatively larger ionization energies for donors and acceptors. The mostcommonly used donor in 4H-SiC is nitrogen which occupies Carbon sitesin the lattice. Its ionization energy is reported to be about 100 meV . Tocreate p-type 4H-SiC, the most commonly used acceptor impurity isAluminum with an ionization energy of about 200 meV1. At above roomtemperature, the ionized donor concentration is over ninety percent
  • 48. 26 SILICON CARBIDE POWER DEVICESallowing the approximation that the electron concentration is equal to thedonor concentration when calculating the resistivity of drift regions.2.2.2 Recombination LifetimesIn silicon, high voltage devices are designed to operate with the injectionof minority carriers into the drift region to reduce its resistivity by theconductivity modulation phenomenon10. The recombination of holes andelectrons plays an important role in determining the switching speed ofthese structures. The recombination process can occur from band-to-bandbut is usually assisted by the presence of deep levels in the band gap. Thedeep levels can also produce leakage current during reverse blocking inpower devices by the generation of carriers in the depletion region. As already pointed out, for silicon carbide, it is appropriate toonly consider unipolar devices for power switching applications. This isfortunate because the lifetime values reported for this material isrelatively low (10 9 to 10"7 seconds)3. This is consistent with diffusionlengths of between 1 and 2 microns measured by using the EBICtechnique16. It is likely that these low lifetime and diffusion lengths areassociated with surface recombination. The performance of bipolardevices made from 4H-SiC, such as high voltage P-i-N rectifiers,indicates that higher values of bulk lifetime are applicable17. However,the large on-state voltage drop and slow switching speed of these devicesmakes them much less attractive for applications than unipolar devices.2.2.3 Metal-Semiconductor ContactsContacts to power devices are made by using metal films deposited onthe surface of its semiconductor layers. A common requirement is tomake ohmic contacts to n-type and p-type regions. This can be achievedby using a metal-semiconductor contact with low barrier height and ahigh doping concentration in the semiconductor to promote tunnelingcurrent across the contact. For metal-semiconductor contacts with highdoping level in the semiconductor, the contact resistance determined bythe tunneling process is dependent upon the barrier height and the dopinglevel18:
  • 49. Material Properties and Technology 27In order to take full advantage of the low specific on-resistance of thedrift region in silicon carbide devices, it is important to obtain a specificcontact resistance that is several orders of magnitude smaller than that ofthe drift region. This is also necessary because the contact areas are oftenonly a small fraction (less than 10 percent) of the active area of mostpower device structures. Typically, specific contact resistances of lessthan 1 x 10"5 ohm-cm 2 are desirable to n-type regions. 0.8 eV io-1 u a S 3 -1 io- 0.6 eV i io-! 0.4 eV !7J io-7 10" 10 2 0 3 Surface Doping Concentration (cm ) Fig. 2.9 Specific Resistance at Metal-Semiconductor Contacts. The specific contact resistance calculated using the aboveformula is plotted in Fig. 2.9 as a function of the doping concentrationusing the barrier height as a parameter. Unfortunately, the barrier heightsof metal contacts to silicon carbide tend to be large due to its wide bandgap. From the figure, it can be concluded that a specific contactresistance of 1 x 10"5 ohm-cm 2 can be obtained for a dopingconcentration of 5 x IO19 cm"3 if the barrier height is 0.6 eV. Such highsurface doping concentrations can be achieved for N-type 4H-SiC byusing hot-implantation of nitrogen, phosphorus or arsenic followed byappropriate high temperature annealing 19 . Ohmic contacts with specificresistances of less than IO"6 Ohm-cm 2 have been reported to ion-implanted layers by using nickel and titanium .
  • 50. 28 SILICON CARBIDE POWER DEVICES Metal-semiconductor contacts can also be used to make Schottkybarrier rectifiers with high breakdown voltages by using silicon carbide.In this case, it is advantageous to have a relatively large barrier height toreduce the leakage current. The commonly used metals for formation ofSchottky barriers to 4H-SiC are Titanium and Nickel. The barrier heightsmeasured for these contacts range from 1.10 to 1.25 eV for Titanium and1.30 to 1.60 eV for Nickel21,2223. The use of these metals to fabricate highvoltage device structures is discussed in subsequent chapters of the book.2.3 Fabrication TechnologyDue to the substantial infrastructure available to fabricate silicon devices,it is advantageous to manufacture silicon carbide devices using the sametechnology platform. During the last fifteen years of research, it has beenestablished that silicon carbide devices can be fabricated using the sameequipment used for silicon devices in most instances. However, it hasbeen found that much higher temperatures are needed for the annealingof ion implanted regions in silicon carbide to activate the dopants andremove the damage. In addition, the design of device structures in siliconcarbide requires giving special consideration to the low diffusioncoefficients for impurities. These unique issues are discussed in thissection of the chapter.2.3.1 Diffusion Coefficients and Solubility of DopantsIn silicon power devices, it is common-place to drive the dopants afterion-implantation to increase the junction depth. The widely used double-diffused (DMOS) process for silicon power MOSFETs utilizes thedifference in the junction depth of the P-base and N* source regions todefine the channel length without relying upon high resolutionlithography to achieve sub-micron dimensions10. In silicon carbide, thediffusion coefficients are very small even at relatively hightemperatures1. For nitrogen - the commonly used N-type dopant, theeffective diffusion coefficient is reported as 5 x 10"12 cm2/s even at 2450°C. For aluminum - the commonly used P-type dopant, the effectivediffusion coefficient is reported as 3 x 10"14 to 6 x 10"12 cm2/s even at1800 - 2000 °C. Due to the on-set of dissociation at these temperatureswith attendant generation of defects, it is not practical to drive dopants insilicon carbide after ion implantation. The design of power device
  • 51. Material Properties and Technology 29structures in silicon carbide must take this limitation in processtechnology into account. The solid solubility of dopants in silicon carbide has beenreported to be comparable to that for dopants in silicon1. For nitrogen andaluminum, the solubility is in excess of 1 x 1020 cm"3. Ion implantednitrogen24 and aluminum25 doped layers have been formed with impurityconcentrations ranging from 1 x 1019 cm"3 to 1 x 1020 cm"3. These valuesare sufficient for the fabrication of most high voltage power devicestructures.2.3.2 Ion Implantation and AnnealingA significant body of literature has developed on the ion implantation ofimpurities into silicon carbide and the subsequent annealing process toactivate the dopants and remove lattice damage. The reader should referto the proceeding of the conferences on Silicon Carbide and RelatedMaterials for an abundance of information on this topic. Although room temperature ion implantation can be successful,it has been found that hot-implantation produces a higher degree ofimpurity activation and a smaller number of defects. The hot-implantsare usually performed in the 500 °C range followed by anneals performedat between 1200 and 1600 °C. At above 1600 °C, degradation of thesilicon carbide surface is observed due to sublimation or evaporation19,25.The surface degradation can be mitigated by using a graphite boat to hostthe implanted wafer with another silicon carbide wafer placed on top(proximity anneals)26.2.3.3 Gate Oxide FormationSilicon bipolar power devices, such as the bipolar power transistor andthe gate turn-off thyristor (GTO), were supplanted with MOS-gateddevices in the 1980s. The silicon power MOSFET replaced the bipolartransistor for lower voltage (< 200 V) applications while the IGBTreplaced bipolar transistors and GTOs for high voltage (>200V)applications. The main advantage of these MOS-gated devicearchitectures was voltage controlled operation which greatly simplifiedthe control circuit making it amenable to integration10. This feature mustbe extended to silicon carbide power devices to make them attractivefrom an applications perspective.
  • 52. 30 SILICON CARBIDE POWER DEVICES The issues that must be considered for the gate dielectric inMOS-gated silicon carbide devices are the quality of the oxide-semiconductor interface and the ability of the oxide to withstand higherelectric fields than within silicon devices27. The quality of the oxide-semiconductor interface determines not only the channel mobility butimpacts the threshold voltage of the devices. The electric field in theoxide is related to the electric field in the semiconductor by GausssLaw: E«= — EMl~3Eiml [2.16]In silicon, the maximum electric field at breakdown is in the 3 x 105V/cm range. Consequently, the maximum electric field in the oxideremains well below its breakdown field strength of 107 V/cm. In contrast,the maximum electric field for breakdown in silicon carbide is in the 3 x 106 V/cm range. Consequently, the electric field in the oxide canapproach its breakdown strength and easily exceed a field of 3 x 106V/cm, which is considered to be the threshold for reliable operation. Oneapproach to overcome this problem is to use gate dielectric material witha larger permittivity2829. In these references, it has been theoreticallyshown that the specific on-resistance can be reduced by an order ofmagnitude by using high dielectric constant gate material. A permittivityof about 15 (versus 3.85 for silicon dioxide) was found to be adequate forallowing full use of the high electric field strength for breakdown insilicon carbide without problems with unacceptably high oxide electricfields. One example of such a dielectric is zirconium oxide30. A second approach utilizes improved device structuralarchitecture to screen the gate dielectric from the high electric fieldswithin the silicon carbide. This is discussed in detail in the chapters onshielded planar and shielded trench gate MOSFETs in this book. Suchdevices can then be made using silicon dioxide whose properties are wellunderstood. In this case, the silicon dioxide can be either grown by thethermal oxidation of silicon dioxide or by the formation of the oxideusing chemical vapor deposition processes. Many studies on both ofthese techniques are available in the literature. The thermal oxidation of SiC has been reviewed in the literatureand the growth rate of the oxide has been compared with that on siliconsurfaces31. Some selected data is shown in Fig. 2.10 to illustrate the muchlower growth rate of thermal oxide on SiC when compared with siliconfor both dry and wet oxidation conditions. The data shown in this figure
  • 53. Material Properties and Technology 31are for 6H-SiC but similar values are applicable to the 4H-SiCpolytype32. It is obvious that a much higher temperature and longer timeduration is required for the growth of oxides on silicon carbide. Thisoxide has been shown to be essentially silicon dioxide with no carbonincorporated in the film. The small amount of aluminum incorporatedinto the oxide, when grown on p-type SiC, has been found to have noadverse effect33,34 on the MOS properties. 10 2 i^esz 1 1 1—i I I I I ,1 1 1 1 1 I I I I I 2 10 10 103 Thermal Oxidation Time (minutes) Fig. 2.10 Comparison ofThermal Oxidation of SiC with silicon at 1200 °C. The gate dielectric produced with thermal oxidation of 6H-SiChas been found to be satisfactory for making MOSFETs with reasonableinversion layer mobility35. However, this method did not producesufficiently high quality interfaces on 4H-SiC to make MOSFETs. It wasdiscovered at PSRC that a low temperature oxide subjected to a wetnitrogen anneal enabled fabrication of n-channel inversion layerMOSFETs in 4H-SiC with an effective inversion layer mobility of 165cm2/Vs3637. Although the gate oxide for these MOSFETs was unusuallylarge (9000 angstroms), high performance MOSFETs with similarmobility values, were subsequently fabricated at PSRC using a gateoxide thickness of 850 angstroms38. At PSRC, an extensive evaluation ofprocess conditions was performed to determine their impact on theinversion layer mobility. This work has been validated by other groups .
  • 54. 32 SILICON CARBIDE POWER DEVICESIn addition, inversion layer mobility in the range of 50 cm2/V-s has beenreported on thermally grown oxides subjected to annealing in nitricoxide3140. These experiments indicate that power MOSFETs with lowspecific on-resistance can be developed from 4H-SiC.2.3.4 Reactive Ion Etching of TrenchesThe first silicon power MOSFETs were manufactured using the Double-diffused or DMOS process to form a planar gate architecture41. Althoughthese devices offered excellent input impedance and fast switchingperformance for low voltage (< 100 volt) applications, their on-resistancewas found to be limited by the presence of a JFET region. The JFETregion could be eliminated by adopting a trench gate or UMOS process10.The trench gate structure in the silicon power MOSFET is fabricated byusing reactive ion etching. An equivalent process for silicon carbide wasnot developed until the mid 1990s. Until then, alternative methods suchas etching with molten KOH solutions or the use of amorphization ofselective SiC regions was explored42. Reactive ion etching is the most convenient process forformation of trenches in silicon carbide enabling the fabrication ofdevices with processes compatible with silicon device manufacturingtechnology. Many gas compositions have been tried for the formation oftrenches in silicon carbide. For application to power devices, the trenchesshould have a nearly vertical profile with a slightly rounded bottom toreduce electric field enhancement. The trench surface must be smoothand free of damage in order to reduce interface states and obtain highmobility along the inversion channel formed on the trench sidewalls.Reactive ion etching using a SF(/02 mixture has been found to producetrenches that meet these requirements43. Other reactive ion etchingchemistries using fluorinated gases44 have also been reported to producetrenches with vertical profiles and smooth surfaces.2.4 SummaryThe properties of silicon carbide relevant to power devices have beenreviewed in this chapter. An improved knowledge of the impactionization coefficients has allowed projection of very high performancefor SiC based unipolar devices. The status of process technology for thefabrication of these unipolar devices has also been summarized here.
  • 55. Material Properties and Technology 33References1 G. L. Harris, "Properties of Silicon Carbide", DEE Inspec, 19952 M. Ruff, H. Mitlehner, and R. Helbig, "SiC Devices: Physics andNumerical Simulations", IEEE Transactions on Electron Devices, Vol.ED41, pp. 1040-1954, 1994.3 N.G. Wright, et al, "Electrothermal Simulation of 4H-SiC PowerDevices", Silicon Carbide, Ill-Nitrides, and Related Materials - 1997,Material Science Forum, Vol. 264, pp. 917-920, 1998.4 S.M. Sze, "Physics of Semiconductor Devices", John Wiley and Sons, 19815 S. K. Ghandhi, "Semiconductor Power Devices", John Wiley and Sons, 1977.6 A.G. Chynoweth, "Ionization Rates for Electrons and Holes in Silicon,Physical Review, Vol. 109, pp. 1537-1545, 1958.7 A. G. Chynoweth, "Uniform Silicon P-N Junctions II. Ionization ratesfor Electrons", J. Applied Physics, Vol. 31, pp 1161-1165, 1960.8 C. R. Crowell and S. M. Sze, "Temperature dependence of AvalancheMultiplication in Semiconductors", Applied Physics Letters, Vol. 9, pp242-244, 1966.9 R. Van Overstraeten and H. De Man, "Measurement of the IonizationRates in Diffused Silicon P-N Junctions", Solid State Electronics, Vol.13, pp. 583-590, 1970.10 B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.11 R. Raghunathan and B. J. Baliga, "Temperature dependence of HoleImpact Ionization Coefficients in 4H and 6H SiC", Solid StateElectronics, Vol. 43, pp. 199-211, 1999.12 R. Raghunathan and B. J. Baliga, "Role of Defects in producingNegative Temperature Dependence of Breakdown Voltage in SiC",Applied Physics Letters, Vol. 72, pp. 3196-3198, 1998.13 C. Jacobini, et al, "A Review of some Charge Transport Properties ofSilicon", Solid State Electronics, Vol. 20, pp. 77-89, 1977.14 H. Iwata and K. M. Itoh, "Theoretical Calculation of the Electron HallMobility in n-type 4H- and 6H-SiC", Silicon Carbide and RelatedMaterials - 1999, Materials Science Forum, Vol. 338-342, pp. 879-884,2000.15 C. Canali, et al, "Electron Drift Velocity in Silicon", Phys. Rev. Vol.B12, pp. 2265-2284, 1975
  • 56. 34 SILICON CARBIDE POWER DEVICES16 R. Raghunathan and B.J. Baliga, "EBIC Measurements of DiffusionLengths in Silicon Carbide", 38th Electronic Materials Conference, Abstr.1-6, 1996.17 R. Singh, "Silicon Carbide Bipolar Power Devices - Potentials andLimits", Material Research Society Proceedings, Vol. 640, pp. H4.2.1-H4-2-12, 2001.18 S.M. Sze, "Physics of Semiconductor Devices", page 304, John Wileyand Sons, 1981.19 S. Imai, et al, "Hot-Implantation of Phosphorus Ions into 4H-SiC",Silicon Carbide and Related Materials - 1999, Materials Science Forum,Vol. 338-342, pp. 861-864, 2000.20 S. Tanimoto, et al, "Ohmic Contact Structure and Fabrication ProcessApplicable to Practical SiC Devices", Silicon Carbide and RelatedMaterials - 2001, Materials Science Forum, Vol. 389-393, pp. 879-884,2002.21 A. Kestle, et al., "A UHV Study of Ni/SiC Schottky Barrier andOhmic Contact Formation", Silicon Carbide and Related Materials - 1999, Materials Science Forum, Vol. 338-342, pp. 1025-1028, 2000.22 K.V. Vassilevski, et al., "4H-SiC Schottky Diodes with high On/OffCurrent Ratio", Silicon Carbide and Related Materials - 2001, MaterialsScience Forum, Vol. 389-393, pp. 1145-1148, 2002.23 R. Raghunathan, D. Alok, and B.J. Baliga, "High Voltage 4H-SiCSchottky Barrier Diodes", IEEE Electron Device letters, Vol. EDL-16,pp. 226-227, 1995.24 S. Blanque, et al., "Room Temperature Implantation and ActivationKinetics of Nitrogen and Phosphorus in 4H-SiC crystals", SiliconCarbide and Related Materials - 2003, Materials Science Forum, Vol.457-460, pp. 893-896, 2004.25 Y. Negoro, et al, "Low Sheet Resistance of High Dose AluminumImplanted 4H-SiC using (1120) Face", Silicon Carbide and RelatedMaterials - 2003, Materials Science Forum, Vol. 457-460, pp. 913-916,2004.26 R.K. Chilukuri, P. Ananthanarayanan, V. Nagapudi, and B.J. Baliga,"High Voltage P-N Junction Diodes in Silicon Carbide using Field PlateEdge Termination", Material Research Society Proceedings, Vol. 572,pp. 81-86, 1999.27 B. J. Baliga, "Critical Nature of Oxide/Interface Quality for SiC PowerDevices", Microelectronics Engineering, Vol. 28, pp. 177-184, 1995.
  • 57. Material Properties and Technology 3528 S. Sridevan, P.K. McLarty, and B.J. Baliga, "Silicon CarbideSwitching Devices having Nearly Ideal Breakdown Voltage Capabilityand Ultra-Low On-State Resistance", U.S. Patent # 5,742,076, IssuedApril 21, 1998.29 S. Sridevan, P.K. McLarty, and B.J. Baliga, "Analysis of GateDielectrics for SiC Power UMOSFETs", IEEE Int. Symposium on PowerDevices and ICs, pp. 153-156, 1997.30 V.V. Afanasev, et al, "Oxidation of Silicon Carbide: Problems andSolutions", Silicon Carbide and Related Materials - 2001, MaterialsScience Forum, Vol. 389-393, pp. 961-966, 2002.31 J. A. Cooper, "Silicon Carbide MOSFETs", in Wide Energy BandgapElectronic Devices, Edited by F. Ren and J. C. Zolper, World ScientificPress, 2003.32 A. Golz, et al, "Oxidation Kinetics of 3C, 4H, and 6H silicon carbide",Silicon Carbide and Related Materials - 1995, Institute of PhysicsConference Series, Vol. 142, pp. 633-636, 1996.33 S. Sridevan, P.K. McLarty, and B.J. Baliga, "On the Presence ofAluminum in Thermally Grown Oxides on 6H-SiC", IEEE ElectronDevice Letters, Vol. 17, pp. 136-138,1996.34 G. Gudjonsson, et al, "High Field Effect Mobility in n-Channel SiFace 4H-SiC MOSFETs with Gate Oxide Grown on Aluminum Ion-Implanted Material", IEEE Electron Device Letters, Vol. 26, pp. 96-98,2005.35 L.A. Lipkin and J.W. Palmour, "Improved Oxidation Procedures forreduced Si02/SiC Defects". J. Electronic Materials, Vol. 25, pp. 909-915,1996.36 S. Sridevan and BJ. Baliga, "Lateral n-Channel Inversion Mode 4H-SiC MOSFETs", Silicon Carbide and Related Materials - 1997,Materials Science Forum, Vol. 264-268, pp. 997-1000, 1998.37 S. Sridevan and B.J. Baliga, "Lateral n-Channel Inversion Mode 4H-SiC MOSFETs", IEEE Electron Device Letters, Vol. 19, pp. 228-230, 1998.38 S. Sridevan and B.J. Baliga, "Phonon Scattering limited Mobility inSiC Inversion Layers", PSRC Technical Report, TR-98-03.39 D. Alok, E. Arnold, and R. Egloff, "Process dependence of InversionLayer Mobility in 4H-SiC Devices", Silicon Carbide and RelatedMaterials - 1999, Materials Science Forum, Vol. 338-342, pp. 1077- 1080,2000.
  • 58. 36 SILICON CARBIDE POWER DEVICES40 J.R. Williams, et al, "Passivation of the 4H-SiC/Si02 Interface withNitric Oxide", Silicon Carbide and Related Materials - 2001, MaterialsScience Forum, Vol. 389-393, pp. 967-972, 2002.41 D.A. Grant and J. Gowar, "Power MOSFETs", John Wiley and Sons,1989.42 D. Alok and B.J. Baliga, "A Novel Method for Etching Trenches inSilicon Carbide", J. Electronic Materials, Vol. 24, pp. 311-314, 1995.43 M. Kothandaraman, D. Alok, and B.J. Baliga, "Reactive Ion Etchingof Trenches in 6H-SiC", J. Electronic Materials, Vol. 25, pp. 875-878,1996.44 V. Saxena and A.J. Steckl, "Fast and Anisotropic Reactive Ion Etchingof 4H and 6H SiC in NF3", Silicon Carbide and Related Materials -1997, Materials Science Forum, Vol. 264-268, pp. 829-832, 1998.
  • 59. Chapter 3 Breakdown VoltageThe main advantage of a wide band gap semiconductor for power deviceapplications stems from the very low resistance of the drift region evenwhen it is designed to support larger voltages. The largest voltage thatcan be supported by a drift region is determined by the onset of impactionization with increasing electric field within the region. In the previouschapter, it was shown that the onset of impact ionization occurs at muchlarger electric fields in silicon carbide when compared with silicon. Inthis chapter, the design of the drift region is discussed and it isdemonstrated that its specific resistance is much smaller than for silicondevices designed to support the same voltage. In addition to the basicparallel plane junction, the influence of the edge termination design isanalyzed. The electric field in power devices is invariably enhanced at itsedges. Consequently, the edge termination design limits the maximumvoltage that can be supported by the device. The results of two-dimensional numerical simulations are used to elucidate the physics ofoperation within the structures.3.1 One-Dimensional Abrupt JunctionThe analysis of a one-dimensional abrupt junction can be used tounderstand the design of the drift region within power devices1. The caseof a P7N junction is illustrated in Fig. 3.1 where the P+ side is assumedto be very highly doped so that the electric field supported within it canbe neglected. When this junction is reverse-biased by the application of apositive bias to the N-region, a depletion region is formed in the N-region together with the generation of a strong electric field within it thatsupports the voltage. The Poissons equation for the N-region is thengiven by: 37
  • 60. 38 SILICON CARBIDE POWER DEVICES d2V d£ Q(x)_ qND [3.1] dx2 dxwhere Q(x) is the charge within the depletion region due to the presenceof ionized donors, e s is the dielectric constant for the semiconductor, q isthe electron charge, and ND is the donor concentration in the uniformlydoped N-region. Depletion Region N > x > x Fig. 3.1 Electric Field and Potential Distribution for an Abrupt Parallel-Plane P+N Junction.Integration of the above equation with the boundary condition that theelectric field must go to zero at the edge of the depletion region (i.e. atx=W) provides the electric field distribution: E(x) = -^(W-x) [3.2]The electric field has a maximum value of Em at the P+/N junction (x=0)and decreases linearly to zero at x=W. Integration of the electric field
  • 61. Breakdown Voltage 39distribution through the depletion region provides the potentialdistribution: V{x) = -?£±<Wx~) [3.3] £s 1This equation is obtained by using the boundary condition that thepotential is zero at x=0 within the P+ region. The potential variesquadratically as illustrated in the figure. The thickness of the depletionregion (W) is related to the applied reverse bias (Va): 2e,V W = AHTL [3 4] N V 1 DUsing these equations, the maximum electric field at the junction can beobtained: 1.-FP -sWhen the applied bias increases, the maximum electric field approachesvalues at which significant impact ionization begins to occur. Thebreakdown voltage is determined by the ionization integral becomingequal to unity: f CC.dx = 1 [ 3.6]where a is the impact ionization coefficient discussed in chapter 2. Inorder to obtain a closed form solution for the breakdown voltage, it isconvenient to use a power law behavior for the impact ionizationcoefficient in place of Chynoweths law. For silicon, this is usuallyperformed using the Fulops power law formula: aF{Si) = 1.^x10^ E1 [3.7]A fit to the 4H-SiC data provided in chapter 2 gives the equivalentBaligas power law formula for the impact ionization coefficient: aB(4H-SiC) = 3.9xlO42E1 [3.8]The impact ionization coefficient obtained by using these equations arecompared with those obtained using the Chynoweth formula in Fig. 3.2.
  • 62. 40 SILICON CARBIDE POWER DEVICES 10" ^kH =2 !_^_ a / / f f I 1 /i -4 n Si i fr 4H-^>^ o U =^hzpt- 1 yi a o — j/ - k Fulops •a « power law o 1 r^ for Silicon M i-* / Baligas «• <^JI § / I power law 11 f for 4H-SiC 1 1 I I I // // 101 5 10 10« 107 Electric Field (V/cm) Fig. 3.2 Impact Ionization Coefficients for Si and 4H-SiC using a Power Law.Using the power law equation, analytical solutions for the breakdownvoltage and the corresponding maximum depletion layer width can bederived: BVPP (AH - SiC) = 3.CM015N~D3/4 [3.9]and WPP(4H - SiC) = 1.82x10" N D 7 / 8 [3.10]The breakdown voltage is plotted in Fig. 3.3 as a function of the dopingconcentration on the lightly doped side of the junction. It is obvious thatit is possible to support a much larger voltage in 4H-SiC when comparedwith silicon for any given doping concentration. The ratio of thebreakdown voltage in 4H-SiC to that in silicon for the same dopingconcentration is found to be 56.2. It is also obvious from this figure thatfor a given breakdown voltage, it is possible to use a much higher dopingconcentration in the drift region for 4H-SiC devices when compared withsilicon devices. The ratio of the doping concentration in the drift regionfor a 4H-SiC device to that for a silicon device with the same breakdownvoltage is found to be 200.
  • 63. Breakdown Voltage 41 1013 1014 1015 1016 10" 3 Doping Concentration (cm )Fig. 3.3 Breakdown Voltage for Abrupt Parallel-Plane Junctions in Si and 4H-SiC. 1013 10"» 10ls 10" 10" Doping Concentration (cm"3) Fig. 3.4 Maximum Depletion Width at Breakdown in Si and 4H-SiC.
  • 64. 42 SILICON CARBIDE POWER DEVICES The maximum depletion width reached at the onset ofbreakdown is shown in Fig. 3.4 for silicon and 4H-SiC. For the samedoping concentration, the maximum depletion width in 4H-SiC is 6.8xlarger than that in silicon because it can sustain a much larger electricfield. However, for a given breakdown voltage, the depletion width in4H-SiC is smaller than for a silicon device because of the much largerdoping concentration in the drift region. This smaller depletion width, inconjunction with the far larger doping concentration, results in anenormous reduction in the specific on-resistance of the drift region in4H-SiC when compared with silicon. These values correspond to the maximum electric field at thejunction becoming equal to a critical electric field for breakdown, whichis given by: Ec {AH - SiC) = 3.3xl0 4 iV^ 8 [ 3.11]The critical electric field for 4H-SiC can be compared with that forsilicon using Fig. 3.5. For the same doping concentration, the criticalelectric field in 4H-SiC is 8.2x larger than in silicon. The larger criticalelectric field in 4H-SiC results in a much larger Baligas Figure of Merit. •C 105 I 1—I I I Mill 1—I I 1 Mill 1—I I I I Mil 1—I I I M i l l U 1013 10 u 101S 10" 10" Doping Concentration (cm 3 ) Fig. 3.5 Critical Electric Field for Breakdown in Si and 4H-SiC.
  • 65. Breakdown Voltage 43 The specific on-resistance of the drift region is related to thebreakdown voltage by equation [1.4] which is repeated here fordiscussion: 4BV2 R on,sp [3.12]A complete modeling of the specific on-resistance requires taking intoaccount the variation of the critical electric field and mobility on thedoping concentration, which varies as the breakdown voltage is changed.It is possible to do this by computing the doping concentration forachieving a given breakdown voltage and then using the equations forthe depletion width and mobility as a function of doping concentration toobtain the specific on-resistance: W, pp R on,sp [3.13] WnNDThe specific on-resistance projected for the drift region in 4H-SiCdevices by using the above method is compared with that for silicondevices in Fig. 3.6. The 4H-SiC values are about 2000 times smaller thanfor silicon devices for the same breakdown voltage. 1U* m ± i 101 4= L_LJ Si —r il =^ - V) •55 <u AU Ci/t H n-? <& • a io- 4 T li O <j c == 0 V a. m «3 10-7 102 103 104 Breakdown Voltage (Volts) Fig. 3.6 Specific On-Resistance of Drift Regions in 4H-SiC and Silicon.
  • 66. 44 SILICON CARBIDE POWER DEVICES3.2 Schottky Diode Edge TerminationsThe silicon Schottky diode is commonly used for power supply designsoperating at low voltages. It offers a much lower on-state voltage dropalbeit at a larger leakage current and reduced maximum operatingtemperature capability. The resistance of the drift region becomesprohibitive for silicon Schottky rectifiers at breakdown voltages above200 volts1. However, the much lower drift region resistance in siliconcarbide enables scaling the breakdown voltage to over 3000 volts whileobtaining reasonable on-state voltage drops. This is discussed in detail inthe next chapter. The realization of the full potential for a silicon carbideSchottky rectifier requires attainment of close to the ideal breakdownvoltage, i.e. the parallel-plane breakdown voltage. This requires properedge termination designs that are suitable for implementation in siliconcarbide as discussed in this section.3.2.1 Planar Schottky Diode Edge Termination SCHOTTKY BARRIER CONTACT V///////////A . N-DRIFT REGION N+ SUBSTRATE CATHODE Fig. 3.7 The Un-terminated Schottky Diode Structure.The first high voltage vertical Schottky barrier rectifiers were fabricatedat PSRC with the remarkably simple process of evaporating metalthrough a dot mask onto a silicon carbide surface after appropriatecleaning2. This structure, illustrated in Fig. 3.7, contains a sharp edge atthe periphery of the diode leading to electric field enhancement and
  • 67. Breakdown Voltage 45reduction of the breakdown voltage. To illustrate this phenomenon, two-dimensional numerical simulations were performed on a Schottky diodewith a drift region with doping concentration of 1 x 1016 cm"3. A metalwork function of 4.5 eV was used to form the Schottky barrier. Thediode was found to exhibit a breakdown voltage of 650 volts. A threedimensional view of the electric field for the un-terminated Schottkydiode is shown in Fig. 3.8 at a bias of 500 volts. It can be seen that thereis a sharp increase in the electric field at the edge of the metal leading tothe reduced breakdown voltage. Metal Edge Fig. 3.8 Electric Field distribution at the 4H-SiC un-terminated Schottky diode for a Reverse Bias of 500 volts.3.2.2 Planar Schottky Diode with Field Plate Edge TerminationThe breakdown voltage for the planar Schottky diode can be significantlyimproved by using a field plate at its periphery to reduce the electric fieldat the metal edge. This termination is illustrated in Fig. 3.9 with oxide asthe dielectric. Field plates have also been reported using silicon nitride asthe dielectric3. To understand the benefits of the field plate structure, theresults of two-dimensional numerical simulations are discussed here withvariations to the field plate length and the oxide thickness.
  • 68. SILICON CARBIDE POWER DEVICES SCHOTTKY BARRIER CONTACT FIELD PLATE E222ZZ2ZZZ2_ N-DRIFT REGION N» SUBSTRATE ///////////////////////////7777s CATHODEFig. 3.9 Schottky Diode Structure with Field Plate Termination. No Field Plato 20 25 Distance (microns) 10 micron Field Plate 10 15 20 25 Dislance (microns)Fig. 3.10 Potential Contours for Schottky Diode with Field Plate.
  • 69. Breakdown Voltage 47 The potential contours for the case of a field plate edgetermination using a length of 10 microns and an oxide thickness of 1micron are shown in Fig. 3.10 at a reverse bias of 500 volts. Thepotentials contours for the un-terminated diode are also shown in thisfigure for comparison at a reverse bias of 1000 volts. It can be seen thatthe depletion region spreads along the surface in the presence of the fieldplate reducing the potential crowding at point A. Consequently, thestructure with the field plate had a breakdown voltage of 1300 voltscompared with 650 volts for the un-terminated diode. The reduction inelectric field at the edge (point A) of the Schottky diode can be examinedin the three-dimensional view of the electric field provided in Fig. 3.11.The ratio of the peak electric field at point A to that in the middle of thediode is reduced to 2.3x in comparison with a ratio of 2.7x for the un-terminated diode. 10 micron Field Plate Metal Edge " Fig. 3.11 Electric Field distribution in the 4H-SiC Schottky diode with Field Plate for a Reverse Bias of 1000 volts. A further reduction of the electric field at the metal edge (pointA) can be obtained by reducing the oxide thickness. The electric fielddistribution for the case of an oxide thickness of 0.6 microns is shown inFig. 3.12. The peak electric field at the metal corner is now 2x of that inthe middle. This allowed the breakdown voltage to increase to 1430volts. A further reduction in oxide thickness leads to an even lower
  • 70. 48 SILICON CARBIDE POWER DEVICESelectric field at the metal corner as shown in Fig. 3.13. Unfortunately, theelectric field at the field plate edge (point B) now becomes larger than atpoint A leading to a reduction of the breakdown voltage to 840 volts. 0.6 micron Field Oxide Fig. 3.12 Electric Field distribution in the 4H-SiC Schottky diode with Field Plate for a Reverse Bias of 1000 volts. 0.2 micron Field Oxide Metal Edge { Field Plate Edge Fig. 3.13 Electric Field distribution in the 4H-SiC Schottky diode with Field Plate for a Reverse Bias of 500 volts.
  • 71. Breakdown Voltage 49 The variation of the breakdown voltage with field oxidethickness is plotted in Fig. 3.14. It is obvious that there is an optimumoxide thickness at which the breakdown voltage reaches a maximumvalue. It is also important to use a sufficient length (L) for the field plateas shown in Fig. 3.15. A length of 10 microns is adequate for thesimulated case. 1600 1400 ^^ Volts 1200 1000 tag o 800 > e 6(H) * o •o X « 400 M u 200 0 0.2 0.4 0.6 0.8 1.0 1.2 Field Oxide Thickness (microns) Fig. 3.14 Schottky Diode in 4H-SiC with Field Plate. 1400 • ^ « 1200 3 •© 1111)0 > o> tag 800 o > 600 a ? o 3 400 Field Oxide = 1 micron « u « 200 0 5 10 15 20 25 Field Plate Length (microns) Fig. 3.15 Schottky Diode in 4H-SiC with Field Plate.
  • 72. 50 SILICON CARBIDE POWER DEVICES3.2.3 Schottky Diode with Floating Metal Rings SCHOTTKY DIODE - MAIN CONTACT FLOATING METAL RING Y///////////A 777777Z N-DRIFT REGION N+ SUBSTRATE CATHODE Fig. 3.16 Schottky Diode Edge Termination with Floating Metal Ring.A floating guard ring is commonly used for silicon devices to enhancetheir breakdown voltage1. This concept of using a ring around the mainjunction with a floating potential can be extended to Schottky diodes. Inthis case, it is convenient to use the Schottky barrier metal tosimultaneously form floating metal rings around the main diode. Thisstructure is illustrated in Fig. 3.16. The optimum spacing for the floatingmetal ring is governed by the same considerations as for the floating fieldring (see later section in this chapter). In the case of 6H-SiC Schottkydiodes, it was found that the breakdown voltage increased with ringspacing up to a distance of 5 microns. The resulting breakdown voltagewas twice that for the un-terminated Schottky barrier diode4.3.2.4 Schottky Diode Edge Termination with Argon ImplantSince the breakdown voltage of the planar Schottky diode is limited byelectric field enhancement at the edge of the metal, its breakdownvoltage can be increased by spreading the potential along the surface.One effective method for achieving this is by creating a highly resistivelayer along the surface as illustrated in Fig. 3.17. This was firstdemonstrated at PSRC by using Argon ion implantation around Schottkydiodes in 6H-SiC to produce nearly ideal breakdown voltages5 followedby its successful application to 4H-SiC6. A remarkable increase in the
  • 73. Breakdown Voltage 51breakdown voltage from 300 V to 1000 V was achieved with thistechnique. • SCHOTTKY BARRIER CONTACT „,<,„ RES1S|V|TY R E G i 0 N L , / OXIDE / L / J N-DRIFT REGION N+ SUBSTRATE Y///////////////////M^ CATHODE Fig. 3.17 Schottky Diode Edge Termination with High Resistivity Extension. The principle behind the approach is to utilize ion implantationto create damage in the silicon carbide lattice to produce deep levels inits band gap. This moves the Fermi level close to the center of the bandgap within the implanted zone producing a high resistivity layer due tothe large band gap of the semiconductor7. The presence of the deep leveltraps has been confirmed using Deep Level Transient Spectroscopy(DLTS) measurements. The damage can be created by using anyimplantation species (including dopants, such as Aluminum and Boron,without sufficient annealing to remove all the deep level defects) assubsequently reported by other groups8. The design of the argon implanted edge termination has beenstudied to determine its optimum length9. It was found that a length of100 microns is adequate to achieve a breakdown voltage of 800 V for a6H-SiC diode fabricated using an epitaxial layer doping concentration of2 x 1016cm"3 as shown in Fig. 3.18. An argon implant dose of 1 x 1015cm"2 was used at the periphery of the Schottky diodes. The length of theimplanted zone is about ten times the width of the depletion region atbreakdown. The leakage current was found to increase linearly with thelength of the implanted zone. It is therefore important to use a length justsufficient to achieve the parallel plane breakdown voltage. It has been
  • 74. 52 SILICON CARBIDE POWER DEVICESfound that the leakage current can be reduced by two-orders ofmagnitude with post implantation annealing at 600 °C10. 800 1.6 r- • 1 2 —PC fy° > / 600 1.2 S 60 4 S I l 0- J 400 0.8 1 £ 200 0.4 * * * SO 100 150 200 250 Length of Argon Implanted Zone (microns) Fig. 3.18 Design of the High Resistivity Extension for the Planar Junction Edge Termination.3.2.5 Schottky Diode Edge Termination with RESP RegionThe breakdown voltage of a Schottky diode can also be improved byspreading the potential along the surface using a resistive Schottkybarrier field plate or RESP termination4. The RESP layer is a highresistivity film formed on the silicon carbide surface with a rectifyinginterface. In the case of silicon carbide devices, this has been achieved bydepositing a very thin layer of Titanium (50 to 80 angstroms), which issubsequently oxidized to increase its resistivity in a controlled manner. Ithas been demonstrated that the oxidation can be performed at 300 °C inair without damaging the quality of the main Schottky barrier contact.Prior to oxidation of the titanium layer, the breakdown voltage of thestructure was only 150 volts, as in the case of un-terminated diodes. Thebreakdown voltage was found to increase to 500 volts when the sheetresistance of the RESP layer reached 1 MQ/square. Modeling of theRESP termination using a distributed resistor/diode network4 indicatesthat larger breakdown voltages would be achieved when the sheetresistance reaches 1 G£2/square. Beyond this, the breakdown voltagedecreases because the RESP layer begins to behave like a dielectric.
  • 75. Breakdown Voltage 533.3 P-N Junction Edge TerminationsThe P-N junction is commonly used for the formation of a variety ofpower device structures. Although the emphasis in this book is onunipolar devices due to their high performance characteristics whenfabricated from 4H-SiC, these devices often utilize P-N junctions tocontrol the electric field distribution within the active region. The P-Njunction can then also be used at the edges of the devices to reduceelectric field crowding. Device edge terminations that utilize P-Njunctions are discussed in this section.3.3.1 Planar Junction Edge Termination ANODE p+ N-DRIFT REGION N+ SUBSTRATE CATHODE Fig. 3.19 Ion-Implanted Planar Junction Edge Termination in 4H-SiC.One of the simplest edge terminations used for silicon power devices isthe cylindrical junction. The breakdown voltage of this type oftermination is well below that for the parallel-plane junction due toelectric field enhancement at the corner of the cylindrical junction1. Thisbehavior has been analytically modeled". In silicon carbide, the dopantsdo not move during the ion implant annealing cycles despite therelatively high temperature because of the extremely low diffusioncoefficients (see chapter 2). The ion-implanted junctions must thereforebe modeled with very small characteristic diffusion lengths that arerepresentative of the ion implant straggle. This type of planar edgetermination is illustrated in Fig. 3.19 with an oxide passivation3. This
  • 76. 54 SILICON CARBIDE POWER DEVICESstructure was analyzed by performing two-dimensional numericalsimulations using a drift region doping concentration of 1 x 1016cm~3 andthickness of 30 microns. The depth of the P + region was varied toexamine its impact on the breakdown voltage. Three-dimensional viewsof the doping profile for a shallow and deep junction used during thesimulations are provided below in Fig. 3.20 and 3.21. Junction Depth = 0.2 microns Fig. 3.20 Doping Profile for the Shallow Planar Cylindrical Junction. Junction Depth = 0.9 microns Fig. 3.21 Doping Profile for the Deep Planar Cylindrical Junction.
  • 77. Breakdown Voltage 55 Junction Depth = 0.2 microns S O WFig. 3.22 Electric Field distribution at the Shallow Planar Junction in 4H-SiC for a Reverse Bias of 500 volts. Junction Depth = 0.9 microns P-N Junction / 1 £. ^ s J| w 4.0 8. 2.0 fa 8 ^^^^^^^^^^^^^^^^^^^ W *^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^s?^p * ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^^liifiiilP^ ^^FFig. 3.23 Electric Field distribution at the Deep Planar Junction in 4H-SiC for a Reverse Bias of 950 volts.
  • 78. 56 SILICON CARBIDE POWER DEVICES The breakdown voltage of the structure was found to increasewith increasing junction depth. For a shallow junction depth of 0.2microns, the breakdown occurred at 400 volts. This is due to a significantenhancement in the electric field at the corner of the junction as shown inFig. 3.22. This field enhancement was found to be reduced as shown inFig. 3.23 when the junction depth was increased to 0.9 microns leadingto an increase in the breakdown voltage to 900 volts. These values arewell below the breakdown voltage (3000 volts) for the ideal parallelplane junction. They are consistent with the measured breakdownvoltages for nitrogen implanted N+/P diodes formed in 4H-SiC withoxide surface passivation3 and boron implanted 6H-SiC diodes12. 1000 # Simulations i ^*> 3 800 > g 600 400 Analytical i) / I 03 200 0.2 0.4 0.6 0.8 1.0 Junction Depth (microns) Fig. 3.24 Breakdown Voltage of Cylindrical Planar Junctions in 4H-SiC. The breakdown voltage of cylindrical junctions can be predictedby using the following analytical relationship : .8/7 .6/7BV,CYL V ( 6/7 ( W, PP +2 In 1 + 2BV,PP WPP j yWPp j V rJ J WPp j [3.14]where rj is the radius of curvature of the junction. The breakdownvoltage calculated using this equation is shown in Fig. 3.24 by the solidline for the case of 4H-SiC with a doping concentration of 1 x 1016 cm3.The breakdown voltage obtained by the two dimensional numerical
  • 79. Breakdown Voltage 57simulations are in reasonable agreement with the analytical formula asshown by the symbols.3.3.2 Planar Junction Edge Termination with Field Plate ANODE FIELD PLATE m OXIDE P+ N-DRIFT REGION N+ SUBSTRATE y/////////////////////////////m CATHODE Fig. 3.25 Planar Junction Edge Termination with Field Plate.In the previous section, it was demonstrated that the breakdown voltageof a planar junction is limited by the enhanced electric field at the cornerof the P-N junction (location A in Fig. 3.25 above). This electric fieldenhancement can be ameliorated by forming a field plate by extendingthe anode metal over the edge of the junction on top of the oxide. Forsilicon devices, the improvement in the breakdown voltage depends uponthe length (L) of the field plate and the thickness of the oxide underneaththe field plate1. Although this also true in principle for the case of siliconcarbide structures, an additional consideration is the much higher electricfield within the oxide. Two-dimensional numerical simulations of the planar junctionwith field plate were performed using an N-type drift region with dopingconcentration of 1 x 1016 cm"3. The junction depth was chosen as 0.9microns. The increase in the breakdown voltage is shown in Fig. 3.26with increasing length of the field plate. In these simulations, the oxidethickness was kept at 1 micron. The breakdown voltage can be increasedtwo-fold with sufficient field plate length. A field plate length of 15microns is adequate for this particular N-region doping concentration.
  • 80. 58 SILICON CARBIDE POWER DEVICES 2000 4 6 8 10 12 14 16 Field Plate Length (microns) Fig. 3.26 Cylindrical Planar Junctions in 4H-SiC with Field Plate. No Field Plate 5 10 IS 20 Distance (microns) 10 micron Field Plate 0 ••• 4 1 8 1 12 I V K = 1500 V 16 H N-Drift Reg ion 0 5 10 IS 20 25 30 Distance (microns) Fig. 3.27 Potential Contours for Cylindrical Planar Junctions with Field Plate.
  • 81. Breakdown Voltage 59 The reason for the increase in the breakdown voltage with theaddition of the field plate can be understood by examining the potentialcontours shown in Fig. 3.27. In the case of the planar junction shown atthe top, potential crowding is observed at the junction (location A in Fig.3.25). The addition of the field plate reduces the potential crowding atthe junction by spreading the depletion region along the surface as shownin the lower portion of Fig. 3.27. However, potential crowding isobserved at the edge of the field plate (location B in Fig. 3.25). 10 micron Field Plate Fig. 3.28 Electric Field distribution at the Field Plate in 4H-SiC for a Reverse Bias of 1500 volts. The impact of the potential crowding at the edge of the fieldplate can be seen in the three-dimensional electric field distribution plotin Fig. 3.28. Although there is an electric field peak located at its edge(point B) inside the semiconductor, this peak is smaller than that at thejunction. This implies that the breakdown will be initiated at the junction.The electric field at the edge of the field plate can become greater thanthat at the junction if the oxide thickness is reduced. As an example, theelectric field for the case of 4000 angstrom oxide is shown in Fig. 3.29. Itcan be seen that the electric field at the edge of the field plate exceedsthat at the junction for this smaller oxide thickness.
  • 82. 60 SILICON CARBIDE POWER DEVICES 4000 Angstrom Field Oxide P-N Junction l Field Plate Edge S^ ,s Jsik 8„ f /i^^^^^WM M ^^i 3.0 t r 8. 2.0 1.0 fa 8 •2 ^ 0 u Fig. 3.29 Electric Field distribution at the Field Plate in 4H-SiC for a Reverse Bias of 1000 volts. 2000 0.2 0.4 0.6 0.8 1.0 1.2 Field Oxide Thickness (microns) Fig. 3.30 Cylindrical Planar Junctions in 4H-SiC with Field Plate.
  • 83. Breakdown Voltage 61 The impact of changing the field oxide thickness on thebreakdown voltage is shown in Fig. 3.30. It can be seen that thebreakdown voltage reaches a maximum value at a field oxide thicknessof 0.8 microns. However, the change in breakdown voltage is small forlarger oxide thickness values. These results indicate that a simple edgetermination for 4H-SiC devices can be constructed using a P-N junctionwith a field plate extending over an oxide at the edges. The mainadvantage of this approach is that no additional masking or processingsteps are required during device fabrication to prepare the edgetermination. However, the breakdown voltage achieved with this methodis well below that for the ideal parallel plane junction.3.3.3 Planar Junction Edge Termination with Floating Rings ANODE FLOATING FIELD RING OXIDE N-DRIFT REGION N+ SUBSTRATE V////////////////////////////Z7A CATHODE Fig. 3.31 Planar Junction Edge Termination with Floating Field Ring.The planar junction edge termination with a single floating field ring isshown in Fig. 3.31. This method for edge termination is commonly usedin silicon devices, particularly at lower breakdown voltages, to improvethe operating voltages. One of the advantages of this approach is that thefloating field ring can be fabricated simultaneously with the mainjunction without adding process steps. The breakdown voltage of thetermination depends upon the spacing (Ws) of the floating field ring fromthe main junction1. If the spacing is too large, the electric field at theedge of the main junction remains high leading to a breakdown voltage
  • 84. 62 SILICON CARBIDE POWER DEVICESsimilar to the planar junction without the field ring. If the spacing is toosmall, a high electric field develops at the outer edge of the floating fieldring leading to a breakdown voltage equal to that for a planar junctionwithout the field ring. An optimum spacing is required to achieve anincrease in the breakdown voltage. The breakdown voltage of a planarjunction with a single floating field ring can be calculated using ananalytical method13: ( „ f .. 611 "* FFR "* CYL 0.5 •0.96 BV PP yWpp j WppJ 1 r, i rr PP + 1.92 .In 1.386 r V "PP J V J J [3.15]with the optimum floating field ring spacing given by: W< BV,FFR BV, FFR BV,CY [3.16] W, PP BV,PP BV,pp BV,ppFor the case of a drift region doping concentration of 1 x 10 16 cm"3 and ajunction depth of 0.9 microns, these equations predict an increase in thebreakdown voltage from about 800 V to 1200 V for an optimum fieldring spacing of 4.5 microns. Such a modest increase in the breakdown voltage has been experimentally observed for junctions fabricated in 4H-SiC with field ring spacing of 4 microns314. An optimum field ringspacing of 5 microns has also been reported for diodes with a breakdownvoltage of 1600 volts15, consistent with the predictions of the analyticalmodel.3.3.4 Planar Junction Edge Termination with P-ExtensionFor silicon devices, the breakdown voltage has been shown to be greatlyimproved by using a Junction Termination Extension . This structure,illustrated in Fig. 3.32, contains a P-type region formed at the peripheryof a P+/N junction. This lightly doped P-type region is usually formed byusing ion implantation to precisely control the dopant charge within thelayer. If the doping concentration in the P-type region is too high, thebreakdown occurs at its edge (point B) at a lower breakdown voltage
  • 85. Breakdown Voltage 63than the main junction due to its smaller radius of curvature. If thedoping concentration is too low in the P-type region, it becomescompletely depleted at low reverse bias voltages resulting in breakdownat the main junction (point A) at the same voltage as the un-terminatedjunction. ANODE P- REGION i L / / J OXIDE B A N-DRIFT REGION N+ SUBSTRATE //////////////////////////////A CATHODE Fig. 3.32 Planar Junction Edge Termination with P-Extension. The optimum charge in the P-type region is: Q = esEc [3.17]which amounts to 2.58 x 10"6 C/cm2 for a critical electric field of 3 x 106V/cm for 4H-SiC. This is equivalent to a dopant dose of 1.6 x 10° cm"2,which is about 10 times larger than that used in silicon devices1. A moreprecise optimization of the dose can be performed by two-dimensionalnumerical simulations of the structure. The results of the simulations, performed using an extensionlength of 10 microns, are summarized in Fig. 3.33 where the variation inbreakdown voltage is plotted as a function of the dopant dose in the P-region. As in the case of silicon devices, there is an optimum dose atwhich the breakdown voltage has a maximum value. At lower doses, thebreakdown voltage continues to occur at the main junction due to thepeak in the electric field at point A as shown in the electric fielddistribution plotted in Fig. 3.34. At higher doses, the breakdown voltageoccurs at the edge of the extension due to the peak in the electric field atpoint B as shown in the electric field distribution plotted in Fig. 3.35.
  • 86. 64 SILICON CARBIDE POWER DEVICES 2500 ^ 2000 "3 > 1500 M 3 "3 > | 1000 •8 1 as 500 I 0.5 1.0 1.5 2.0 2.5 3.0 Dopant Dose in Extension Region (1013 cm"2) Fig. 3.33 Planar Junctions in 4H-SiC with P- Extension. Dose = 0.5 x 1013 cm 3 P+N Junction Fig. 3.34 4H-SiC Planar Junction with Extension (Bias = 1000 V).
  • 87. Breakdown Voltage 65 Dose = 2.5 x 10 13 c m 3 P+N Junction Extension Edge »5 I IFig. 3.35 4H-SiC Planar Junction with Extension (Bias = 1000 V). Dose = 1.5 x 10 13 cm"3 P+N Junction S > 3.0 S WFig. 3.36 4H-SiC Planar Junction with Extension (Bias = 2000 V).
  • 88. 66 SILICON CARBIDE POWER DEVICES The electric field distribution at the optimum dose is shown inFig. 3.36. It can be seen that the electric field at the P^U junction and atthe edge of the extension are equal leading to the maxima in thebreakdown voltage. In all the cases, the electric field first develops at theedge of the extension and then spreads through the extension region. Thiscan be observed in the electric field profile taken along the surface,shown in Fig. 3.37, for the case of the optimum dose. At a bias of 500volts, the electric field is confined to point B in Fig. 3.32. As the voltageincreases, the electric field extends towards the main P*N junctionbecause the extension region gets depleted. Dose = 1.5 x 10 u cm"2 I * 2 c I o 10 15 20 25 30 Distance along the surface (microns) Fig. 3.37 4H-SiC Planar Junction with Extension. For a comparison between the different dopant dose cases, theelectric field along the surface is shown in Fig. 3.38 at a reverse bias of1000 volts. It can be seen that a high electric field develops at the edge ofthe extension region if the dose is too high and at the main junction if thedose is too low. At high doses (> 2 x 1013 cm"2), the extension regiondoes not get depleted in the region between point A and B in Fig. 3.32because the charge is too large. Consequently, the electric field continuesto escalate with bias at the edge of the extension region leading tobreakdown at lower voltages. If the dose is too low, the extension regionbecomes depleted at low bias values and a high electric field develops atthe main junction.
  • 89. Breakdown Voltage 67 Bias Voltage = 1000 V Fig. 3.38 4H-SiC Planar Junction with Extension. The optimum dose obtained by using the numerical simulationsis in excellent agreement with that predicted by using the simple formulain Eq. [3.17]. The breakdown voltage obtained at the optimum dose istwice that for the un-terminated junction for this extension length. Thedependence of the breakdown voltage on the extension length is shownin Fig. 3.39 at the optimum dose in the extension. A breakdown voltageclose to the parallel plane junction can be obtained by using an extensionlength of 50 microns. This method for edge terminations has gained popularity due toits effectiveness in suppressing the edge breakdown for P-Njunctions1718,19. In order to implement this technique it was necessary todevelop methods for precisely controlling the P-type dopant dose in theextension. Although the dose can be controlled very well by using ionimplantation, processes for the annealing and activation of P-typedopants (Boron and Aluminum) needed to be developed. In addition, theperformance has been found to be sensitive to surface charge in thepassivation as also reported for silicon devices. Enhancements to thebreakdown voltage can also be achieved using multiple zones withdifferent dopant dose levels20 achieved by etching steps in a epitaxiallygrown P-type layer.
  • 90. 68 SILICON CARBIDE POWER DEVICES JUUO 2500 "3 C 2000 8 "3 1500 > a 3 1000 1 M 500 10 20 30 40 50 60 Length of Extension Region (microns) Fig. 3.39 Planar Junctions in 4H-SiC with P- Extension.3.4 SummaryThe design issues pertinent to obtaining a high breakdown voltage insilicon carbide structures have been reviewed in this chapter. As a benchmark, the breakdown voltage of the abrupt parallel plane junction hasbeen analyzed for 4H-SiC and analytical equations developed for thedepletion layer width and critical electric field. The breakdown voltageof practical devices is limited by the electric field crowding at theiredges. Various edge termination methods have been reviewed todetermine their performance relative to the ideal parallel plane junction.The argon implanted high resistance zone and the junction extensionusing a P- region with a dose of 1.5 x 1013 cm"2 have been found toprovide the best performance.
  • 91. Breakdown Voltage 69References B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.2 M. Bhatnagar and BJ. Baliga, "Silicon Carbide High Voltage (400V)Schottky Barrier Diodes", IEEE Electron Device Letters, Vol. ED13, pp.501-503, 1992.3 R.K. Chilukuri, P. Ananthanarayanan, V. Nagapudi, and BJ. Baliga,"High Voltage P-N Junction Diodes in Silicon Carbide using Field PlateEdge Termination", MRS Symposium Proceedings, Vol. 572, pp. 81-86,1999.4 M. Bhatnagar, et al, "Edge Terminations for SiC High VoltageSchottky Rectifiers", International Symposium on Power SemiconductorDevices and ICs, pp. 89-94, 1993.5 D. Alok, BJ. Baliga, and P.K. McLarty, "A Simple Edge Terminationfor Silicon Carbide with Nearly Ideal Breakdown Voltage", IEEEElectron Device Letters, Vol. ED15, pp. 394-395, 1994.6 D. Alok, R. Raghunathan, and B J. Baliga, "Planar Edge Terminationfor 4H-SiC Devices", IEEE Transactions on Electron Devices, Vol. 43,pp.1315-1317, 1996.7 D. Alok, B J. Baliga, M. Kothandaraman, and P.K. McLarty, "ArgonImplanted SiC Device Edge Termination: Modeling, Analysis, andExperimental Results", Institute of Physics Conference Series, Vol. 142,pp. 565-568, 1996.8 A. Itoh, T. Kimoto, and H. Matsunami, "Excellent Reverse BlockingCharacteristics of High Voltage 4H-SiC Schottky Rectifiers with BoronImplanted Edge Termination", IEEE Electron Device Letters, Vol.ED17, pp. 139-141, 1996.9 D. Alok and BJ. Baliga, "SiC Device Edge Termination using FiniteArea Argon Implantation", IEEE Transactions on Electron Devices, Vol.44, pp. 1013-1017, 1997.10 A.P. Knights, et al, "The Effect of Annealing on Argon ImplantedEdge Terminations for 4H-SiC Schottky Diodes", MRS SymposiumProceedings, Vol. 572, pp. 129-134, 1999.11 B J. Baliga and S. Ghandhi, "Analytical Solutions for the BreakdownVoltage of Abrupt Cylindrical and Spherical Junctions", Solid StateElectronics, Vol. 19, pp.739-744, 1976.12 P.M. Shenoy and BJ. Baliga, "Planar, High Voltage, BoronImplanted 6H-SiC P-N Junction Diodes", Institute of Physics ConferenceSeries, Vol. 142, pp. 717-720, 1996.
  • 92. 70 SILICON CARBIDE POWER DEVICES13 B. J. Baliga, "Closed Form Analytical Solutions for the BreakdownVoltage of Planar Junctions Terminated with a Single Floating FieldRing", Solid State Electronics, Vol. 33, pp. 485-488, 1990.14 R. Singh and J. W. Palmour, "Planar Terminations in 4H-SiCSchottky Diodes with Low Leakage and High Yields", InternationalSymposium on Power Semiconductor Devices and ICs, pp. 157-160,1997.15 W. Bahng, et al, "Fabrication and Characterization of 4H-SiC pnDiode with Field Limiting Ring", Silicon Carbide and Related Materials- 2003, Materials Science Forum, Vol. 457-460, pp. 1013-1016, 2004.16 V.A.K. Temple, "Junction Termination Extension: a New Techniquefor increasing Avalanche Breakdown Voltage and controlling SurfaceElectric Fields in P-N Junctions", IEEE International Electron DevicesMeeting, Abstract 20.4, pp. 423-426, 1977.17 R. Rupp, et al, "Performance and Reliability Issues of SiC SchottkyDiodes", Silicon Carbide and Related Materials - 1999, MaterialsScience Forum, Vol. 338-342, pp. 1167-1170, 2000.18 R. Singh, et al, "SiC Power Schottky and PiN Diodes", IEEETransactions on Electron Devices, Vol. ED49, pp. 665-672, 2002.19 H.P. Felsl and G. Wachutka, "Performance of 4H-SiC SchottkyDiodes with Al-Doped p-Guard-Ring Junction Termination at ReverseBias", Silicon Carbide and Related Materials - 2001, Materials ScienceForum, Vol. 389-393, pp. 1153-1156, 2002.20 X. Li, et al, Theoretical and Experimental Study of 4H-SiC JunctionEdge Termination", Silicon Carbide and Related Materials - 1999,Materials Science Forum, Vol. 338-342, pp. 1375-1378, 2000.
  • 93. Chapter 4 PiN RectifiersAs discussed in previous chapters, from a power device perspective, themain advantage of wide band gap semiconductors is the very lowresistance of the drift region even when it is designed to support largervoltages. This favors the development of high voltage unipolar deviceswhich have much superior switching speed than bipolar structures.However, the development of high voltage PiN rectifiers has been givensignificant attention among the SiC research community1,2. For thisreason, the basic operating principles of the PiN rectifier are reviewed inthis chapter. The results of two-dimensional numerical simulations areused to elucidate the physics of operation within these structures. Sincethe minority carrier lifetime plays an important role in determining thecharacteristics of these devices, this parameter has been varied toexamine its influence on performance. The silicon PiN rectifiers that are designed to support largevoltages rely upon the high level injection of minority carriers into thedrift (i) region . This phenomenon greatly reduces the resistance of thethick, very lightly doped drift regions necessary to support high voltagesin silicon. In the case of silicon carbide, the drift region doping level isrelatively large and its thickness is much smaller than for silicon devicesto achieve very high breakdown voltages. The benefits of high levelinjection are not obvious unless the breakdown voltage approaches 10,000 volts as shown in this section.4.1 One-Dimensional PiN StructureThe basic one-dimensional PiN rectifier structure is illustrated in Fig. 4.1together with the electric field profile when reverse biased and the carrierdistribution profile when it is forward biased. A punch-through i-regiondesign is favored for PiN rectifiers due to the conductivity modulation of 71
  • 94. 72 SILICON CARBIDE POWER DEVICESthe drift region in the on-state. The breakdown voltage for such regionsis provided in reference 3. When this junction is forward-biased by the application of anegative bias to the N-region, holes and electrons are injected into thedrift-region as illustrated in Fig. 4.1. The carrier distribution n(x) can beobtained by solving the continuity equation for the N-region: dn n d2n — =0= - + D, dx2 [4.1] • HL dt r.where Da is the ambipolar diffusion coefficient and XHL is the high levellifetime in the drift region. N- Drift (i) Region N+ 2d •*• x E(x) n(x) P(x) n=p Nr ^P V ->• X Fig. 4.1 Electric Field and Carrier Distribution for a PiN Rectifier.The solution for this equation using appropriate boundary conditions3yields: r J cosh(x / La) sinh(jc / La n(x) = p(x) = t HLJ F [4.2] 2qLa sinh(d/La) 2cosh(d/La
  • 95. PiN Rectifiers 73The catenary carrier distribution described by this equation is illustratedin the figure. In this expression, the ambipolar diffusion length is givenby: A,=V^ HL [4.3]The forward current density JF can be related to the on-state voltage dropVF after taking into account voltage drops in the middle (i) region and thetwo junctions (P+/i and i/N+): f 2qDant d^ qVF J. exp [4.4] KKJ 2kT,where F(d/La) is a function that reaches a maximum value when La = d. For purposes of comparison, numerical simulations wereperformed on both silicon and 4H-SiC PiN rectifier structures withvarious breakdown voltages. In each case, the impact of changing thehigh level lifetime was included in the analysis. The design of the driftregion for these rectifiers can be compared in Table 4.1. As discussedearlier, for each breakdown voltage, the doping concentration in the driftregion for 4H-SiC is 200 times larger than that for the silicon case. Breakdown Silicon 4H-SiC Voltage Doping Thickness Doping Thickness (cm"3) (microns) (cm 3 ) (microns) 500 V 5 x 1014 36 1 x 1017 2.2 1,000 V 2xl014 81 4 x 1016 5.3 2,000 V 8 x 1013 183 1.6 x 1016 12 3,000 V 5 x 1013 294 1 x 1016 20 5,000 V 2 x 1013 530 4.4 x 1015 35 10,000 V 9 x 1012 1200 1.7 x 1015 80 Table 4.1 Comparison of Drift Region Parameters for Si and 4H-SiC.
  • 96. 74 SILICON CARBIDE POWER DEVICES Silicon PiN Rectifiers: T = 1 jlsec -3 | Fig. 4.2 Forward Conduction Characteristics of Silicon PiN Rectifiers. The forward conduction characteristics for the silicon PiNrectifiers obtained with numerical simulations are shown in Fig. 4.2 forthe case of a lifetime of 1 jj,s (namely, T^ = T„o = 1 l^s). Since the area ofthe simulation structure is 1 x 10"8 cm"2, an on-state current density of100 A/cm2 corresponds to a current of 1 x 10"6 A in the figure (asindicated the dashed line). It can be seen that the on-state voltage dropbecomes large when the voltage rating becomes greater than 3000 voltsfor this lifetime value. The on-state voltage drop for the device withbreakdown voltage of 10,000 volts can be reduced by increasing thelifetime as shown in Fig. 4.3. This is due to be improved conductivitymodulation, which can be observed in Fig. 4.4, where the injected holeconcentration is compared with the background doping level in the driftregion. At the 1 |is lifetime, very little high level injection occurs due tothe short diffusion length. The large resistance of the very lightly doped,thick drift region produces the high on-state voltage drop. At a lifetimeof 10 us, there is weak modulation of the drift region. A lifetime of 100
  • 97. PiN Rectifiers 75[is is required to get a low on-state voltage drop in the 10 kV silicon PiNrectifier. This results in a poor switching speed. Silicon PiN Rectifier: BV = 10 kV -4 -3 -2 -1 0 Forward Bias (V) Fig. 4.3 Forward Conduction Characteristics of lOkV Si PiN Rectifiers. Silicon PiN Rectifier: BV = 10 kV 0.2 0.4 0.6 0.8 1.0 1.2 Distance (mm) Fig. 4.4 Conductivity Modulation within 10 kV Si PiN Rectifiers.
  • 98. 76 SILICON CARBIDE POWER DEVICES As shown in Table 4.1, the thickness of the drift region in the4H-SiC PiN rectifiers is much smaller than for the silicon devices for thesame breakdown voltage. This allows good conductivity modulation ofthe drift region even for the device with breakdown voltage of 10,000volts as shown in Fig. 4.5 for a lifetime of 100 ns. This plot was done at aforward voltage drop of 4 volts because of the larger junction potentialfor4H-SiC 4H-SiC PiN Rectifier: BV = 10 kV Vf=4V 0 20 40 60 80 100 Distance (microns) Fig. 4.5 Conductivity Modulation within 10 kV 4H-SiC PiN Rectifier. The forward conduction characteristics for the 10 kV 4H-SiCPiN rectifier obtained from the numerical simulations are shown in Fig.4.6 for various lifetime values. It can be seen that the on-state voltagedrop is determined by the un-modulated resistance of the drift regionwhen the lifetime is at 5 or 10 nsec. When the lifetime is increased to 100nsec, the conductivity modulation of the drift region reduces the on-statevoltage drop. The results of numerical simulations of the forwardcharacteristics of 4H-SiC PiN rectifiers with various breakdown voltagecapabilities are shown in Fig. 4.7 for the case of a lifetime of 5 nsec. Theinfluence of conductivity modulation of the drift region can be observedeven for the case of a breakdown voltage of 5000 V. However, the on-state voltage drop for all the devices is relatively high (3 V) whencompared to silicon devices.
  • 99. PiN Rectifiers 77 4H-SiC PiN Rectifier: BV = 10 kV -3 - ^ ^ ^ -4 • ^ 1 (isec 100 nsec S - 5 S ^ ,; -O u "~~~~~--^CS. JFW 100 A/cm2 3 5,10 n s e c ^ U -v- [Forward do I o © -10 < 1 -11 -12" -4 -3 -2 -1 Forward Bias (V)Fig. 4.6 Forward Conduction Characteristics of lOkV 4H-SiC PiN Rectifier. 4H-SiC PiN Rectifiers: x = 5 nsec -4 -3 -2 -1 Forward Bias (V) Fig. 4.7 Forward Conduction Characteristics of 4H-SiC PiN Rectifiers.
  • 100. 78 SILICON CARBIDE POWER DEVICES The 4H-SiC PiN rectifier operates on the same principles as thesilicon device. To illustrate this, the on-state carrier distribution within a3 kV device is shown in Fig. 4.8 at a forward voltage drop of 4 volts. Theplot includes both the electron and hole concentrations within the driftregion as well as the background doping concentration. High levelinjection of the mobile carriers is evident leading to strong conductivitymodulation even with a lifetime of 10 nsec used in the simulation. Thehole and electron carrier profile observes the catenary shape described byEq. [4.2]. This carrier distribution has been experimentally validated .The behavior of silicon carbide rectifiers can be modeled using the samehigh level injection physics previous used for silicon devices. However,one advantage of 4H-SiC structures is that the small drift region widthrequired to support high voltages allows reduction of the lifetime to thenanosecond level. This is favorable for achieving fast switching speedswhen compared with silicon devices. 4H-SiC PiN Rectifier: BV = 3kV 19 v,=-XM f £ * 18 Concentration] A i .i -> n s V 17: 1 P i i i j 8P 16 i Doping 15 0 5 10 15 20 25 Distance (microns) Fig. 4.8 Conductivity Modulation within 3 kV 4H-SiC PiN Rectifier. The impact of operating temperature on the on-state voltage dropof the 4H-SiC PiN rectifier is shown in Fig. 4.9 for case of a breakdownvoltage of 3000 volts. It can be seen that a positive temperaturecoefficient for on-state voltage drop occurs when the forward current
  • 101. PiN Rectifiers 79density exceeds 100 A/cm2. This is favorable for the paralleling ofdevices and preventing hot spots or current filaments. 4.0 j c i 300 A/cm 2 l l _ | -it~ " J F = 100 A/cm 2 §• 3.0 1L II 1 II 1 • 1 • F=; * +• 2 2 J • 50 A/cnII J F = 10 A/cm 2.0 Breakdown Voltage = 3000 V 1.0 300 350 400 450 500 Temperature (°K) Fig. 4.9 On-state Voltage Drop for a 3 kV 4H-SiC PiN Rectifier.4.2 Experimental ResultsMany groups have worked on the development of high voltage PiNrectifiers2. In early studies, the quality of the P + region was poor due toproblems with achieving a high doping concentration. The best resultswere obtained by epitaxial growth of the anode followed by etching stepsto create the edge termination5. More recently, the anode has beenformed by ion implantation of Al or B or both dopants. The forwardcharacteristic of implanted junction diodes was found to be sensitive tothe junction depth and activation process6. The on-state voltage drop of a4H-SiC diode fabricated using 100 micron thick drift region with dopingconcentration of 1-3 x 1014 cm"3 has been reported2 at 7.1 volts for acurrent density of 100 A/cm2. These diodes had a breakdown voltage of8.6 kV. This is significantly worse than that obtained by the numericalsimulations despite the reported lifetime in the diodes being about 2microseconds. Some of this can be attributed to the high contactresistance to the anode. The on-state voltage drop of diodes formed by co-implantationof aluminum, carbon, and boron to create the anode region7 has been
  • 102. 80 SILICON CARBIDE POWER DEVICESreported to be about 4.7 volts at room temperature. These diodes,fabricated using a 40 micron thick drift region with doping concentrationof 1 x 1015 cm"3, had a breakdown voltage of about 4.5 kV. The on-statevoltage drop was found to reduce with increasing temperature at acurrent density of 100 A/cm2. This was attributed to a reduction in thecontact resistance to the anode region. The lifetime extracted from thereverse recovery measurements was about 21 nanoseconds. These resultsconfirm the conclusion that fast switching PiN rectifiers can bedeveloped from 4H-SiC.4.3 SummaryThe physics of operation of the silicon carbide PiN rectifier has beenshown to be similar to that used to describe silicon devices. High levelinjection in the drift region enables modulating its conductivity to reducethe on-state voltage drop. Due to the much smaller width of the driftregion required to obtain a given breakdown voltage when comparedwith silicon devices, a much smaller lifetime can be used in siliconcarbide devices. This is favorable for reducing switching losses.However, the large band gap of silicon carbide results in a large on-statevoltage drop in excess of 4 volts. A lower on-state voltage drop can beobtained in a silicon carbide device by using the Schottky barrier contactto achieve rectification as discussed in the next chapter. These Schottkybarrier rectifiers are superior to PiN rectifiers for breakdown voltages ofat least 5000 volts.
  • 103. PiN Rectifiers 81References1 T.P. Chow, N. Ramangul, and M. Ghezzo, "Wide BandgapSemiconductor Power Devices", MRS Symposium Proceedings, Vol.483, pp. 89-102, 1998.2 R. Singh, "Silicon Carbide Bipolar Power Devices - Potentials andLimits", MRS Symposium Proceedings, Vol. 640, pp. H4.2.1-H4.2.12,2001.3 B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.4 O. Tornblad, et al, "Investigation of Excess Carrier distributions in4H-SiC Power Diodes under Static Conditions and Turn-on", SiliconCarbide and Related Materials - 1997, Material Science Forum, Vol.264-268, pp. 1053-1056, 1998.5 Y. Sugawara, K. Asano, R. Singh, and J.W. Palmour", "6.2 kV 4H-SiC pin Diode with Low Forward Voltage Drop", Silicon Carbide andRelated Materials - 1999, Material Science Forum, Vol. 338-342, pp.1371-1374,2000.6 R.K. Chilukuri, P. Ananthanarayanan, V. Nagapudi, and B.J. Baliga,"High Voltage P-N Junction Diodes in Silicon Carbide using Field PlateEdge Termination", MRS Symposium Proceedings, Vol. 572, pp. 81-86,1999.7 J.B. Fedison, et al, "AtfC/B Co-implanted High Voltage 4H-SiC PiNJunction Rectifiers", Silicon Carbide and Related Materials - 1999,Material Science Forum, Vol. 338-342, pp. 1367-1370, 2000.
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  • 105. Chapter 5 Schottky RectifiersThe main advantage of wide band gap semiconductors for power deviceapplications is the very low resistance of the drift region even when it isdesigned to support large voltages. This favors the development of highvoltage unipolar devices which have much superior switching speed thanbipolar structures. The Schottky rectifier, formed by making a rectifyingcontact been a metal and the semiconductor drift region, is an attractiveunipolar device for power applications. In the case of silicon, themaximum breakdown voltage of Schottky rectifiers has been limited bythe increase in the resistance of the drift region1. Commercially availabledevices are generally rated at breakdown voltages of less than 100 volts.Novel silicon structures that utilize the charge-coupling concept haveallowed extending the breakdown voltage to the 200 volt range . Manyapplications described in chapter 1 require fast switching rectifiers withlow on-state voltage drop that can also support over 500 volts. The muchlower resistance of the drift region for silicon carbide enablesdevelopment of such Schottky rectifiers with very high breakdownvoltages. These devices not only offer fast switching speed but alsoeliminate the large reverse recovery current observed in high voltagesilicon rectifiers. This reduces switching losses not only in the rectifierbut also in the IGBTs used within the power circuits4. This chapter reviews the basic principles of operation of themetal semiconductor contact. Unique issues that relate to the wide bandgap of silicon carbide and the presence of defect levels within the bandgap must be given special consideration. The much larger electric field insilicon carbide is shown to lead to significant barrier lowering withincreasing reverse voltage when compared with silicon devices.Structures designed to reduce the electric field at the Schottky contact aretherefore of importance to the development of rectifiers. The results ofthe analysis of these structures by using two-dimensional numerical simulations are described in the next chapter. The influence of defects on 83
  • 106. 84 SILICON CARBIDE POWER DEVICESthe characteristics of 4H-SiC Schottky rectifiers is discussed in thischapter. Experimental results on relevant structures are provided todefine the state of the development effort on Schottky rectifiers.5.1 Schottky Rectifier Structure: Forward Conduction ANODE (SCHOTTKY METAL) ELECTRIC FIELD V////////////A DRIFT REGION Wn SUBSTRATE V////////////A CATHODE Fig. 5.1 Structure and Electric Field in a Schottky Rectifier.The basic one-dimensional structure of the metal-semiconductor orSchottky rectifier structure is shown in Fig. 5.1 together with electricfield profile under reverse bias operation. The applied voltage issupported by the drift region with a triangular electric field distribution ifthe drift region doping is uniform. The maximum electric field occurs atthe metal contact. The device undergoes breakdown when this fieldbecomes equal to the critical electric field. As discussed in chapter 1, thespecific on-resistance of the drift region is given by: 4BV2 R on-ideal [5.1] £ sMn^CThe specific on-resistance of the drift region for 4H-SiC is approximately2000 times smaller than for silicon devices for the same breakdownvoltage as shown earlier in Fig. 3.6. Their values are given by:
  • 107. Schottky Rectifiers 85 **» =Ron-ideal(Si) = 5.93x10^ BV™ [5.2]and R*» = Ron-ideal (4H - SiC) = 2.97x10-^ BV " [ 5.3] In addition, it is important to include the resistance associatedwith the thick, highly doped N+ substrate because this is comparable tothat for the drift region in some instances. The specific resistance of theN+ substrate can be determined by taking the product of its resistivity andthickness. For silicon, N+ substrates with resistivity of 1 m£2-cm areavailable. If the thickness of the substrate is 200 microns, the specificresistance contributed by the N+ substrate is 2 x 10"5 £2-cm2. For siliconcarbide, the available resistivity of the N+ substrates is substantiallylarger. For the available substrates with a typical resistivity of 0.02 Q-cmand thickness of 200 microns, the substrate contribution is 4 x 10"4 Q-cm2. The on-state voltage drop for the Schottky rectifier at a forwardcurrent density JF, including the substrate contribution, is given by: { J ^ VF=— In + (Rdnfi+Rsubs)jP [5.4] 9 JS )where J s is the saturation current density. The saturation current densityfor the Schottky barrier is related to the Schottky barrier height (fa): Js = AT exp - [5.5]where A is Richardsons constant. For silicon, the Richardsons constantis 110 A°K"2cm~2 while that for 4H-SiC has been calculated5 to be 146A°K2cm"2. In Eq. [5.4], the first term accounts for the voltage dropacross the metal-semiconductor contact while the second term accountsfor the voltage drop across the series resistance (shown as RD in Fig. 5.1). The calculated forward conduction characteristics for siliconSchottky rectifiers are shown in Fig. 5.2 for various breakdown voltages.For this figure, a Schottky barrier height of 0.7 eV was chosen becausethis is a typical value used in actual devices. It can be seen that the seriesresistance of the drift region does not adversely impact the on-statevoltage drop for the device with breakdown voltage of 50 volts at anominal on-state current density of 100 A/cm2. However, this resistance
  • 108. 86 SILICON CARBIDE POWER DEVICESbecomes significant when the breakdown voltage exceeds 100 volts. Thishas limited the application of silicon Schottky rectifiers to systems, suchas switch-mode power supply circuits, operating at voltages below 50 V. 5.0 / / Silicon eV = 500V BV = 300V If •s 4.o Barrier Height = 0.7 eV r 1 3.0 / BV 200V I 2.0 1.0 BV mm/ . i3V = 50V 1 10 100 1000 Forward Current Density (A/cm2) Fig. 5.2 Forward Characteristics of Silicon Schottky Rectifiers. 5.0 / / I 4H-SiC BV = 10,000V •5 4.0 Barrier Height = 1.1 eV BV = . 1 1 / 5000V 3.0 J 2.0 / BV = 3000V BV = 2000V BV = 1000V BV=500V 1.0 10 100 1000 Forward Current Density (A/cm2) Fig. 5.3 Forward Characteristics of 4H-SiC Schottky Rectifiers.
  • 109. Schottky Rectifiers 87 The significantly smaller resistance of the drift region enablesscaling of the breakdown voltage of silicon carbide Schottky rectifiers tomuch larger voltages typical of medium and high power electronicsystems, such as those used for motor control. The forwardcharacteristics of high voltage 4H-SiC Schottky rectifiers are shown inFig. 5.3 for the case of a Schottky barrier height of 1.1 eV. The N+substrate resistance used for these calculations was 4 x 10"4 Q -cm2. It canbe seen that the drift region resistance does not produce a significantincrease in on-state voltage drop until the breakdown voltage exceeds3000 volts. From these results, it can be concluded that silicon carbideSchottky rectifiers are excellent companion diodes for medium and highpower electronic systems that utilize Insulated Gate Bipolar Transistors(IGBTs). Their fast switching speed and absence of reverse recoverycurrent can reduce power losses and improve the efficiency in motorcontrol applications4. 5.0 / 1000V 4H-SiC / 0.00 / Barrier Height = 1.1 eI /^^ 5. 00a,2Q 3.0 <u 1II 2.0 1.00 0.50 0.10(2 1.0 0.02 10 100 1000 Forward Current Density (A/cm2) Fig. 5.4 Forward Characteristics of 4H-SiC Schottky Rectifiers: Impact of Substrate and Contact Resistance (in m£2-cm2). The impact of the substrate and contact resistance is shown inFig. 5.4 for the case of a 4H-SiC rectifier with a breakdown voltage of1000 volts. The drift region specific on-resistance for this breakdown
  • 110. SILICON CARBIDE POWER DEVICESvoltage is 9.4 x 10"5 Q-cm2. The typical substrate contribution of 4 x 10,-4Q-cm2 is therefore a dominant resistance for this rectifier. However, thecontribution of this resistance to the on-state voltage drop (40 mV) isacceptable when compared with a total on-state voltage drop of 0.9 volts.The ohmic contact resistance to the substrate can substantially add to thetotal series resistance. It is necessary to reduce this resistance to below 1mQ-cm2 to avoid further increase in the on-state voltage drop.5.1.1 Forward Conduction: Simulation ResultsTo confirm the analytically calculated forward characteristics, numericalsimulations of the one-dimensional 4H-SiC Schottky rectifier wereperformed using a metal work function of 4.5 eV (barrier height of 0.8eV). The drift region parameters were varied in accordance with theparameters given in Table 4.1 to change the breakdown voltagecapability of the structures. The forward characteristics obtained from thesimulations are shown in Fig. 5.5. -3 -4 s -6 u 10,000 V u -7 u -8 cs -9 OJD © •10 Work Function = 4.5 eV •11 -12 -2.5 -2.0 -1.5 -1.0 -0.5 Forward Bias (V) Fig. 5.5 Forward Characteristics of 4H-SiC Schottky Rectifiers.
  • 111. Schottky Rectifiers 89 The results shown in Fig. 5.5 are in agreement with theanalytical model when the difference in barrier height is taken intoaccount. The influence of the barrier height on the forwardcharacteristics can be observed from Fig. 5.6 for the case of drift regionwith breakdown voltage of 3000 volts. When the barrier height isincreased to 1.3 eV corresponding to a work function of 5.0 eV, theforward characteristics are close to those for the 3kV structure in Fig.5.3. Due to the relatively small contribution to the forward voltage drop(at the nominal on-state current density of 100 A/cm2) from the seriesresistance of the drift region, the on-state voltage drop is found tostrongly depend upon the barrier height. Breakdown Voltage = 3000 V -4i _ _ ^ ^ J F = 100 A/cm2 -5 (V) : -6; " ^ ^ ^ ^ X N Log [Forward Current] -7; -8: " -9 4 5 eV Work 5 e V -10 0 3, e v < v ° Function -11 -2.5 -2.0 -1.5 Forward Bias (V) V-1.0 -0.5 0 Fig. 5.6 Forward Characteristics of 3 kV 4H-SiC Schottky Rectifiers: Impact of Schottky Barrier Work-Function. The impact of changing the ambient temperature on the forwardconduction characteristics of the 4H-SiC Schottky rectifier is shown inFig. 5.7 for the case of a breakdown voltage of 3000 volts. As in the caseof silicon devices, the voltage drop associated with the barrier reduces
  • 112. 90 SILICON CARBIDE POWER DEVICESwith increasing temperature leading to a smaller voltage drop at lowcurrent levels. However, the drift region resistance increases withtemperature due to the degradation of the bulk mobility leading to anincrease in the on-state voltage drop at high current levels. For thenominal operating current density of 100 A/cm2, the on-state voltagedrop has a positive temperature coefficient indicating stable operation forthe diode. Breakdown Voltage = 3000 V -4 J F = 100 A/cm2 -5- -6 - - - -"-":_":.-;_--?>r^ XV1 s <u u -7- u a U • -8 ^ •E -9 l Work Function = 4.5 eV i. 10 T = 300K T = 400K 1 i wo 11 j © 1 = OUUK 1 i h-) -2.5 -2.0 -1.5 -1.0 -0.5 Forward Bias (V) Fig. 5 7 Forward Characteristics of a 3 kV 4H-SiC Schottky Rectifier: Impact of Operating Temperature.5.1.2 Forward Conduction: Fxperimental ResultsThe first high voltage silicon carbide Schottky rectifiers were developedat the Power Semiconductor Research Center (PSRC) in 1991 using thecommercially available 6H polytype6. The breakdown voltage of theseun-terminated diodes was limited by electric field enhancement at theedges. The breakdown voltage was subsequently increased to 1000 voltsby using an argon implanted edge termination7. The same approach
  • 113. Schottky Rectifiers 91enabled the development of high voltage Schottky diodes from 4H-SiCwith breakdown voltages of up to 1000 volts without edge termination8.The breakdown voltage of these diodes was extended to 1330 volts byusing the argon implanted edge termination9. The 4H-SiC Schottky rectifiers discussed above were fabricatedusing titanium as the barrier metal due to its low barrier height (1.1 eV).The on-state voltage drop for these 4H-SiC Schottky rectifiers was foundto be less than 1.1 volts at a current density of 100 A/cm2 consistent withthe calculated values in Fig. 5.3. Other groups have also reported thesuccessful fabrication of high voltage Schottky barrier rectifiers from4H-SiC by using various barrier metals. An on-state voltage drop of1.73V, 1.5V, and 1.12V was reported at an on-state current density of100 A/cm2 for diodes with breakdown voltage of 800V fabricated byusing gold, nickel and titanium5, respectively. The on-state voltage dropreduces as the barrier height decreases from 1.80 eV for gold to 1.1 eVfor titanium. Schottky rectifiers with a breakdown voltage of 1000 voltswere reported with on-state voltage drop of 1.78V and 1.61V, at an on-state current density of 100 A/cm2, by using nickel and platinum asbarrier metals10. These relatively larger on-state voltage drops areassociated with the larger barrier height of 1.59 eV and 1.39 eV fornickel and platinum, respectively. These demonstrations of low on-statevoltage drop in high voltage silicon carbide Schottky rectifiers haveencouraged the analysis of manufacturing issues11 leading to thedeployment of commercial products.5.2 Schottky Rectifier Structure: Reverse BlockingWhen a negative bias is applied to the Schottky rectifier, the voltage issupported across the drift region with the maximum electric field locatedat the metal-semiconductor contact as shown in Fig. 5.1. At a smallreverse bias voltage, the leakage current is determined by the saturationcurrent given in Eq. [5.5] as governed by the Schottky barrier height. Thesaturation current for 4H-SiC calculated by using this expression isshown in Fig. 5.8 for various temperatures. In comparison with silicon, itis possible to obtain a much larger barrier height in silicon carbide metal-semiconductor contacts due to the larger band gap. For this reason, thegraph extends to relatively large barrier heights. On the one hand, inorder to maintain a low on-state voltage drop, it is preferable to use a lowbarrier height as discussed in the previous section. On the other hand, as
  • 114. 92 SILICON CARBIDE POWER DEVICEScan be seen from Fig. 5.8, it is preferable to use a large barrier height toreduce the leakage current. A good compromise occurs for a barrierheight in the range of 1.0 to 1.3 eV. This can be achieved by usingtitanium as the Schottky contact metal6,8. 10° § 4H-SIC 5> 10-4 IO- 8 500 K I I 10- 450 K 400 K io- 1 350 K L^s / 300 K io- 2 1 0.7 0.9 1.1 1.3 1.5 1.7 1.9 Schottky Barrier Height (eV) Fig. 5.8 Saturation Current Density for 4H-SiC Schottky Rectifiers. In silicon Schottky rectifiers, it is well established that theleakage current is exacerbated by the Schottky barrier loweringphenomenon1. The barrier lowering is determined by the electric field atthe metal-semiconductor interface: A0 B = . [5.6] ^ A7t£owhere Em is the maximum electric field located at the metal-semiconductor interface. For a one-dimensional structure, the maximumelectric field is related to the applied reverse bias voltage (VR) by: 2qND Em=. (VR+Vbi) [5.7]In addition, it is necessary to include the effect of pre-avalanchemultiplication on the leakage current12. The multiplication coefficient
  • 115. Schottky Rectifiers 93(M) can be determined from the maximum electric field at the metal-semiconductor contact: f M 1-1.52 1-exp 4.33xl0" 2 4 ^ 9 X^ [5.8]where WD is the depletion layer width. The leakage current density for asilicon Schottky rectifier with drift region doping concentration of 1 x1016 cm"3 is shown in Fig. 5.9. The breakdown voltage for this case isabout 50 volts. The impact of including the Schottky barrier loweringand multiplication is shown in the figure to illustrate their relativecontributions. The barrier lowering effect increases the leakage currentby nearly an order of magnitude. The effect of including themultiplication coefficient is apparent at high voltages when the electricfield approaches the critical electric field for breakdown. This behavior isconsistent with commercially available silicon devices, which exhibit anorder of magnitude increase in leakage current from low reverse biasvoltages to the rated voltage (about 80 percent of the breakdownvoltage). io-2 | 50V Silicon Rectifier 3 With Barrier Lowering and Multiplication Barrier Height = 0.7 eV 1<H I 10- 4 With Barrier Lowering No Barrier Lowering 10- 5 10 20 30 40 50 Reverse Bias (Volts) Fig. 5.9 Leakage Current Density for a 50V Silicon Schottky Rectifier. Since the low specific on-resistance of the drift region in siliconcarbide devices is associated with the much larger electric fields in the
  • 116. 94 SILICON CARBIDE POWER DEVICESmaterial before the on-set of impact ionization, the Schottky barrierlowering in silicon carbide rectifiers is significantly larger than in silicondevices. For the case of a drift region doping level of 1 x 1016 cm"3 forboth silicon and 4H-SiC, the barrier lowering was found to be three timeslarger in silicon carbide at the breakdown voltage as shown in Fig. 5.10.In preparing this graph, the reverse voltage was normalized to thebreakdown voltage. 0 0.2 0.4 0.6 0.8 1.0 Fraction of Breakdown Voltage Fig. 5.10 Schottky Barrier Lowering for Silicon versus 4H-SiC Schottky Rectifiers. The enhanced Schottky barrier lowering in silicon carbidedevices leads to a more rapid increase in leakage current with increasingreverse bias as shown in Fig. 5.11. The leakage current is predicted bythis model to increase by three orders of magnitude when the reversevoltage approaches the breakdown voltage. In comparison, for silicon theincrease is significantly smaller as shown in Fig. 5.9. The increase inleakage current with applied reverse bias voltage was first reported forhigh voltage 6H-SiC Schottky rectifiers by Bhatnagar et al6. It was foundthat the increase in leakage current is about 6 orders of magnitude withincrease in reverse bias voltage. A similar observation was made later forSchottky rectifiers fabricated at PSRC using 4H-SiC8. Similar resultswere subsequently reported by other groups1314. Thus, the observed
  • 117. Schottky Rectifiers 95leakage current in silicon carbide rectifiers cannot be accounted for byusing the thermionic emission model with Schottky barrier lowering. 10- 3 3kV 4H-SIC Rectifier ! Barrier Height = 1.1 eV With Barrier Lowering and Tunneling With Barrier Lowering No Barrier Lowering 10- 1000 2000 3000 Reverse Bias (Volts) Fig. 5.11 Leakage Current Density for a 3kV 4H-SiC Schottky Rectifier. In order to explain the more rapid increase in leakage currentobserved in silicon carbide Schottky rectifiers, it is necessary to includethe field emission (or tunneling) component of the leakage current15. Thethermionic field emission model for the tunneling current leads to abarrier lowering effect proportional to the square of the electric field atthe metal-semiconductor interface. When combined with the thermionicemission model, the leakage current density can be written as: Js = A7" 2 exp .exp (CTEI) [5.9]where CT is a tunneling coefficient. A tunneling coefficient of 8 x 10"13cmVv2 was found to yield an increase in leakage current by six orders ofmagnitude as shown in Fig. 5.11 consistent with the behavior observed inreference [15] and the experimental results discussed earlier. As can benoted from Fig. 5.11, the inclusion of the tunneling model enhances theleakage current by another three orders of magnitude. As discussed above, the leakage current in silicon carbideSchottky rectifiers increases much more rapidly with reverse voltage
  • 118. 96 SILICON CARBIDE POWER DEVICESthan in silicon devices. Fortunately, larger barrier heights can be utilizedin silicon carbide devices to reduce the magnitude of the leakage currentdensity. This enables maintaining an acceptable level of powerdissipation in the reverse blocking mode. For example, in the case of the3kV 4H-SiC Schottky diode discussed above, the reverse powerdissipation at room temperature is less than 1 W/cm2 compared with anon-state power dissipation of 100 W/cm2. The expected increase inleakage current with temperature must of course be taken into account inorder to ensure than the reverse power dissipation remains below the on-state power dissipation for stable operation1.5.3 Schottky Rectifier Structure: Impact of Defects LOW BARRIER HEIGHT REGION SCHOTTKY METAL ^ ^ DEFECT DRIFT REGION SUBSTRATE 77777//////////////////////////A CATHODE Fig. 5.12 Schottky Rectifier with Localized Low Barrier Region.The impact of defects or surface inhomogeneities on the forward andreverse characteristics of silicon carbide high voltage Schottky rectifierswas first observed and analyzed at PSRC for diodes made from 6H-SiC16. These diodes exhibited a leakage current at low bias voltages(before the on-set of the tunneling currents) that was several orders ofmagnitude larger than calculated based upon the barrier height extractedfrom C-V measurements. Meanwhile, the forward characteristics at highcurrent density were consistent with those calculated using this barrierheight. This conundrum could be solved by postulating small regions of
  • 119. Schottky Rectifiers 97the contact with lower barrier height when compared with most of thecontact layer as illustrated in Fig. 5.12. It was speculated that the lowerbarrier height originates from the presence of defects in the siliconcarbide or the surface preparation process prior to Schottky metaldeposition. The influence of inhomogeneous contacts on silicon Schottkyrectifiers had been previously postulated by Tung17. Breakdown Voltage = 3000 V JF = 100 A/cm2 r<. -4 ^ ^ ^ ^ ^ - S3 I* u -5 s U u at -6 & DC Shoulder or inflection 3 -7 -1.0 -0.8 -0.6 -0.4 -0.2 0 Forward Bias (V) Fig. 5.13 Forward Characteristics of 3 kV 4H-SiC Schottky Rectifiers with 0.02 percent Inhomogeneous Contact Area. The impact of the inhomogeneous contact depends upon thereduction of the barrier height at the local region as well as its arearelative to the entire contact. The results of two dimensional numericalanalysis of a Schottky contact with a reduced barrier region operating inparallel with the main contact are discussed here to elucidate thephenomenon. The drift region parameters used for these simulations arethe same as those used earlier for the 3kV 4H-SiC Schottky rectifiers. Adefect region with an area of 0.02 percent of the total contact area will beconsidered with a total area of the simulated structure of 5 x 10"7 cm 2 .
  • 120. 98 SILICON CARBIDE POWER DEVICESThe work function for the defect area was chosen as 4.0 eV versus 4.5eV used for the main contact (i.e. a barrier reduction by 0.5 eV). Underthese conditions, a shoulder is observed in the forward characteristics, asshown in Fig. 5.13. This shoulder is associated with current flow throughthe low barrier contact region at smaller applied voltages. This can beconfirmed by looking at the currents through the main contact and thelow barrier (defect) contact as shown in Fig. 5.14. Breakdown Voltage = 3000 V -3 Main Contact Current J F = 100 A/cm2 < -4 c 3 u © Defect Contact Current 3 -V -8 -1.0 -0.8 -0.6 -0.4 -0.2 0 Forward Bias (V) Fig. 5.14 Forward Characteristics of 3 kV 4H-SiC Schottky Rectifiers with 0.02 percent Inhomogeneous Contact Area. From the forward characteristics shown above, it is apparent thatthe impact of the low-barrier defect region is not significant on the on-state voltage drop (indicated by the line at a current density of 100 A/cm2on the graphs). This is due to the high series resistance for such a smallcontact within the structure, although this series resistance is notproportional to the area of the defect region because of significantcurrent spreading within the drift region. However, the defect region hasa very significant impact on the reverse leakage current as shown in Fig.
  • 121. Schottky Rectifiers 995.15. It can be seen that the leakage current contributed from the lowbarrier (defect) region is four orders of magnitude larger than from themain contact in spite of a difference in area by a factor of 2 x 10"4. Thus,very small defects can have a large influence on the leakage current inthe silicon carbide Schottky contacts. The impact of changing the area ofthe defect region and the amount of barrier height lowering has beenreported in reference [16] for 6H-SiC Schottky rectifiers. Similar resultshave been more recently reported for 4H-SiC Schottky rectifiers1819,20.These diodes display a shoulder in the forward characteristics as shownby the above figures and a much larger leakage current than predicted bythe barrier height extracted from C-V measurements. A defect area ofabout 0.1 percent is indicated in the experimental results. The presenceof defects that may be responsible for the low barrier height regions hasbeen confirmed by EBIC measurements16. Breakdown Voltage = 3000 V •7I Defect Contact Current -8 / ; a •9 i u -10: t« u -li : > • • Main Contact Current -12 o .. 4 6 10 Reverse Bias (V) Fig. 5.15 Reverse Characteristics of 3 kV 4H-SiC Schottky Rectifiers with 0.02 percent inhomogeneous contact area.
  • 122. 100 SILICON CARBIDE POWER DEVICES5.4 Reliability IssuesThe low on-state voltage drop of high voltage silicon carbide Schottkyrectifiers and their excellent reverse recovery behavior has encouragedthe development of commercial products. However, for commercialacceptance, it is necessary to meet various reliability criteria forsemiconductor diodes. The results of the following tests on titanium 4H-SiC Schottky rectifiers have been reported: (a) Thermal cycling up to 400°C (b) Cycling between -55 and 150°C (1000 times) (c) High temperature reverse bias testing (150°C, 600V, 1000 hours) (d) High humidity, high temperature reverse bias testing (85°C, 85% relative humidity, 80V, 1000 hours)No failures were observed indicating that the reliability of silicon carbideSchottky rectifiers under reverse bias stress is excellent21.5.5 SummaryThe physics of operation of the silicon carbide Schottky rectifier hasbeen shown to be similar to that used to describe silicon devices in theforward conduction direction. However, the reverse leakage current insilicon carbide devices is significantly enhanced by the thermionic fieldemission (or tunneling) current at high reverse bias voltages. This is dueto the much larger electric field in silicon carbide devices whencompared with the silicon counterpart. Fortunately, the availability ofmuch larger Schottky barrier heights in silicon carbide, at the expense ofan increased on-state voltage drop, allows reducing the absolute valuesfor the leakage currents to a level where the reverse bias powerdissipation is below the forward bias power dissipation enabling stableoperation in circuits. A better approach is to shield the Schottky contactfrom the high electric field developed in the silicon carbide drift regionas discussed in the next chapter. It has been found that the presence ofsmall defects can greatly enhance the leakage current in silicon carbideSchottky rectifiers due to a localized barrier lowering phenomenon.However, the defect density in wafers has been reduced to the point atwhich commercial products are being deployed as companion diodes forIGBTs in motor control applications.
  • 123. Schottky Rectifiers 101References1 B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.2 B.J. Baliga, "Schottky Barrier Rectifiers and Methods of Forming theSame", U.S. Patent 5,612,567, March 18,1997.3 B.J. Baliga, "The Future of Power Semiconductor Technology",Proceedings of the JEEE, Vol. 89, pp. 822-832, 2001.4 B.J. Baliga, "Power Semiconductor Devices for Variable FrequencyDrives", Proceedings of the IEEE, Vol. 82, pp. 1112-1122, 1994.5 A. Itoh, T. Kimoto, and H. Matsunami, "High Performance of HighVoltage 4H-SiC Schottky Barrier Diodes", IEEE Electron DeviceLetters, Vol. 16, pp. 280-282, 1995.6 M. Bhatnagar, P.K. McLarty, and B.J. Baliga, "Silicon Carbide HighVoltage (400V) Schottky Barrier Diodes", IEEE Electron Device Letters,Vol. 13, pp. 501-503, 1992.7 D. Alok, B.J. Baliga, and P.K. McLarty, "A Simple Edge Terminationfor Silicon Carbide with Nearly Ideal Breakdown Voltage", IEEEElectron Device Letters, Vol. ED15, pp. 394-395, 1994.8 R. Raghunathan, D. Alok, and B.J. Baliga, "High Voltage 4H-SiCSchottky Barrier Diodes", IEEE Electron Device Letters, Vol. 16, pp.226-227, 1995.9 D. Alok, R. Raghunathan, and B.J. Baliga, "Planar Edge Terminationfor 4H-SiC Devices", IEEE Transactions on Electron Devices, Vol. 43,pp.1315-1317, 1996.10 V. Saxena, N. Nong, and A.J. Steckl, "High Voltage Ni and Pt SiCSchottky Barrier Diodes utilizing Metal Field Plate Termination", IEEETransactions on Electron Devices, Vol. 46, pp. 456-464, 1999." M. Treu, et al, "Challenges and First Results of SiC Schottky DiodeManufacturing using a 3 inch Technology", Silicon Carbide and RelatedMaterials - 2003, Material Science Forum, Vol. 457-460, pp. 981-984,2004.12 S. L. Tu and B. J. Baliga, "On the Reverse Blocking Characteristicsof Schottky Power Diodes", IEEE Transactions on Electron Devices,Vol. 39, pp. 2813-2814, 1992.13 F. Dahlquist, et al, " A 2.8kV, Forward Drop JBS Diode with LowLeakage", Silicon Carbide and Related Materials - 1999, MaterialScience Forum, Vol. 338-342, pp. 1179-1182, 2000.
  • 124. 102 SILICON CARBIDE POWER DEVICES14 Y. Sugawara, K. Asano, and R. Saito, "3.6kV 4H-SiC JBS Diodeswith Low RonS", Silicon Carbide and Related Materials - 1999, MaterialScience Forum, Vol. 338-342, pp. 1183-1186, 2000. 15 T. Hatakeyama and T. Shinohe, "Reverse Characteristics of a 4H-SiCSchottky Barrier Diode", Silicon Carbide and Related Materials - 2001,Material Science Forum, Vol. 389-393, pp. 1169-1172, 2002.16 M. Bhatnagar, B.J. Baliga, H.R. Kirk, and G.A. Rozgonyi, "Effect ofSurface Inhomogeneities on the Electrical Characteristics of SiCSchottky Contacts", IEEE Transactions on Electron Devices, Vol. 43, pp. 150-156,1996.17 R. T. Tung, "Electron Transport of Inhomogeneous SchottkyBarriers", Applied Physics Letters, Vol. 58, pp. 2821-2822, 1991.18 D. Defives, et al, "Barrier Inhomogeneities and ElectricalCharacteristics of Ti/4H-SiC Schottky Rectifiers", IEEE Transactions onElectron Devices, Vol. 46, pp. 449-455, 1999.19 F. Roccaforte, et al, "Electrical Characterization of InhomogeneousNiSi/SiC Schottky Contacts", Silicon Carbide and Related Materials -2003, Material Science Forum, Vol. 457-3460, pp. 869-872, 2004.20 H. Saitoh, T. Kimoto, and H. Matsunami, "Origin of Leakage Currentin SiC Schottky Barrier Diodes at High Temperatures", Silicon Carbideand Related Materials - 2003, Material Science Forum, Vol. 457-3460,pp. 997-1000, 2004.21 R. Rupp, et al, "Performance and Reliability Issues of SiC SchottkyDiodes", Silicon Carbide and Related Materials - 1999, Material ScienceForum, Vol. 338-342, pp. 1167-1170, 2000.
  • 125. Chapter 6 Shielded Schottky RectifiersIn the case of silicon Schottky rectifiers, it has been traditional to trade-off the on-state (or conduction) power loss against the reverse blockingpower loss by optimizing the Schottky barrier height. As the Schottkybarrier height is reduced, the on-state voltage drop decreases producing asmaller conduction power loss. At the same time, the smaller barrierheight produces an increase in the leakage current leading to largerreverse blocking power loss. It has been demonstrated that the power losscan be minimized by reducing the Schottky barrier height at the expenseof a reduced maximum operating temperature1. This optimization process is exacerbated by the rapid increase inthe leakage current with increasing reverse bias voltage due to theSchottky barrier lowering phenomenon. The first method proposed toameliorate the barrier lowering effect in vertical silicon Schottkyrectifiers utilized shielding by incorporation of a P-N junction23. Sincethe basic concept was to create a potential barrier to shield the Schottkycontact against high electric fields generated in the semiconductor byusing closely spaced P+ regions around the contact, this structure wasnamed the Junction-Barrier controlled Schottky (JBS) rectifier. In theJBS rectifier, the on-state current was designed to flow in the un-depletedgaps between the P+ regions when the diode is forward biased to preserveunipolar operation. In addition to reducing the leakage current, thepresence of the P+ regions was also shown to enhance the ruggedness ofthe diodes. Detailed optimization of the silicon JBS rectifiercharacteristics was achieved with sub-micron dimensions between the P+regions4. Subsequently, a novel silicon structure that utilizes the charge-coupling concept was proposed to reduce the resistance in the driftregion5. Since these structures utilized an electrode embedded within anoxide coated trench region that surrounds the metal-semiconductorcontact, this structure was named the Trench MOS Barrier controlled 103
  • 126. 104 SILICON CARBIDE POWER DEVICESSchottky (TMBS) rectifier. The performance of this structure was furtherenhanced by using a graded doping profile to create a device named the Graded-Doped Trench MOS Barrier controlled Schottky (GD-TMBS)rectifier6. This has allowed extending the breakdown voltage of siliconSchottky rectifiers to the 200 volt range78. Yet another method proposed to create a potential barrier underthe Schottky contact was the utilization of a second metal-semiconductorcontact with large barrier height surrounding the main Schottky contactwith a low barrier height9. Since a stronger potential barrier could becreated by locating the high barrier metal with a trench, this structurewas named the Trench Schottky Barrier controlled Schottky (TSBS)rectifier. In the previous chapter it was demonstrated that the increase inleakage current with reverse bias voltage is much stronger for the siliconcarbide Schottky rectifiers. This is due to a larger Schottky barrierlowering effect associated with the larger electric field in silicon carbidedrift regions and the onset of field emission (or tunneling) current. It istherefore obvious that the methods proposed to suppress the electric fieldat the Schottky contact in silicon diodes will have even greater utility insilicon carbide rectifiers. This chapter discusses the application of shielding techniques toreduce the electric field at the metal-semiconductor contact in siliconcarbide Schottky rectifiers. The physics of operation of these structures isanalyzed by using two-dimensional numerical analysis. It isdemonstrated that the JBS and TSBS concepts can be extended to siliconcarbide to achieve significant improvement in performance. However,the TMBS and GD-TMBS approaches are not appropriate for siliconcarbide because of the high electric field generated in the oxide leadingto its rupture. Experimental results on relevant structures are provided todefine the state of the development effort on shielded silicon carbideSchottky rectifiers.6.1 Junction Barrier Schottky (JBS) Rectifier StructureThe Junction Barrier controlled Schottky (JBS) rectifier structure isillustrated in Fig. 6.1. It consists of a P+ region placed around theSchottky contact to generate a potential barrier under the metal-semiconductor contact in the reverse blocking mode. The space betweenthe P+ regions is chosen so that there is an un-depleted region below the
  • 127. Shielded Schottky Rectifiers 105Schottky contact to enable unipolar conduction through the structure.The voltage drop across the diode is usually not sufficient to forward biasthe P-N junction. Low voltage silicon devices operate with on-statevoltage drops around 0.4 volts which is well below the 0.7 volts neededfor inducing strong injection across the P-N junction. The margin is evenlarger for silicon carbide due to its much larger band gap. Typical siliconcarbide Schottky rectifiers have on-state voltage drops of less than 1.5volts due to low specific resistance of the drift region. This is well belowthe 3 volts required to induce injection from the P-N junction.Consequently, the JBS concept is well suited for development of siliconcarbide structures with very high breakdown voltages. ANODE (SCHOTTKY METAL) ANODE (SCHOTTKY METAL) DEPL ETION REGION XT Potential Barrier N-DRIFT REGION CURRENT PATH N+ SUBSTRATE N*SUBSTRATE Y///////////////J^m v///////////////zmw CATHODE CATHODE Fig. 6.1 Junction Barrier controlled Schottky Rectifier Structure. The P+ region is usually formed by ion-implantation of P-typedopants using a mask with appropriate spacing to leave room for theSchottky contact. For processing convenience, the same metal layer isused to make an ohmic contact to the highly doped P+ region as well asto make the Schottky barrier contact to the N- drift region. The spacebetween the P+ regions must be optimized to obtain the best compromisebetween the on-state voltage drop, which increases as the space isreduced, and the leakage current, which decreases as the space isreduced.
  • 128. 106 SILICON CARBIDE POWER DEVICES6.1.1 JBS Rectifier Structure: Forward Conduction ModelAnalysis of the on-state voltage drop of the JBS rectifier requires takinginto consideration the current constriction at the Schottky contact and thespreading resistance of the drift region10. The current flow pattern in theforward conduction mode is illustrated in Fig. 6.1 with the dotted area.The on-state voltage drop for the JBS rectifier is sufficiently low so thatany injection from the P-N junction can be neglected resulting in nocurrent flow through the junction. The current through the Schottkycontact flows only within the un-depleted portion (with dimension d) ofthe drift region at the top surface. Consequently, the current density atthe Schottky contact (Jps) is related to the cell (or cathode) currentdensity (JFC) by: FS f") FC [6.1] (l; Depending up on the lithography used for device fabrication tominimize the size (dimension s) of the P+ region, the current density atthe Schottky contact can be enhanced by a factor of ten or more. Thismust be taken into account when computing the voltage drop across theSchottky contact: j J ^ FS FS r 2 [6.2] " q {AT After flowing across the Schottky contact, the current flowsthrough the un-depleted portion of the drift region. The resistance of thedrift region is larger than the specific on-resistance discussed in theprevious chapters due to current spreading from the Schottky contact tothe N+ substrate: R drift = Po{xj+wJj [6.3]The first term accounts for the resistance of the drift region between theP+ regions. The dimension d is determined by the cell pitch (p): d= p-s-WD [6.4]where WD is the depletion width. For silicon carbide Schottky rectifiers itis even more important to take the depletion width into account due to
  • 129. Shielded Schottky Rectifiers 107the large built-in potential (Vbi) for P-N junctions. As an approximation,the zero bias depletion width (W0) can be used: Wn [6.5]For a doping concentration of 1 x 1016 cm3, the zero bias depletion widthis about 0.6 microns, which is comparable to the cell dimensions. In addition, the resistance associated with the thick, highly dopedN+ substrate (Rsubs) can be included by taking the product of its resistivityand thickness. For the available substrates with a typical resistivity of0.02 Q-cm and thickness of 200 microns, the substrate contribution is 4 x10"4 Q-cm2. The on-state voltage drop for the JBS rectifier at a forwardcell current density JFc, including the substrate contribution, is then givenby: kT J FS VF = In • ( * drift ^subs I"*FC [6.6] AT 3.0 4H-SiC JBS Rectifier r I 1 " Barrier Height = 1.1 eV p=1.25 I p=1 .20 "" t I * p=1.15 - * p=1.10 • * > * s Ss*^" 1.0 -• V •V Schottky Rectifier ! to 0.5 10 100 1000 Forward Current Density (A/cm2) Fig. 6.2 Forward Characteristics of 3kV JBS Rectifiers. The forward characteristics of 3kV JBS rectifiers calculatedusing the above analytical approach are shown in Fig. 6.2 with the cell
  • 130. 108 SILICON CARBIDE POWER DEVICESpitch (p) as a parameter. The width of the P+ region (s) was kept at 0.5microns for this analysis. In comparison with the Schottky rectifiercharacteristics (shown by the dashed line in the figure), the increase inon-state voltage drop at a nominal forward current density of 100 A/cm2is small (less than 0.2 volts) as long as the cell pitch is more than 1.15microns. This cell pitch is sufficient to obtain substantial reduction of theelectric field at the metal-semiconductor contact as shown later in thechapter.6.1.2 JBS Rectifier Structure: Reverse Leakage ModelThe reverse leakage current in the JBS rectifier is reduced whencompared with the Schottky rectifier due to the smaller electric field atthe metal-semiconductor interface. In addition, the area of the Schottkycontact is a fraction of the total cell area resulting in a smaller reversecurrent contribution. The leakage current in the JBS rectifier can becalculated using the same expression as for the Schottky rectifier withthese adjustments: qbft bJBS JL AT exp .exp .exp (-<T£jBS ) [6.7] PJ kT J kTwhere CT is a tunneling coefficient (8 x 10"13 cm2/V2). In contrast withthe Schottky rectifier, the barrier lowering and the tunneling contributionis determined by the reduced electric field EJBs at the contact: A WE, JBS [6.8] Am = ne*The electric field EJBS is related to the reverse bias voltage (VP) at whichthe space between the P+ regions gets depleted by: E ^JBS •ft*>"-> = [6.9]where (3 is a coefficient used to account for the build up in the electricfield after pinch-off. The pinch-off voltage VP can be obtained from thedevice cell parameters:
  • 131. Shielded Schottky Rectifiers 109 V = " 1^{P-S)2-V» [6M] In the case of a cell pitch (p) of 1.25 microns with a P+ regionwith dimension s of 0.5 microns, the pinch-off voltage is 5.3 volts for adrift region with doping concentration of 1 x 1016 cm"3. Using a P of 10,the electric field at the Schottky contact is found to be reduced to about4.5 x 103 V/cm at a reverse bias of 50 volts. The calculated leakagecurrent for this electric field after accounting for the reduced contact areais about 8 x 10" A/cm2. Even if the electric field at the Schottky contactincreases to 1 x 106 V/cm corresponding to a reverse bias of 300 volts,the calculated leakage current is only 1 x 10"9 A/cm2, which is far smallerthan the values of about 1 x 10"4 A/cm2 near breakdown for the Schottkyrectifier. Thus, limiting the electric field by creating a potential barrierbelow the Schottky contact can be very beneficial to reducing theleakage current in silicon carbide Schottky rectifiers. In order todetermine the magnitude of the electric field reduction at the Schottkycontact it is necessary to resort to two dimensional numericalsimulations.6.1.3 JBS Rectifier Structure: Simulation ResultsThe case of a JBS rectifier with breakdown voltage of 3kV using a driftregion with doping concentration of 1 x 1016 cm"3 will be considered herefor comparison with the Schottky rectifier described in chapter 5. Thetwo-dimensional numerical simulations were performed with variousspacing between the P+ regions. The depth of the P+ region was alsovaried to examine its impact on the electric field reduction at theSchottky contact. In each case, the forward and reverse characteristicswere analyzed to look at the trade-off between on-state voltage drop andelectric field reduction at the Schottky contact. The P+ dimension V waskept at 0.5 microns for all the simulation structures. The forward characteristics of a 3kV JBS 4H-SiC rectifier isshown in Fig. 6.3 for the case of a cell pitch of 1.25 microns. The on-state voltage drop at a current density of 100 A/cm2 is about 0.1 voltslarger than that for the Schottky rectifier. This is similar to the resultsobtained using the analytical model in the previous section. The diodeexhibits the desirable positive temperature coefficient with no kinks inthe characteristics.
  • 132. no SILICON CARBIDE POWER DEVICES Breakdown Voltage = 3000 V 300 K 400 K 500 K -5: . 1 -^^r^/^-~^ C -6, a S -7 JF = 100 A/cm2 • 1 , 1 V > S -8; V o * to M l • O Cell Pitch = 1.25 microns -10 Work Function = 4.5 eV 1 -11 -2.5 -2.0 -1.5 -1.0 -0.5 0 Forward Bias (V) Fig. 6.3 Forward Characteristics of 3 kV 4H-SiC JBS Rectifier. Breakdown Voltage = 3000 V ° -7 S u •e -8 u s -9 W) O Cell Pitch = 1.00 microns -10 Work Function = 4.5 eV -11 -2.5 -2.0 -1.5 -1.0 -0.5 0 Forward Bias (V) Fig. 6.4 Forward Characteristics of 3 kV 4H-SiC JBS Rectifier.
  • 133. Shielded Schottky Rectifiers 111 However, as expected, the forward characteristics were found todegrade substantially when the cell pitch was reduced to 1.0 microns asshown in Fig. 6.4. The on-state voltage drop increases by 0.7 volts whenthe cell pitch is reduced, which is consistent with the analytical model. Itwill be shown later in this section that a cell pitch of 1.25 microns isadequate to suppress the electric field at the Schottky contact. The reason for the increase in the on-state voltage drop can beunderstood by examining the current flow in the cell under forward biasconditions. The current flow pattern for the structure with 1.00 microncell pitch is compared with that in the structure with 1.25 micron cellpitch in Fig. 6.5. The much greater constriction of the current at theSchottky contact is obvious for the smaller cell pitch Cell Pitch = 1.00 microns 0 0.2 0.4 0.6 0.8 1.0 Distance (microns) Cell Pitch = 1.25 microns 0 0.2 0.4 0.6 0.8 1.0 1.2 Distance (microns) Fig. 6.5 On-state Current Flow in 3 kV 4H-SiC JBS Rectifiers.
  • 134. 112 SILICON CARBIDE POWER DEVICES It is also worth noting that the current spreading occurs quiterapidly and becomes uniform at a depth of about 2 microns. Thisindicates an even lower series resistance for the drift region for the JBSrectifier than obtained by the model in the previous section. By using a45 degree spreading angle from the Schottky contact region into the driftregion, the lower drift region resistance can be modeled using: + pD{t-Xj-s-2WD)This lower drift region resistance favors silicon carbide JBS rectifier on-state performance approaching that of Schottky rectifiers. The reverse blocking characteristics were also studied by usingtwo-dimensional numerical simulations. The breakdown voltage of theJBS structure was found to be the same as that for the Schottky rectifiersfor the same drift region parameters. As expected, it was found that theelectric field at the Schottky contact was reduced by the potential barriercreated using the P-N junction. The degree of field reduction wasdependent on the spacing between the P+ regions as well as the depth ofthe P+ region. Cell Pitch = 1.25 microns Fig. 6.6 Electric Field distribution in a 4H-SiC JBS Rectifier.
  • 135. Shielded Schottky Rectifiers 113 A three-dimensional view of the electric field in a JBS structurewith cell pitch of 1.25 microns is shown in Fig. 6.6 at a reverse bias of3000 volts (just prior to breakdown). It can be seen that the highestelectric field occurs at the P-N junction and that the electric field issuppressed at the Schottky contact. It is worth pointing out that themaximum electric field at the Schottky contact occurs at the locationfurthest away from the P-N junction (at x = 1.25 microns for the structurein Fig. 6.6). Consequently, the largest leakage due to barrier loweringand tunneling components will occur at this location. For this reason, thehighest electric field at the Schottky contact will be used to analyze thereverse leakage characteristics for the JBS rectifiers. Cell Pitch = 1.25 microns 3.0 I I a © 3 Fig. 6.7 Electric Field variation with Reverse Voltage in a 4H-SiC JBS Rectifier. The electric field profile at the center of the Schottky contact isshown in Fig. 6.7 for the case of a cell pitch of 1.25 microns. It can beseen that the electric field at the surface under the contact is significantlyreduced when compared the peak electric field in the bulk. The peak ofthe electric field occurs at a depth of about 2 microns. At a reverse biasof 3000 volts, the electric field at the Schottky contact is only 1.4 x 106
  • 136. 114 SILICON CARBIDE POWER DEVICESV/cm compared with 2.8 x 106 V/cm at the maxima. An even greaterreduction of the electric field at the Schottky contact can be achieved byreducing the cell pitch. This is illustrated in Fig. 6.8 for the case of a cellpitch of 1.00 microns. Here, the electric field at the Schottky contact isonly 7 x 105 V/cm compared with 2.8 x 106 V/cm at the maxima. Cell Pitch = 1.00 microns 3.0 I I Distance (microns) Fig. 6.8 Electric Field variation with Reverse Voltage in a4H-SiC JBS Rectifier. The increase in the electric field at the Schottky contact withincreasing reverse bias voltage is charted in Fig. 6.9 for various cases ofthe cell pitch. The electric field at the contact becomes close to themaximum value in the bulk when the pitch is over 2 microns. Thus, thebenefits of using the JBS concept to suppress the electric field at theSchottky contact can be obtained only with carefully optimized spacing.With proper spacing, the reduction of the electric field provides thebenefit of reducing the Schottky barrier lowering and the leakage current.This is quantified in the graphs shown in Fig. 6.10 and Fig. 6.11,respectively, where the values were determined using the analyticalformulae with the electric field extracted from the simulations. With apitch of 1.25 microns, the Schottky barrier lowering is reduced from 0.22eVto0.14eV.
  • 137. Shielded Schottky Rectifiers 115 3.0 1 1 1 „-<> 3kV 4H-SiC JBS Rectifier Pitch (urn) , - - "s or i 2.00.y E m „(Bulk)& 2-0 r . 1.502 V 1.25fais i.o ,J) 1.00 1000 2000 3000 Reverse Bias (Volts) Fig. 6.9 Electric Field variation with Reverse Voltage in 4H-SiC JBS Rectifiers. 0.25 i r i 1 3kV 4H-SiC JBS Rectifier Pitch (jtm) 0.20 i .«. y - - ~ - — Schottky (--"" 2.00 s Rectifieri 0.15 ^ > " ^ 1.50 1.25i 0.10 VXy -4 1.00 osr 1000 2000 3000 Reverse Bias (Volts) Fig. 6.10 Schottky Barrier Lowering in 4H-SiC JBS Rectifiers.
  • 138. 116 SILICON CARBIDE POWER DEVICES The impact of ameliorating the Schottky barrier loweringphenomenon on the leakage current is quite dramatic from siliconcarbide Schottky rectifiers because of the strong dependence of thetunneling component on the electric field. A reduction in the leakagecurrent by five orders of magnitude is observed at high reverse biasvoltages, as shown in Fig. 6.11, demonstrating the advantage of utilizingthe junction barrier concept. From this point of view, the JBS structureoriginally proposed for silicon rectifiers is even more utilitarian forsilicon carbide rectifiers. 0 1000 2000 3000 Reverse Bias (Volts) Fig. 6.11 Leakage Current in 4H-SiC JBS Rectifiers. In addition to the spacing between the P-N junctions, thepotential barrier formed under the Schottky contact is dependent uponthe depth of the P+ region. The effect of changing the junction depthfrom 0.5 microns in the previous structures to a larger (0.9 microns) andsmaller (0.1 microns) value was analyzed using two-dimensionalnumerical simulations. It was found that the breakdown voltage reducedto 2550 volts for the larger junction depth. The reason for this is evidentin the three dimensional view of the electric field in this structure shownin Fig. 6.12. An enhancement in the electric field occurs at the corner ofthe P+ region leading to reduction of the breakdown voltage
  • 139. Shielded Schottky Rectifiers 117 Junction Depth = 0.9 microns Fig. 6.12 Electric Field distribution in a4H-SiC JBS Rectifier. 3.0 1 1 I"1 > 3kV 4H-SIC JBS Rectifier 0.10 „4 ^E E ,£>* ^.(Bulk)& 2-0 ^ " ^ " ^ r^s^ P* Depth (jim)I S i.o 0.5 0.90 1000 2000 3000 Reverse Bias (Volts)Fig. 6.13 Electric Field variation with Reverse Voltage in 4H-SiC JBS Rectifiers.
  • 140. 118 SILICON CARBIDE POWER DEVICES The electric field at the Schottky contact for the various junctiondepths is compared in Fig. 6.12 for a cell pitch of 1.25 microns. In thecase of the 0.9 micron junction depth, the data extends to 2500 voltsbecause of the premature breakdown discussed above. On the one hand,it is apparent that there is very little suppression of the Schottky barrierlowering when the junction depth is reduced to 0.1 microns. On the otherhand, it can be seen that the electric field reduction is the same for thejunction depths of 0.5 and 0.9 microns. Consequently, a junction depth ofmore than 0.5 microns is not required and is detrimental to both the on-state voltage drop and the breakdown voltage of the JBS rectifierstructure.6.1.4 JBS Rectifiers: Experimental ResultsThe first high voltage silicon carbide JBS rectifiers were reported in1997 after the evolution of adequate technology for ion-implantation andactivation of P-type dopants1112. These structures were sometimeserroneously labeled as Merged PN Schottky (MPS) rectifiers11. The MPSconcept was originally proposed for improving the performance of highvoltage silicon rectifiers13. In the MPS concept, the P-N junction is usedto inject minority carriers into the drift region and modulate (reduce) theresistance in series with the Schottky contact. When compared to PiNrectifiers, the MPS structure has been found to contain a smaller storedcharge leading to an improved trade-off between on-state voltage dropand reverse recovery characteristics for silicon rectifiers. As alreadypointed out, the very low resistance in the drift region of high voltagesilicon carbide rectifiers does not warrant the modulation of itsconductivity with the injection of minority carriers that degrade theswitching performance. It is therefore appropriate to use the JBSnomenclature for the high voltage silicon carbide structures rather thanthe MPS moniker. In the first JBS rectifiers12 with breakdown voltage of 700 voltsachieved by using 9 micron thick epitaxial layers with doping level of 3x 1015 cm", the addition of the P+ regions to the Schottky contact wasfound to result in an improvement in the breakdown voltage and leakagecurrent. In spite of a reduction of the electric field at the titaniumSchottky contact consistent with that shown in Fig. 6.9, the reduction ofthe leakage current was only by two orders of magnitude. However, theincrease in the on-state voltage drop was small, similar to that shown in
  • 141. Shielded Schottky Rectifiers 119Fig. 6.3. Subsequently, the breakdown voltage of the JBS rectifier wasextended to 2.8 kV14 by using 27 micron thick epitaxial layers withdoping concentration of 3 x 1015 cm3. The on-state voltage drop for theseJBS diodes was 2.0 volts versus 1.8 volts observed for the Schottkydiodes. In this study, the leakage current for the Schottky diode wasreported to increase with reverse voltage by a factor of 106 while that forthe JBS diode increased by only a factor of 103. This behavior isconsistent with the simulation results shown in Fig. 6.11. Subsequent work1516 on JBS rectifiers confirmed the benefits ofusing the junction barrier concept for reducing the leakage current. Inaddition, it was found that the surge current capability of the diodes wasenhanced when compared with Schottky diodes. In Schottky rectifiers,the on-state voltage drop becomes extremely large (~ 30 volts) undersurge current levels (current density above 1000 A/cm2) leading to theobservation of destructive failures. In contrast, the injection of minoritycarriers at applied voltages above 3.5 volts in the JBS rectifier enablesreduction of the on-state voltage drop under surge current levelspreventing destructive failures. Further, unlike Schottky rectifiers, theJBS rectifiers were found to exhibit a positive temperature coefficient forthe on-state voltage drop at a current density of 100 A/cm2 as shown inFig. 6.3. Thus, the increased resistance created by the P+ regions in theJBS rectifiers had the benefit of compensating for the reduction involtage drop across the Schottky contact with increasing temperature. Most recently17, the breakdown voltage of the JBS rectifier hasbeen extended to 4.3 kV using a 30 micron thick drift layer with dopingconcentration of 2 x 1015 cm"3. The leakage current for these diodes wasreported to increase by 3 orders of magnitude with reverse bias whencompared with 6 orders of magnitude for the Schottky diode. Thisbehavior is consistent with the results of the modeling discussed abovebased upon the reduced electric field at the metal-semiconductorinterface. For this reduced doping concentration, an optimum spacing of9 microns between the P+ regions was observed to provide the bestcharacteristics. In conclusion, the JBS concept has been found to be veryvaluable for reducing the leakage current in silicon carbide Schottkyrectifiers with a modest increase in the on-state voltage drop. Thepresence of the P+ regions used to form the potential barrier under theSchottky contact, creates the added benefit of improving the surgecurrent handling capability.
  • 142. 120 SILICON CARBIDE POWER DEVICES6.2 Trench MOS Barrier Schottky (TMBS) Rectifier Structure ANODE (SCHOTTKY METAL) METAL or V///////////A POLYSILICON OXIDE Potential Barrier N-DRIFT REGION N+ SUBSTRATE vz^m^^^m CATHODE Fig. 6.14 Trench MOS Barrier controlled Schottky (TMBS) Rectifier Structure.The Trench MOS barrier Schottky Rectifier (TMBS) structure, shown inFig. 6.14, was originally proposed for silicon Schottky rectifiers518 toachieve charge coupling between the electrode in the trench and thedopant charge in the drift region. The charge coupling allows for veryhigh doping concentration in the drift region while maintaining abreakdown voltage above the theoretically predicted values for one-dimensional parallel plane junctions. The high drift region dopingreduces the series resistance of the drift region resulting in low on-statevoltage drop for Schottky rectifiers with higher breakdown voltages. Thisconcept, particularly when enhanced with a linearly graded dopingprofile6, has been shown to produce excellent silicon Schottky rectifierswith breakdown voltages of 50 to 100 volts19. In addition, the electricfield at the Schottky contact can be reduced by the formation of apotential barrier due to extension of the depletion region from thesidewalls of the trench. Recently, there have been attempts to apply the TMBS conceptto silicon carbide Schottky rectifiers2021. This approach is misdirectedbecause of two problems. Firstly, the doping concentration in the driftregion for high voltage silicon carbide structures is very high when
  • 143. Shielded Schottky Rectifiers 121compared with silicon as shown earlier. It is therefore unnecessary toutilize charge coupling to enhance the doping unless the operatingvoltages are above 5000 volts. Secondly, the electric field within thesilicon carbide drift regions is an order of magnitude larger than withinsilicon devices. This creates an equally higher electric field inside theoxide used for the TMBS structure. The oxide can consequently besubjected to field strengths that induce failure by rupture. These issuesare discussed with the aid of numerical simulations in this section of thechapter.6.2.1 TMBS Rectifier Structure: Simulation ResultsTwo dimensional numerical simulations of the TMBS structure wereperformed using a drift region with doping concentration of 1 x 101 cm"3and thickness of 20 microns for comparison with the Schottky and JBSstructures already discussed in this chapter. The device cell, shown inFig. 6.14, had a pitch of 1 micron. The trench width and mesa width werealso 1 micron. Note that only half the trench and mesa widths areillustrated in Fig. 6.14. A trench depth of 1 micron was used with anoxide thickness of 0.1 microns (1000 Angstroms). Bias Voltage = 1500 V Trench Oxide Corner Fig. 6.15 Electric Field distribution in a4H-SiC TMBS Rectifier.
  • 144. 122 SILICON CARBIDE POWER DEVICES A three dimensional view of the electric field distribution in theupper part of the TMBS structure is shown in Fig. 6.15 at a reverse biasof 1500 volts. As expected, there is a reduction of the electric field at theSchottky contact due to the potential barrier created by the trench MOSstructure. This reduction of the electric field at the Schottky contact canbe clearly observed in Fig. 6.16 where the electric field profile is shownat the center of the mesa region (location B in Fig. 6.14). The peak of theelectric field in the silicon carbide occurs at a depth of about 1 micronwith much lower values at the surface. Thus, the TMBS concept iseffective in terms of reducing the Schottky barrier lowering and hencethe leakage current. Unfortunately, this improvement cannot be utilizedbecause of the very high electric field in the oxide. Cell Pitch = 1.00 microns 5 10 15 20 Distance (microns) Fig. 6.16 Electric Field variation with Reverse Voltage in a 4H-SiC TMBS Rectifier. The high electric field in the oxide is evident in Fig. 6.15 at areverse bias of only 1500 volts for a drift region capable of supporting3000 volts. The oxide field has reached a value close to 1 x 107 V/cm,which makes its rupture likely. This problem is exacerbated by the fieldenhancement at the trench corner (location A in Fig. 6.14). The
  • 145. Shielded Schottky Rectifiers 123magnitude of the electric field in the oxide can be observed more clearlyin Fig. 6.17. There is a jump in the electric field at the oxide-semiconductor interface due to the difference in dielectric constants. At areverse bias of 1500 volts, the electric field in the oxide has reached avalue of almost 1 x 107 V/cm, the breakdown strength of silicon dioxide.The oxide fields at other reverse bias voltages are indicated by the arrowsin the figure. For reliable operation, the electric field in the oxide willhave to be kept below 3 x 106 V/cm. This will limit the maximumoperating reverse voltage to less than 500 volts. Such a severe reductionof the reverse blocking capability removes most the advantages of usingsilicon carbide as the semiconductor material. Consequently, the ad hocapplication of a structure developed for silicon Schottky rectifiers is notwarranted for silicon carbide. In fact, the reported breakdown voltages ofthe experimentally fabricated devices20 were only 100 volts even for anepitaxial layer doping concentration of 6 x 1015 cm3. Cell Pitch = 1.00 microns 1.0 •1500 V ^ 0.8 -1000 V S u > —Oxide Electric Field Reverse Bias © 0.6 500 V 1500 V 2 1000 V S 0.4 500 V B 100 V 3 0.2 5 10 15 20 Distance (microns) Fig. 6.17 Electric Field variation with Reverse Voltage in a 4H-SiC TMBS Rectifier.
  • 146. 124 SILICON CARBIDE POWER DEVICES -4 *T -6 e >M >H 3 -7 u i- 0 -8 1- O = . -9 Cell Pitch = 1.00 microns BJ) o Work Function = 4.5 eV h-l -10 -11 -2.5 -2.0 -1.5 -1.0 -0.5 0 Forward Bias (V) Fig. 6.18 Forward Characteristics of 3 kV 4H-SiC TMBS Rectifier. For the sake of completeness, the forward characteristicsobtained by numerical simulations for the TMBS 4H-SiC rectifier areshown in Fig. 6.18 at various temperatures. The on-state voltage drop atthe nominal current density of 100 A/cm2 is similar to that observed forthe JBS rectifier. Although the on-state voltage drop is low, there is noparticular advantage when compared with the JBS rectifier. In fact, asalready pointed out, the JBS rectifier has good surge current handlingcapability due to the presence of the P-N junctions which can injectminority carriers at higher on-state voltage drops. In the absence of thisfeature, the TMBS rectifier will have the same problems with destructivefailure at surge current levels as the ordinary Schottky rectifier.6.3 Trench Schottky Barrier Schottky (TSBS) Rectifier StructureIn the previous section, it has been demonstrated that the shielding of themetal-semiconductor contact to reduce the electric field suppressesleakage current at high voltages. The potential barrier that must becreated for the shielding of the contact can also be produced by using
  • 147. Shielded Schottky Rectifiers 125another Schottky contact placed adjacent to the main Schottky contact.The second Schottky contact must have a larger barrier height than themain Schottky contact so that the leakage current from this contact issmall despite the high electric field at its interface with thesemiconductor. In addition, it is preferable to locate the high barrierheight metal contact within a trench surrounding the main low barriermetal Schottky contact as illustrated in Fig. 6.19. The trench architectureenhances the potential barrier under the main Schottky contact incomparison with a planar structure. ANODE (LOW BARRIER METAL) Potential Barrier N-DRIFT REGION N+ SUBSTRATE CATHODE Fig. 6.19 Trench Schottky Barrier controlled Schottky (TSBS) Rectifier Structure. All of the above features were first proposed for improvement ofSchottky barrier rectifiers in a patent9 issued in 1993. This patentdescribes devices with a high barrier metal located in trenches etchedaround the main low barrier metal Schottky contact with variousgeometries, such a stripes or cellular configurations. A simple method forfabrication of the device is also described. It consists of depositing thelow barrier metal and patterning it to expose areas for etching thetrenches. The trenches are then formed using the metal as the maskinglayer. The high barrier metal is then deposited into the trenches and overthe low barrier metal to complete the cell structure. The TSBS conceptwas not pursued for silicon devices due to the success of the JBS andTMBS concepts. However, it is particularly suitable for silicon carbide
  • 148. 126 SILICON CARBIDE POWER DEVICESdevices because it eliminates the need for formation of P-N junctionswhich require very high temperature anneals that can degrade thesemiconductor surface. Due to the large band gap of silicon carbide, it ispossible to produce high barrier Schottky contacts by using metals suchas nickel in conjunction with low barrier main Schottky contacts such astitanium. In the TSBS structure, the on-state current flow occurs via thelow barrier main metal contact. The same analytical model developedearlier for the JBS rectifier can also be applied to the TSBS structure.The increase in resistance of the drift region due to current constriction atthe main Schottky contact must be accounted for. However, as alreadydiscussed for the JBS rectifiers, the increase in the drift region resistanceis small as long as the mesa width is sufficiently large to prevent the zerobias depletion width from pinching it off completely. In the same vein, the reverse characteristics of the TSBSstructure can be analyzed by using the same methodology alreadydescribed for the JBS rectifier. However, the leakage current from thehigh barrier metal (JIXHB)) must to be added to the suppressed leakagecurrent from the main low barrier metal (JL<LB)): J UTSBS) ~ J L(LB) J L(HB) I 6.12]The leakage current from the low barrier main metal contact is given by: "bTSBS " exp [ 6.13] kT V kT jwhere CT is a tunneling coefficient (8 x 10"13 cm2/V2). The barrierlowering and the tunneling contributions are determined by the reducedelectric field ETSBS at the main contact: I Q&TSBS WmBs=A:Lr^ Ane I6-14! sThe electric field ETSBS is related to the reverse bias voltage (VP) at whichthe space between the P+ regions gets depleted by: ETSBS =J^JL(0VP+Vbi) [6.15] S
  • 149. Shielded Schottky Rectifiers 127where P is a coefficient used to account for the build up in the electricfield after pinch-off. In contrast, the leakage current from the high barriermetal contact is given by: , , = d AT2exp V0b).pvC A D . . J<lM>bHB - .cxp(CTElB)[6.13] L(HB) PJ kT kT Jwhere CT is a tunneling coefficient (8 x 10"13 cm2/V2). The barrierlowering and the tunneling contributions are determined by the electricfield E H B at the unprotected high barrier contact:The electric field EHB is determined by the applied reverse bias voltage(VA): EHB=Jrf£-(YA+Vil) [6.15]It has been found that the leakage current contribution from the highbarrier metal can become comparable to that from the main low barriermetal as the reverse bias voltage approaches the breakdown voltage.6.3.1 TSBS Rectifier Structure: Simulation ResultsFor comparison with previously described structures, TSBS rectifierswith breakdown voltage of 3kV using a drift region with dopingconcentration of 1 x 1016 cm"3 will be considered here. The two-dimensional numerical simulations of the structures were performed withvarious mesa widths (spacing m in Fig. 6.19). The depth of the trench(dimension t in Fig. 6.19) was also varied to examine its impact on theelectric field reduction at the Schottky contact. In each case, the forwardand reverse characteristics were analyzed to look at the trade-off betweenon-state voltage drop and electric field reduction at the Schottky contact.The trench width was kept at 1 micron for all the simulation structures.Note that only half the trench is shown in Fig. 6.19. A work function of4.5 eV, corresponding to a barrier height of 0.8 eV, was used as beforefor the main Schottky contact. A work function of 5.0 eV, correspondingto a barrier height of 1.3 eV, was used for the high barrier Schottkycontact within the trenches.
  • 150. 128 SILICON CARBIDE POWER DEVICES Trench Depth = 0.5 microns 300 K 400 K 500 K -5 rrr^ ^r— ~ ~ ~ ~^~~"-~^ 6 ¥" . !_ ^ 1* 3 -7- i J F = 100 A/cm 2 : 7 u ^ 9 l " DC O J -10 i Cell Pitch = 1.00 micron -11 i -2.5 -2.0 -1.5 -1.0 -0.5 Forward Bias (V) Fig. 6.20 Forward Characteristics of 3 kV 4H-SiC TSBS Rectifier. Trench Depth = 0.5 microns -4 300 K 400 K 500 K -2.5 -2.0 -1.5 -1.0 -0.5 Forward Bias (V) Fig. 6.21 Forward Characteristics of 3 kV 4H-SiC TSBS Rectifier.
  • 151. Shielded Schottky Rectifiers 129 The forward characteristics of a 3kV JBS 4H-SiC rectifier areshown in Fig. 6.20 for the case of a cell pitch of 1.00 micron at varioustemperatures. The on-state voltage drop at a current density of 100 A/cm2 is about 0. i volts larger than that for the Schottky rectifier. The on-statevoltage drop increases by 0.3 volts, as shown in Fig. 6.21, when the cellpitch is reduced to 0.75 microns (by decreasing the mesa width to 0.25microns). This is due to the stronger constriction of current flow underthe main Schottky contact. Note that the increase in on-state voltage dropis not as severe for the TSBS structure as for the JBS structure for thesame cell pitch. This is because of the reduced zero bias depletion widthin the TSBS structure due to the smaller potential across the high barrierto semiconductor interface when compared with that across the P-Njunction. The reason for the increase in the on-state voltage drop in theTSBS structure can be understood by examining the current flow in thecell under forward bias conditions. The current flow pattern for thestructure with 1.00 micron cell pitch is shown in Fig. 6.22. Theconstriction of the current at the main Schottky contact is not as strong asthat observed in Fig. 6.5 for the JBS rectifier structure with the same 1.00micron cell pitch. It is worth pointing out that the current spreadingoccurs quite rapidly and becomes uniform at a depth of 1 micron.Consequently, the model for the drift resistance described by Eq [6.11] issuitable for the TSBS rectifier structure as well. This lower drift regionresistance favors silicon carbide TSBS rectifier on-state performanceapproaching that of Schottky rectifiers. Cell Pitch = 1.00 micron Fig. 6.22 On-state Current Flow in a 3 kV 4H-SiC TSBS Rectifier.
  • 152. 130 SILICON CARBIDE POWER DEVICES Trench Depth = 0.5 microns -4i Low Barrier Metal -5 2 rrent] -6 -7- JF = 100 A/cm2 5 rward -8 o ^ High Barrier Metal 1 -9 / -. W O / J / Cell Pitch = 1 micron -mi v _ -ii -2.5 -2.0 -1.5 -1.0 -0.5 0 Forward Bias (V) Fig. 6.23 Current Distribution in a 3 kV 4H-SiC TSBS Rectifier. The relative current flow between the low and high barrier metalcontacts in the TSBS structures can be observed in Fig. 6.23 for the caseof a cell pitch of 1 micron. The current through the high barrier metal isabout 5 orders of magnitude less than that through the low barrier metal.The on-state voltage drop for the TSBS rectifier is therefore controlledby the barrier height of the main contact metal. The reverse blocking characteristics of the TSBS structure werealso studied by using two-dimensional numerical simulations. Thebreakdown voltage of the TSBS structure was found to be the same (~3000 volts) as that for the Schottky rectifiers for the same drift regionparameters. The current flowing through the high and low barrier metalsis shown in Fig. 6.24 as a function of the reverse bias voltage. It can beseen that the leakage current contribution from the main Schottky contactdominates at reverse bias voltages up to 2000 volts due to its low barrierheight. However, the exponential increase in leakage current with reversebias on the unprotected high barrier metal contact allows its leakagecurrent to catch-up and then exceed the leakage current of the maincontact at a reverse bias of 2900 volts.
  • 153. Shielded Schottky Rectifiers 131 Trench Depth = 0.5 microns - l i Cell Pitch = 1 micron <f -13 . W Low Barrier Metal < 2 Ji / u * ~ 1 j L ex | High Barrier Metal / v on DreaKaown J -16 .17 , . , .—1 P • P . r • - - 4 p , — , , . r- 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Reverse Bias (kV)Fig. 6.24 Reverse Blocking Characteristics of a 3 kV 4H-SiC TSBS Rectifier. Bias Voltage = 3000 V Fig. 6.25 Electric Field distribution in a4H-SiC TSBS Rectifier.
  • 154. 132 SILICON CARBIDE POWER DEVICES As expected, it was found that the electric field at the mainSchottky contact was reduced by the potential barrier created using thehigh Schottky barrier metal. The degree of field reduction was dependenton the spacing between the trench regions as well as the depth of thetrench. A three-dimensional view of the electric field in a TSBS structurewith cell pitch of 1.00 micron is shown in Fig. 6.25 at a reverse bias of3000 volts (just prior to breakdown). It can be seen that the highestelectric field occurs at the high barrier metal contact with someenhancement at the trench corner, and that the electric field is suppressedat the main Schottky contact. As in the case of the JBS rectifier, the maximum electric field atthe main Schottky contact occurs at the location furthest away from thetrench (at x = 1.00 micron for the structure in Fig. 6.25). Consequently,the largest barrier lowering and tunneling components will occur at thislocation. For this reason, the highest electric field at the Schottky contactwill be used to analyze the reverse leakage characteristics for the TSBSrectifiers. Cell Pitch = 1.00 micron 3.0 I I Distance (microns) Fig. 6.26 Electric Field variation with Reverse Voltage in a 4H-SiC TSBS Rectifier.
  • 155. Shielded Schottky Rectifiers 133 The electric field profile at the center of the Schottky contact isshown in Fig. 6.26 for the case of a cell pitch of 1 micron. It can be seenthat the electric field at the surface under the contact is significantlyreduced when compared the peak electric field in the bulk. The peak ofthe electric field occurs at a depth of about 1 micron. At a reverse bias of3000 volts, the electric field at the Schottky contact is only 1 x 106 V/cmcompared with 2.85 x 106 V/cm at the maxima in the bulk. An evengreater reduction of the electric field at the Schottky contact can beachieved by reducing the cell pitch. This is illustrated in Fig. 6.27 for thecase of a cell pitch of 0.75 microns. Here, the electric field at theSchottky contact is only 2 x 105 V/cm compared with 2.85 x 106 V/cm atthe maxima in the bulk. Cell Pitch = 0.75 microns 3.0 I Fig. 6.27 Electric Field variation with Reverse Voltage in a4H-SiC TSBS Rectifier. The increase in the electric field at the Schottky contact withincreasing reverse bias voltage is charted in Fig. 6.28 for various cases ofthe cell pitch with the trench depth held constant at 0.5 microns. Theelectric field at the contact becomes close to the maximum value in thebulk when the pitch is over 2 microns. Thus, the benefits of using theTSBS concept to suppress the electric field at the Schottky contact can be
  • 156. 134 SILICON CARBIDE POWER DEVICESobtained only with carefully optimized spacing which is slightly smallerthan for the JBS rectifier22. With proper spacing, the reduction of theelectric field provides the benefit of reducing the Schottky barrierlowering and the leakage current. 3.0 ^> 3kV 4H-SiC TSBS Rectifier +* r- Pitch (un) E r m.,(Bulk) f 1 1.50 £ 2.0 n ^ 1 I s I... j f ^ ^ , 1.00 I /y — i i 0.75 [—" 1 — 1000 2000 3000 Reverse Bias (Volts) Fig. 6.28 Electric Field variation with Reverse Voltage in 4H-SiC TSBS Rectifiers. The protection of the main Schottky contact against barrierlowering is quantified in the graphs shown in Fig. 6.29 and Fig. 6.30,respectively, where the values were determined using the analyticalformulae with the electric field extracted from the simulations. With apitch of 1 micron, the Schottky barrier lowering is reduced from 0.22 eVto 0.12 eV. The impact of ameliorating the Schottky barrier loweringphenomenon on the leakage current is quite dramatic for silicon carbideSchottky rectifiers because of the strong dependence of the tunnelingcomponent on the electric field. A reduction in the leakage current byfive orders of magnitude is observed at high reverse bias voltages, asshown in Fig. 6.30, demonstrating the advantage of utilizing the potentialbarrier to suppress the leakage current from the main contact. (Note thatthe leakage current from me high barrier metal was neglected in theseplots.) The TSBS structure is therefore quite effective for improving thereverse blocking characteristics of high voltage silicon carbide rectifiers.
  • 157. Shielded Schottky Rectifiers 1350.25 I I 3kV 4H-SIC TSBS Rectifier0.200.150.100.05 1000 2000 3000 Reverse Bias (Volts) Fig. 6.29 Schottky Barrier Lowering in 4H-SiC TSBS Rectifiers.103 1 1 1 > 3kV 4H-SIC TSBS Rectifiers . * • * - "" ^ Schottky10"* r** Rectifier V^ •^ Pitch (urn) •>* r~ , 1.50 • >f sio-» 1.00 1 1 I 0.7510- 1000 2000 3000 Reverse Bias (Volts) Fig. 6.30 Leakage Current in 4H-SiC TSBS Rectifiers.
  • 158. 136 SILICON CARBIDE POWER DEVICES In addition to the mesa width, the potential barrier formed underthe main Schottky contact in the TSBS structure is dependent upon thedepth of the trench. The effect of changing the trench depth from 0.5microns in the previous structures to larger values was analyzed usingtwo-dimensional numerical simulations. In addition, the case with a zerotrench depth (or a planar structure) was also considered. 4.0 1 1 1 1 Tre nch 3kV 4H-SiC TSBS Rectifier )th(nm) - S -4 L 0 4i 3.0 > Schottky r ^ A Diode r^>-^ I 2.0 S^"" <J •c f>^ .£ 1.0 AT r 0.75 •——H F — 1 1i 1i- 1i / 1.00 1000 2000 3000 Reverse Bias (Volts) Fig. 6.31 Electric Field variation with Reverse Voltage in 4H-SiC TSBS Rectifiers. The electric field at the Schottky contact for the different trenchdepths is compared in Fig. 6.31 for a cell pitch of 1 micron. It can beseen that the electric field at the Schottky contact (location B in Fig.6.19) for a trench depth of 1 micron is significantly (~ 5x) smaller thanfor the trench depth of 0.5 microns. This is beneficial for reducing theSchottky barrier lowering and consequently the leakage current as shownin Fig. 6.32 and Fig. 6.33, respectively. The improvement in the leakagecurrent by many orders of magnitude, when compared with the Schottkyrectifier, is quite evident. However, in the case of reducing the trenchdepth to zero (i.e. a planar structure), it was found that there was only aslight reduction of the electric field at the main Schottky contact for thecase of a cell pitch of 1 micron, as shown in Fig. 6.31. It is thereforenecessary to create a trench to house the high barrier metal adjacent to
  • 159. Shielded Schottky Rectifiers 137the main low barrier Schottky contact to get the full benefits of the TSBSconcept. 0.25 1 1 1 1 3kV 4H-SiC TSBS Rectifier .-.-" K — ^ & 0.20 .i r •c Tre nch £ 0.15 Schottky De[>th Qim) — o t -J Diode i* , 0.50 V •c i; o.io t 0.75 p a ^ , I / , • • — l__ 1| 1L i.oo J 0.05 u in v^ 1 1h 1 1000 2000 3000 Reverse Bias (Volts) Fig. 6.32 Schottky Barrier Lowering in 4H-SiC TSBS Rectifiers. 10- 3 • • . ^ 3kV 4H-SiC TSBS Rectifiers f ^ •^ p 10-4 Schottky ^ Rectifier ^< a r* ." Tre nch >f Dep th(jun) a O 1- 09 . 4 I 0.50 V ps=——< K "* » — < > •< 1 11 1.00 1 1I 1l — 1 10 12 1000 2000 3000 Reverse Bias (Volts) Fig. 6.33 Leakage Current in 4H-SiC TSBS Rectifiers.
  • 160. 138 SILICON CARBIDE POWER DEVICES6.3.2 TSBS Rectifiers: Experimental ResultsThe TSBS concept for improving the performance of silicon carbideSchottky rectifiers was first simultaneously explored at PSRC23 andPurdue University24. Titanium was used as the main Schottky contactmetal due to its relatively low barrier height (1.1 eV) on 4H-SiC whilenickel was used in the trenches as the high barrier height (1.7 eV) metal.For an epitaxial layer with doping concentration of 3 x 1015 cm"3 andthickness of 13 microns, a breakdown voltage of 400 volts wasobserved25. This was far below the capability of the material andcompares poorly with 1720 volts observed for the planar nickel Schottkyrectifier. The analysis discussed in the previous section indicates that thisbreakdown problem is not endemic to the TSBS structure but may berelated to the chip design and layout. However, a reduction of theleakage current by a factor of 75 x was observed confirming the ability ofthe TSBS concept in mitigating the barrier lowering and tunnelingcurrents from the main Schottky contact. In addition, the on-statecharacteristics were found to be similar to those for a planar titaniumSchottky contact as expected from the description of the simulatedstructures in the previous section. More recently25, a reduction of leakage current by a factor of 30xhas also been reported by using the planar TSBS structure (i.e. zerotrench depth) with little impact on the forward characteristics. Thesmaller improvement in the leakage current when compared with thetrench structure is consistent with less effective potential barrierobserved in the simulation results described in the previous section. Thebreakdown voltages of these diodes ware far below the capability of theunderlying drift region due to absence of adequate edge termination.6.4 SummaryA significant improvement in the leakage current of silicon carbideSchottky rectifiers can be achieved by shielding the Schottky contactagainst high electric fields generated in the semiconductor. The JBS andTSBS structures are found to be very effective in reducing leakagecurrent without significant degradation of the forward characteristics. Incontrast, the TMBS concept, although very effective for improvement ofsilicon Schottky rectifiers, is inappropriate for silicon carbide due to thegeneration of high electric fields in the oxide.
  • 161. Shielded Schottky Rectifiers 139References B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.2 B.J. Baliga, "The Pinch Rectifier: A Low Forward Drop High SpeedPower Diode", IEEE Electron Device Letters, Vol. 5, pp. 194-196, 1984.3 B. J. Baliga, "Pinch Rectifier", U. S. Patent 4,641,174, IssuedFebruary 3, 1987.4 M. Mehrotra and B. J. Baliga, "Very Low Forward Drop JBSRectifiers Fabricated using Sub-micron Technology", IEEE Transactionson Electron Devices, Vol. 41, pp. 1655-1660, 1994.5 M. Mehrotra and B. J. Baliga, "Schottky Barrier Rectifier with MOSTrench", U. S. Patent 5,365,102, Issued November 15, 1994.6 B.J. Baliga, "Schottky Barrier Rectifiers and Methods of Forming theSame", U.S. Patent 5,612,567, March 18, 1997.7 S. Mahalingam and B.J. Baliga, "The Graded Doped Trench MOSBarrier Schottky Rectifiers", Solid State Electronics, Vol. 43, pp. 1-9,1999.8 B.J. Baliga, "The Future of Power Semiconductor Technology",Proceedings of the IEEE, Vol. 89, pp. 822-832, 2001.9 L. Tu and B. J. Baliga, "Schottky Barrier Rectifier including SchottkyBarrier regions of Differing Barrier Heights", U. S. Patent 5,262,668,November 16, 1993.10 B. J. Baliga, "Analysis of Junction Barrier controlled SchottkyRectifier Characteristics", Solid State Electronics, Vol. 28, pp. 1089-1093,1985." R. Held, N. Kaminski and E. Niemann, "SiC Merged p-n/SchottkyRectifiers for High Voltage Applications", Silicon Carbide and RelatedMaterials - 1997, Material Science Forum, Vol. 264-268, pp. 1057-1060,1998.12 F. Dahlquist, et al, "Junction barrier Schottky Diodes in 4H-SiC and6H-SiC", Silicon Carbide and Related Materials - 1997, MaterialScience Forum, Vol. 264-268, pp. 1061-1064, 1998.13 B. J. Baliga, "Analysis of a High Voltage Merged PiN/Schottky(MPS) Rectifier", IEEE Electron Device Letters, Vol. 8, pp. 407-409,1987.14 F. Dahlquist, et al, "A 2.8kV JBS Diode with Low Leakage", SiliconCarbide and Related Materials - 1999, Material Science Forum, Vol.338-342, pp. 1179-1182, 2000.
  • 162. 140 SILICON CARBIDE POWER DEVICES15 D. Peters, et al, "Comparison of 4H-SiC pn, Pinch, and SchottkyDiodes for the 3kV Range", Silicon Carbide and Related Materials -2001, Material Science Forum, Vol. 389-393, pp. 1125-1128, 2002.16 F. Dahlquist, H. Lendenmann and M. Ostling, "A JBS Diode withcontrolled Forward Temperature Coefficient and Surge CurrentCapability", Silicon Carbide and Related Materials - 2001, MaterialScience Forum, Vol. 389-393, pp. 1129-1132, 2002.17 J. Wu, et al, "4,308V, 20.9 mO-cm2 4H-SiC MPS Diodes Based on a30 micron Drift Layer", Silicon Carbide and Related Materials - 2003,Material Science Forum, Vol. 457-460, pp. 1109-1112, 2004.18 M. Mehrotra and B. J. Baliga, The Trench MOS Barrier SchottkyRectifier", IEEE International Electron Devices Meeting, Abstract28.2.1, pp. 675-678, 1993.19 S. Mahalingam and B. J. Baliga, "A Low Forward Drop High VoltageTrench MOS Barrier Schottky Rectifier with Linearly Graded DopingProfile", IEEE International Symposium on Power SemiconductorDevices and ICs, Paper 10.1, pp. 187-190, 1998.20 V. Khemka, V. Ananthan, and T. P. Chow, "A 4H-SiC Trench MOSBarrier Schottky (TMBS) Rectifier", IEEE International Symposium onPower Semiconductor Devices and ICs, pp. 165-168, 1999.21 Q. Zhang, M. Madangarli, and T. S. Sudarshan, "SiC Planar MOS-Schottky Diode", Solid State Electronics, Vol. 45, pp. 1085-1089, 2001.22 B. J. Baliga, "High Voltage Silicon Carbide Devices", MaterialResearch Society Symposium, Vol. 512, pp. 77-88, 1998.23 M. Praveen, S. Mahalingam, and B. J. Baliga, "Silicon Carbide DualMetal Schottky Rectifiers", PSRC Technical Working Group Meeting,Report TW-97-002-C, 199724 K. J. Schoen, et al, "A Dual Metal Trench Schottky Pinch-Rectifier in4H-SiC", IEEE Electron Device Letters, Vol. 19, pp. 97-99, 1998.25 F. Roccaforte, et al, "Silicon Carbide Pinch Rectifiers using a Dual-Metal Ti-NiSi Schottky Barrier", IEEE Transactions on ElectronDevices, Vol. 50, pp. 1741-1747, 2003.
  • 163. Chapter 7 Metal-Semiconductor Field Effect TransistorsAs already pointed out in earlier chapters, the main advantage of wideband gap semiconductors for power device applications is the very lowresistance of the drift region even when it is designed to support largevoltages. This favors the development of high voltage unipolar deviceswhich have much superior switching speed than bipolar structures. TheJunction Field Effect Transistor (JFET) and the Metal SemiconductorField Effect Transistor (MESFET) are potential candidates as unipolarswitches for power applications. These structures have also been calledStatic Induction Transistors1. In the case of silicon, the maximumbreakdown voltage of JFETs has been limited by the increase in theresistance of the drift region2. This limitation does not apply to siliconcarbide due to the much larger doping concentration within the driftregion for high voltage structures. However, as in the case of siliconstructures, the normally-on behavior of the high voltage JFETs has beenfound to be a serious impediment to circuit applications. When poweringup any electronic system, it is impossible to ensure that the gate voltagerequired to block current flow in the JFET is provided to the structureprior to the incidence of the drain voltage on the structure. This situationcan result in shoot-through currents between the power rails resulting indestructive failure of the devices. This has discouraged the use ofnormally-on devices in power electronic applications. The normally-on behavior of silicon JFETs motivated thedevelopment of MOS-gated bipolar structures leading to the evolution ofthe Insulated Gate Bipolar Transistor (IGBT)3. Consequently, after avigorous period of development in the 1980s, interest in silicon powerJFETs declined. Problems encountered with quality of the oxide-semiconductor interface in silicon carbide brought renewed interest inJFETs for power switching applications. In addition, the invention of the 141
  • 164. 142 SILICON CARBIDE POWER DEVICESBaliga Pair circuit configuration4 enabled achieving a normally-offpower switch function with a high speed integral diode that is ideallysuitable for H-bridge applications. The Baliga-Pair utilizes a high voltagenormally-on silicon carbide JFET or MESFET in a cascodeconfiguration5 with a low voltage silicon power MOSFET to achieve anormally-off function. Since this approach provides many advantages asdiscussed in the next chapter, it was an important conceptual break-through that has motivated the development of silicon carbide highvoltage JFET/MESFET structures. This chapter reviews the basic principles of operation of theJunction (or Metal-Semiconductor) Field Effect Transistor. Thesestructures must be designed to deplete the channel region by applicationof a reverse bias voltage to the gate-source junction. To prevent currentflow through the device, a potential barrier for electron transport must becreated in the channel to suppress electron transport even under largedrain bias voltages. Concurrently, the channel must remain un-depleted(preferably at zero gate bias) to allow on-state current flow with low on-state resistance. Unique issues that relate to the wide band gap of siliconcarbide must be given special consideration. The results of the analysisof these structures by using two-dimensional numerical simulations aredescribed in this chapter. Experimental results on relevant structures areprovided to define the state of the development effort on high voltagesilicon carbide JFETs and MESFETs. The operating principles for the Baliga-Pair configuration thatprovide the desired normally-off function are discussed in the nextchapter. The results of two-dimensional numerical simulations of aconcatenated MOSFET and MESFET structure are described to provideinsight into the operation of this concept. The results of experimentalwork on the Baliga-Pair are summarized validating the utility of this ideafor high power system applications.7.1 Trench Junction (Metal-Semiconductor) Field Effect TransistorStructureThe basic structure of the vertical trench Junction Field Effect Transistor(JFET) and the trench Metal-Semiconductor Field Effect Transistor(MESFET) are shown in Fig. 7.1. The structures contain a drift region(usually N-type) between the drain and the source regions designed tosupport the desired maximum operating voltage. As discussed in detail
  • 165. Metal-Semiconductor Field Effect Transistors 143later in the chapter, the drift region must be capable of supporting thesum of the drain bias and the reverse gate bias potentials withoutundergoing breakdown. To prevent current flow under forward blockingconditions, a gate region must be incorporated in the drift region. A P-Njunction gate region is used for the JFET structure and a Schottky (metal-semiconductor) contact is used for the MESFET structure. In order toproduce a strong potential barrier for suppressing the transport ofelectrons between the drain and the source, it is preferable to create agate with vertical sidewalls. For the JFET structure, this can be achievedby utilizing multiple P-type ion implants with increasing energy using acommon mask edge. For the MESFET structure, a trench is etched withvertical sidewalls followed by the selective deposition of the Schottkybarrier gate metal to fill the trench. MESFET JFET SOURCE GATE SOURCE GATE ±n % mm . p+ N-DR1FT REGION N-DRIFT REGION N+ SUBSTRATE N+ SUBSTRATE V/////////////A Y////////////M DRAIN DRAIN Fig. 7.1 The Vertical Trench JFET and MESFET Structures. When a negative bias is applied to the gate electrode, a depletionlayer extends from the gate into the drift region. With sufficient gatebias, the entire space between the gate regions becomes depleted. Thegate bias required to deplete the space between the gate regions isreferred to as the pinch-off voltage. At a gate bias above the pinch-offvoltage, a potential barrier forms under the source region at location A.This barrier suppresses the transport of electrons between the drain andthe source. However, the potential barrier is reduced with application of
  • 166. 144 SILICON CARBIDE POWER DEVICESthe drain bias. Consequently, as the drain bias increases, drain currentflow commences at voltages well below the breakdown voltagecapability of the drift region. Since a larger potential barrier is created forlarger gate bias voltages, it is possible to support a larger drain biasvoltage before the observation of drain current flow. The spacing between the gate regions is usually designed to bemore than twice the zero bias depletion width. Consequently, an un-depleted portion of the drift region remains under the source region atzero gate bias. Current flow between the drain and source occurs throughthis region with the amount limited by the resistance of the channelregion (between the gates) and the drift region below the gate. A largeun-depleted region is favored for reducing the on-resistance but thisreduces the magnitude of the potential barrier when the device operatesin the forward blocking mode. Thus, a trade-off between the on-stateresistance and blocking characteristics must be made when designingthese structures.7.1.1 Trench Metal-Semiconductor Field Effect TransistorStructure: Forward BlockingSince the operating principles for the MESFET and JFET structures aresimilar, these names will be used interchangeably in this chapter. In anormally-on device structure, an un-depleted portion of the channelexists at zero gate bias. Drain current flow can therefore occur via thisun-depleted region at zero gate bias. The forward blocking capability inthe MESFET structure is achieved by creating a potential barrier in thechannel between the gate regions by applying a reverse bias to the gateregion. At a gate bias above the pinch-off voltage, the channel becomescompletely depleted. As the gate bias is increased above the pinch-offvoltage, the potential barrier increases in magnitude. This will be shownlater in the chapter with the aid of two-dimensional numerical analysis oftypical structures. Current transport between the drain and source issuppressed because electrons must overcome the potential barrier. As thedrain voltage is increased, the potential barrier reduces allowing injectionof electrons over it. An exponential increase in the drain current isobserved with increasing drain bias with triode-like characteristics.This behavior can be described by6: J r D ~ H^^-^A- _qDnND jf{aVG-/3VD) [7.1]
  • 167. Metal-Semiconductor Field Effect Transistors 145where a and (3 are constants that depend upon the gate geometry. In thisequation, D„ is the diffusion coefficient for electrons, ND is the dopingconcentration in the drift region, L is the gate length (in the direction ofcurrent flow), q is the charge of the electron, k is Boltzmanns constant,T is the absolute temperature, VG is the gate bias voltage and VD is thedrain bias voltage. The exponential variation of drain current withvariation of gate and drain bias has been observed in silicon verticalchannel JFETs7. On the one hand, if the space between the gate regions in theJFET structure is reduced so that it becomes completely depleted by thezero bias depletion width, the structure can exhibit a normally-offbehavior upto a limited drain voltage. This type of design will exhibitpurely triode-like characteristics. On the other hand, if the space betweenthe gate regions is larger than the maximum depletion width atbreakdown for the drift region, the structure will exhibit purely pentode-like characteristics. If the space between the gate regions falls betweenthese extremes, the device will exhibit a mixed triode-pentode likecharacteristics. High voltage normally-on JFETs are usually designed tooperate in this mixed triode-pentode mode to obtain a good compromisebetween low on-state resistance and high blocking voltage capability. l l [ o.i " — " — " 10" 10 1 4 1015 1016 Drift Region Doping Concentration (cm"3) Fig. 7.2 Design Space for High Voltage Silicon JFETs.
  • 168. 146 SILICON CARBIDE POWER DEVICES The design space for vertical high voltage JFETs is bounded bythe depletion widths at breakdown and the zero-bias depletion width.These boundaries are shown in Fig. 7.2 for the case of silicon devices,and in Fig. 7.3 for the case of 4H-SiC devices. For any given dopingconcentration, a much larger spacing is required for 4H-SiC devices dueto the bigger depletion width at breakdown. In general, a greater latitudeexists for the design of 4H-SiC devices to optimize the characteristics. 1000 4H-SiC Purely Pentode-like Oe*. Characteristics 100 Mixed Pe ntode- "/>/B "o,. tJ"0 % Triode I Characteristics ***»+« iff 3«7 I 10 _ I Purely ^a a* OePte« c "**Hh = Triode-like Characteristic s 0.1 10" 10 14 10" 10" Drift Region Doping Concentration (cm3) Fig. 7.3 Design Space for High Voltage 4H-SiC JFETs. A good compromise between achieving a low on-state resistanceand a good blocking voltage capability for high voltage JFETs requiresdesigning the channel to operate in the mixed pentode-triode regime. Atlow drain current levels and high drain voltages, these devices exhibittriode-like characteristics. In this mode, it is useful to define a DCblocking gain (GDC) as the ratio of the drain voltage to the gate voltage ata specified leakage current level. A differential blocking gain (GAc) canalso be defined as the increase in drain voltage, at a specified leakagecurrent level, for an increase in the gate voltage by 1 volt. From Eq.[7.1], it can be shown that: r -dv» a [7.2] AC dVG J3
  • 169. Metal-Semiconductor Field Effect Transistors 147The parameters a and P are dependent upon the channel aspect ratio. Thechannel aspect ratio is defined as the ratio of the length of the gate(dimension L in Fig. 7.4) in the direction of current flow and the spacebetween the gate regions (dimension a in Fig. 7.4). A large aspect ratiofavors obtaining a high blocking gain, which is beneficial for reducingthe gate voltage required to block high drain voltages. Theoreticalanalysis8 and empirical observations9 on high voltage silicon JFETsindicate that the blocking gain can be described by: V r B- [7.3] ajwhere A and B are constants. In silicon JFETs, a blocking gain of about10 is obtained for a vertically walled structure when the channel aspectratio is approximately equal to unity. Since the gate junction mustsupport the sum of the negative gate bias voltage and the applied positivedrain voltage, the drift region parameters must be chosen to account forthe finite blocking gain. b SOURCE GATE ////A1 W/// "n;" p+ a N-DRIFT REGION N+ SUBSTRATE W//////////M DRAIN Fig. 7.4 Channel Aspect Ratio (17a) for JFET structures. The largest drain voltage that can be supported by the JFETstructure before the on-set of significant current flow is determined byseveral factors. Firstly, it is limited by the intrinsic breakdown voltagecapability of the drift region as determined by the doping concentration
  • 170. 148 SILICON CARBIDE POWER DEVICESand thickness. The breakdown voltage can be obtained by using thegraphs and equations provided in chapter 3. Secondly, the maximumdrain voltage that can be supported without significant current flow canbe limited by the applied gate bias and the blocking gain of the structure.In addition, the largest gate bias that can be applied is limited by the on-set of breakdown between the gate and the source regions. Thebreakdown voltage between the gate and the source regions isdetermined by the depletion layer punch-through from the gate junctionto the highly doped N+ source region. Since the space between theseregions must be kept small in order to obtain a high channel aspect ratioleading to high blocking gain, the electric field between the gate andsource regions can be assumed to be uniform. Under this approximation,the gate-source breakdown voltage can be calculated using: BVGS=b.Ec [7.4]where b is the space between the gate and the source as shown in Fig.7.4 and E c is the critical electric field for breakdown. Fortunately, thecritical electric field for breakdown in silicon carbide is much larger thanfor silicon, allowing high gate-source breakdown voltages in spite ofusing small gate-source spacing.7.1.2 Trench Junction Field Effect Transistor Structure: On-State GATE SOURCE V/////A V7777m DEPL ETION ;6UHR6NTPATH; I I I I I I I I I I i I I I I I I I I I I I WSUBSTKATE; y////////////////m?m CATHODE Fig. 7.5 Current Flow in On-State for JFET structures.
  • 171. Metal-Semiconductor Field Effect Transistors 149 For the normally-on JFET design with mixed Pentode-Triodemode of operation, the on-state current flow pattern is as indicated in Fig.7.5 by the dotted lines. The current flows from the source through auniform cross section between the gate regions with a width (d)determined by the space between the gate regions and the zero-biasdepletion width. The current then spreads at a 45 degree angle into thedrift region to a depth of s under the gate region, and then becomesuniform throughout the cross-section. This current flow pattern can beused to model the on-state resistance: P(S + W O)J In P^ p-2d 2d) [7.5] + pD{t-s)where W0 is the zero bias depletion width. The specific on-resistance of the JFET can be much larger thanthe ideal specific on-resistance for any particular blocking voltagecapability of the JFET structure. Firstly, this is because the drift regionmust support the sum of the gate and drain bias voltages. Secondly, it isincreased by the contributions from the channel region and the spreadingresistance. These contributions become more significant as the spacebetween the gates is reduced. Thus, a compromise must be madebetween obtaining a low specific on-state resistance and a high blockinggain. When a negative gate voltage is applied to reverse bias the gatejunction, the depletion region extends further into the channel producingan increase in the on-resistance. Further, if the drain voltage becomescomparable to the gate bias voltage, the depletion width at the bottom ofthe channel on the drain side becomes larger (as determined by VGs plusVDS). This alters the current flow pattern as illustrated in Fig. 7.6. Underthe assumption of a field independent mobility and by using the gradualchannel approximation, the drain current is determined by :ID =2apD—- v Y Dch 0 ^Tl(vDch+vG+vblr-(vG+vj12} .4ND) 3a [7.6]where Z is the length of the device in the direction orthogonal to thecross-section, and Vi^h is the drain voltage at the bottom edge of thechannel.
  • 172. 150 SILICON CARBIDE POWER DEVICES The basic I-V characteristics determined by this equation can bedescribed using three segments. In the first segment, the drain voltage ismuch smaller than the gate bias voltage. In this case, the channelresistance increases with reverse gate voltage as given by: (V +V R " " ^ 2 Z "-jlk * » [7.7] GATE SOURCE V/////////////////////A CATHODE Fig. 7.6 Current Flow at larger VDS for JFET structures. In the second segment, the drain voltage is comparable to thegate voltage. This produces a non-linear characteristic with the resistanceincreasing with increasing drain bias. Eventually, the entire spacebetween the gate regions becomes depleted at a certain drain bias. Thiscondition is described by: quDa2 vP=(vt +v T v + v j = 2e< [7.8] Dch GSwith VP defined as the pinch-off voltage. The drain voltage, at whichchannel pinch-off occurs, decreases linearly with increasing gate voltage. In the third segment, the drain current becomes constant becausethe channel is completely pinched off. The saturated drain current isgiven by:
  • 173. Metal-Semiconductor Field Effect Transistors 151 L |^ 6es 3a{qNDJ [7.9]A family of drain current-voltage curves is formed with the saturateddrain current decreasing with increasing gate voltage. Although theseequations predict a constant drain current beyond the channel pinch-offpoint, in practice, the drain current can increase after pinch-off due toelectron injection over the potential barrier formed at the bottom of thechannel. This phenomenon leads to the mixed Pentode-Triodecharacteristics.7.2 Trench Metal-Semiconductor Field Effect Transistor Structure:Simulation ResultsThe case of a vertical MESFET structure with drift region concentrationof 1 x 1016 cm3 and thickness of 20 microns will be used to illustrate theoperating principles of these devices. The two dimensional numericalsimulations were performed with various spacing between the gateregions as well as by varying the depth of the gate region (trench depth).In each case, the on-state resistance was extracted at zero gate bias, andthe blocking characteristics were obtained by application of variousnegative gate bias voltages. A gate metal work-function of 5.2 eV wasused corresponding to a barrier height of 1.5 eV.7.2.1 Trench MESFET Structure: On-State CharacteristicsFirst, consider the case of a MESFET with gate spacing (dimension a inFig. 7.4) of 0.6 microns with a space b of 0.35 microns between the N+source region and the gate metal. The width of the trench (dimension Vin Fig. 7.5) was kept constant for all structures at a value of 0.5 microns.The impact of changing the trench depth was studied by using values of0.5, 1.0, and 1.5 microns. The on-state current flow pattern for thestructures at zero gate bias is shown in Fig. 7.7. It can be seen that thecurrent flow is uniform in the channel region within a width determinedby the un-depleted portion. The current then spreads rapidly (at an angleof 45 degrees) and then becomes uniform for most of the drift region. The specific on-resistance for the device with 1 micron trenchdepth was found to be 1.83 mQ-cm2. This is extremely small for a
  • 174. 152 SILICON CARBIDE POWER DEVICESstructure capable of supporting nearly 3000 volts. The ideal specific on-resistance for the drift region is 1.0 m£2-cm2 as previously discussed inchapter 3 (see Fig. 3.6). Thus, the MESFET structure provides a specificon-resistance approaching the ideal value. The specific on-resistance wasfound to have a weak dependence on the trench depth. It reduced to 1.62mQ-cm2 for a trench depth of 0.5 microns and increased to 2.04 m£2-cm2for a trench depth of 1.6 microns. Consequently, the blocking gain can beincreased by increasing the trench depth without a strong adverse impacton the on-resistance. Trench Depth = 1.0 microns 0.2 0.4 0.6 0.8 Distance (microns) Trench Depth = 1.6 microns (1.2 0.4 0.6 0.8 Distance (microns) Fig. 7.7 On-State Current Flow in 4H-SiC MESFETs: Impact of Trench Depth. The blocking gain of MESFETs can be increased by reducing thespacing between the gate regions. The impact of this space reduction on
  • 175. Metal-Semiconductor Field Effect Transistors 153the on-resistance was studied while keeping the trench depth at 1 micron.It was found that the specific on-resistance reduced from 1.83 m£2-cm2 ata spacing (dimension a) of 0.6 microns to 1.66 mQ-cm2 at a spacing of0.8 microns. This is due to the larger conduction area in the channelregion with increasing gate spacing as shown in Fig. 7.8. However, whenthe spacing was further increased tol micron, the specific on-resistanceincreased slightly to 1.68 m£J-cm2. This occurs because the improvementdue to reduction in absolute cell on-resistance is counteracted by theenlargement of the cell pitch. Consequently, it is advantageous to keepthe gate spacing below 0.8 microns to obtain both a low specific on-resistance and a high blocking gain. The blocking gain for thesestructures is discussed in the next section. Gate Spacing = 0.6 microns 0.2 11.4 0.6 0.8 Distance (microns) Gate Spacing = 0.8 microns 0.4 0.6 0.8 Distance (microns) Fig. 7.8 On-State Current Flow in 4H-SiC MESFETs: Impact of Gate Spacing.
  • 176. 154 SILICON CARBIDE POWER DEVICES7.2.2 Trench MESFET Structure: Blocking CharacteristicsIn a normally-on MESFET structure, the ability to block current flowwith positive drain voltage can be achieved by application of a negativegate bias. The gate bias depletes the space between the gate regions andproduces a potential barrier to the flow of electrons from the source tothe drain. The minimum voltage required to deplete the space betweenthe gate regions is the pinch-off voltage which reduces with smaller gatespacing. For a given gate bias voltage, a larger potential barrier can beformed with smaller gate spacing and a larger channel aspect ratio asdiscussed earlier. These features are discussed with the aid of resultsfrom two-dimensional numerical simulations in this section. Trench Depth = 1 micron Gate Spacing = 0.6 microns Increasing VGS in steps of - 4 volts -30 1 2 3 Distance (microns) Fig. 7.9 Channel Potential Barrier in a 3 kV 4H-SiC MESFET. In the MESFET structure, electron injection can occur over theportion of the channel with the smallest potential barrier leading to theon-set of current flow. The smallest potential barrier occurs at a locationin the channel furthest removed from the edge of the gate region. For this
  • 177. Metal-Semiconductor Field Effect Transistors 155reason, the potential variation between the drain and source at the centerof the channel region (i.e. at x = 0 in Fig. 7.4 and Fig. 7.7) is shown inFig. 7.9. The pinch-off voltage for a structure with a gate spacing of 0.6microns is 3.35 volts for the drift region doping concentration of 1 x 1016cm3. Consequently, it can be seen that a negative potential develops inthe channel after the gate bias exceeds -4 volts. The magnitude of thepotential barrier increases with gate bias and reaches a value of -26 voltsat a gate bias of -40 volts. A linear increase in the potential barrier isobserved with increasing gate bias as shown in Fig. 7.10. k 1-6 30 I 3kV<IH-SiC;MES FET • 1.0 ! 20 I 10 Jl III 0.5 -a o 0 10 20 30 40 Reverse Gate Bias (Volts) Fig. 7.10 Channel Potential Barriers in 3 kV 4H-SiC MESFETs. The development of the channel potential barrier for the case ofincreasing the trench depth from 1 to 1.6 microns is shown in Fig. 7.11.The potential barrier becomes larger with a value of -32 volts at a gatebias of -40 volts. In addition, the barrier becomes broader between thedrain and the source creating additional difficulty for injection ofelectrons and thus suppressing drain current flow. The increase in thebarrier height as a function of gate bias for this case is also shown in Fig.7.10. In addition, the barrier height for the case of a trench depth of 0.5microns is shown in this figure for comparison. With the reduced trenchdepth a much smaller potential barrier develops in the channel. This
  • 178. 156 SILICON CARBIDE POWER DEVICESreduces the blocking gain and consequently the ability of the device tosupport high drain voltages. Trench Depth = 1.6 micron Gate Spacing = 0.6 microns Increasing VQg in steps of - 4 volts Vr.s = - 4 0 V -35 -40 1 2 3 Distance (microns) Fig. 7.11 Channel Potential Barrier in a 3 kV 4H-SiC MESFET. 30 J2 > 0.6 > 3kV 4H-S1C MESFET I 3 20 L 0.8 1 10 o - 10 Gate Spacing i dun) ••— 10 20 30 40 Reverse Gate Bias (Volts) Fig. 7.12 Channel Potential Barriers in 3 kV 4H-SiC MESFETs.
  • 179. Metal-Semiconductor Field Effect Transistors 157 The height of the potential barrier is also dependent upon thegate spacing. A smaller gate spacing not only reduces the pinch-offvoltage but also increases the potential barrier height resulting is largerblocking gain. The change in the potential barrier height as a function ofthe reverse gate bias is shown in Fig. 7.12 when the trench depth ismaintained at 1 micron. Note that the potential barrier begins to developat larger gate bias voltages with increased gate spacing because of thelarger pinch-off voltage, namely, 9.3 volts for the 1 micron gate spacingversus 3.3 volts for the 0.6 micron gate spacing. The potential barrierheight for the 1 micron gate spacing is about half that observed with thegate spacing of 0.6 microns. It is therefore important to obtain precisecontrol over the geometry of the MESFET structure during fabrication.The variation of the potential barrier for the structure with 1 micron gatespacing is provided in Fig. 7.13 for comparison with the simulationresults shown in Fig. 7.9 for the structure with spacing of 0.6 microns. Trench Depth = 1 micron Gate Spacing = 1 micron Increasing Vos in steps of - 4 volts -20 1 2 3 Distance (microns) Fig. 7.13 Channel Potential Barrier in a 3 kV 4H-SiC MESFET. The blocking characteristics of the MESFET structure aredetermined by the triode-like behavior at low drain bias voltages. In thisdomain of operation, current flow occurs when the electrons overcome
  • 180. 158 SILICON CARBIDE POWER DEVICESthe potential barrier created by the gate bias. As the drain voltageincreases, the potential barrier is reduced promoting the injection ofelectrons. This produces triode-like characteristics with an exponentialincrease in drain current with increasing drain bias as described by Eq.[7.1]. The change in the potential barrier height with increasing drainbias is shown in Fig. 7.14 for the case of the structure with 1 microntrench depth and 0.6 micron gate spacing when a gate bias of -40 volts isapplied. It can be seen that the potential barrier becomes smaller withincreasing drain voltage. A -3 volt barrier is still preserved even at adrain bias of 3000 volts indicating that this structure can support 3000volts with low drain leakage current flow. Note that the peak of thepotential barrier moves towards the source with increasing drain biasindicating encroachment of the drain potential into the channel. Trench Depth = 1 micron Gate Spacing = 0.6 microns 1 2 3 Distance (microns) Fig. 7.14 Channel Potential barrier in a 3 kV 4H-SiC MESFET. (VDS = 0,10,50,100,500,1000,1500,2000,2500,3000 volts) The reduction of the potential barrier height with increasingdrain voltage is shown in Fig. 7.15 for the case of devices with differenttrench depths. It can be seen that the barrier height reduces to a greater
  • 181. Metal-Semiconductor Field Effect Transistors 159extent for the shallower trench depth. For the case of a trench depth of0.5 microns, the potential barrier is completely removed with a drain biasof above 500 volts. Thus, this structure cannot support high drainvoltages with a gate bias of -40 volts. 2 | 30 3kV 4H-SiC MESFET Trench Depth = 1.6 an E 2 20 s i V 1 > 10 L Trench Depth = 1.0 urn ¥ U V, Trench Depth = 0.5 (im S 1000 2000 3000 Drain Bias (Volts) Fig. 7.15 Channel Potential Barriers in 3 kV 4H-SiC MESFETs. In general, the normally-on MESFET structure can support alarger drain bias voltage without significant drain current flow if the gatevoltage is increased. However, the reverse gate bias cannot be arbitrarilyincreased because of the on-set of gate-source breakdown. Thebreakdown voltage between the gate and source regions is decided by thedepletion layer punch-through process. Under strong punch-throughconditions, the electric field can be calculated using the approximationthat it is uniform between the gate and the source regions: [7.10] GS ~ bwhere b is the space between the gate and the source as shown in Fig.7.4 and Vbi is the built-in potential for the gate region. The maximumgate voltage that can be applied (BVGs) is then given by the conditionwhere the electric field becomes equal to the critical electric field forbreakdown:
  • 182. 160 SILICON CARBIDE POWER DEVICES BV, = b.Ec-Vbi GS [7.11]For a spacing b of 0.35 microns, the gate-source breakdown voltage for4H-SiC is about 100 volts if a critical electric field of 3 x 106 V/cm isused. Thus, the MESFET structures with shallower trenches could blockdrain voltages above 500 volts with the application of larger gate biasvoltages. However, this is not desirable from an application stand pointwhere lower input voltages are preferred. Trench Depth = 1 micron Gate Spacing = 0.6 microns 0.2 0.4 0.6 0.8 Distance (microns) Fig. 7.16 Electric Field between Gate and Source in a 3 kV 4H-SiC MESFET. The build-up of the electric field between the gate and source isshown in Fig. 7.16 for a typical simulated structure with gate-sourcespacing b of 0.35 microns. As anticipated, the electric field isapproximately uniform between the regions. The electric field calculatedusing Eq. [7.10] with a built-in potential of 1 volt and a spacing of 0.35microns is also shown by the dashed lines in the figure. A goodagreement is observed between the simple analytical method ofcalculation of the electric field and the simulated results.
  • 183. Metal-Semiconductor Field Effect Transistors 161 When the gate bias is changed, the on-set of drain current up toany given leakage current level occurs at different drain bias voltages.This produces the triode-like characteristics between the drain currentand voltage. A typical set of I-V characteristics is shown in Fig. 7.17 forthe case of the structure with 1 micron trench depth and 0.6 micron gatespacing. Note that the drain current increases exponentially withincreasing drain bias consistent with the electron potential barrier modeldiscussed in the previous sections until the drain current exceeds 106 Acorresponding to a current density of 100 A/cm2. Trench Depth = 1 micron Gate Spacing = 0.6 microns Drain Bias (kV) Fig. 7.17 Blocking Characteristics for a 3 kV 4H-SiC MESFET. (VGS = 0,-2,-4,-6,..,-26 volts) By choosing a suitable magnitude for the drain leakage currentunder forward blocking conditions, it is possible to track the drainvoltage supported at each gate bias. The resulting drain blocking voltageis plotted in Fig. 7.18 as a function of the magnitude of the reverse gatebias. From this graph, the benefits of increasing the trench depth toenhance the channel aspect ratio become quite obvious. Similarly, theadverse impact of increasing the gate spacing to reduce the channel
  • 184. 162 SILICON CARBIDE POWER DEVICESaspect ratio is shown in Fig. 7.19 for the case of a trench depth of 1micron. 1 1 1 1 1 1 Trench Depth = 1.6 |im Trench Depth = 1.0 |im f 3000 > | 2000 > i 3kV 4H-SiC MESFET 2 u 3 IOOO 1 f Trench Depth = 0.5 nm J i • m- 10 20 30 Reverse Gate Bias (Volts) 40 Fig. 7.18 Drain Blocking Voltage for 3 kV 4H-SiC MESFETs. 3000 •© > as £ £ "3 2000 > B u o 1000 s a °8 u O 0 k 20 30 40 Reverse Gate Bias (Volts) Fig. 7.19 Drain Blocking Voltage for 3 kV 4H-SiC MESFETs.
  • 185. Metal-Semiconductor Field Effect Transistors 163 In general, the voltage blocking behavior of the verticalMESFET structure can be examined by looking at the blocking gain as afunction of the channel aspect ratio. The DC blocking gain is defined asthe ratio of the drain blocking voltage to the corresponding gate bias.This gain varies with drain and gate bias as observed in the abovefigures. If the gain is taken at a drain bias of 500 volts, then the variousstructures can be compared in terms of the channel aspect ratio. This isdone in Fig. 7.20 for the structures simulated with various trench depthsand gate spacing. The exponential increase in blocking gain withincreasing channel aspect ratio is observed when either the trench depthor the gate spacing is changed. However, the trend lines are not identicaldue to the difference in the width of the potential barrier. 3kV 4H-SJC MESFET Trench Depth / Gate Spacing 0 1.0 2.0 3.0 Channel Aspect Ratio Fig. 7.20 Blocking Gain for 3 kV 4H-SiC MESFETs.7.2.3 Trench MESFET Structure: Output CharacteristicsThe output characteristics of the vertical MESFET structure determinethe safe operating area of the device. In a typical pulse width modulatedcontrol scheme, the power transistor undergoes a switching transientfrom either the on-state to off-state or vice versa. The loci for thesetransients must be kept within the bounds of the safe operating area forthe transistor.
  • 186. 164 SILICON CARBIDE POWER DEVICES Trench Depth = 1 micron Gate Spacing = 0.6 microns Drain Bias (kV) Fie. 7.21 Outout Characteristics for a 3 kV 4H-SiC MESFET. Trench Depth = 0.5 micron Gate Spacing = 0.6 microns Fig. 7.22 Output Characteristics for a 3 kV 4H-SiC MESFET.
  • 187. Metal-Semiconductor Field Effect Transistors 165 The channel design has a strong impact on the outputcharacteristics of the vertical MESFET structure. For the structure withtrench depth of 1 micron and gate spacing of 0.6 microns, the outputcharacteristics exhibit a mixed triode-pentode behavior as shown in Fig.7.21. This structure is capable of supporting a drain bias of 3000 voltswith a gate bias of -26 volts. On the other hand, the structure withreduced trench depth of 0.5 microns is unable to support a drain bias ofmore than 600 volts with a gate bias of -40 volts as shown by the outputcharacteristics in Fig. 7.22. A careful optimization of the structure isrequired to ensure that it can support the desired drain blocking voltagewith moderate (less than 40 volts) gate voltages. When this criterion issatisfied, the vertical MESFET structure can be utilized in the Baliga-Pair circuit configuration to create a very efficient normally-off powerswitch with high input impedance MOS interface. This is discussed indetail in the next chapter.7.3 Junction Field Effect Transistor Structure: Simulation ResultsAlthough the Junction Field Effect Transistor operates on the same basicprinciples as the Metal-Semiconductor Field Effect Transistor, the designof the two devices is slightly altered by the larger built-in potential forthe P-N junction when compared with the metal-semiconductor contact.The case of a vertical JFET structure with drift region concentration of 1x 1016 cm"3 and thickness of 20 microns will be used to illustrate thesedifferences. The two dimensional numerical simulations were performedwith gate spacing (dimension a in Fig. 7.4) of 0.6 microns with a space b of 0.35 microns between the N+ source region and the gate junction.The width of the P+ region (dimension s in Fig. 7.5) was kept at a valueof 0.5 microns. The on-state current flow pattern for the JFET structure at zerogate bias is compared in Fig. 7.23 with the MESFET structure having thesame gate spacing. Due to the larger built-in potential of the P-Njunction, a much stronger constriction of the current is observed for theJFET structure. This leads to an increase in the specific on-resistance.The specific on-resistance for the JFET structure was found to be 3.93mQ-cm2 when compared with 1.83 m&-cm2 for the MESFET structureand 1 mQ-cm2 for the ideal drift region alone. However, this value is stillrespectable for a device capable of supporting 3000 volts making theJFET structure an alternative option to the MESFET structure.
  • 188. 166 SILICON CARBIDE POWER DEVICES MKSFKT • 0.2 0.4 0.6 0.8 1.0 Distance (microns) 0 0.2 0.4 0.6 0.8 1.0 Distance (microns) Fig. 7.23 On-State Current Flow in a 4H-SiC JFET versus a MESFET. The blocking capability of the JFET structure is predicated uponformation of a potential barrier in the channel to suppress the injection ofelectrons from the source to the drain. The barrier height created by theapplication of various reverse gate bias voltages for the JFET structure isshown in Fig. 7.24. A slightly larger potential barrier is created in theJFET structure when compared with the MESFET structure for the samechannel design because of the larger built-in potential. This is moreobvious in the plot of the potential barrier as a function of gate biasprovided in Fig. 7.25. The barrier is about 1 volt larger for the JFETstructure at all gate bias voltages. The larger potential barrier in the channel for the JFET structurespromotes higher drain blocking voltage capability. This can be observedin the I-V characteristics for the device shown in Fig. 7.26. The structureis able to block drain current flow upto a drain bias of 3000 volts with agate bias of -26 volts. The improvement in the blocking gain is less than10 percent. Consequently, the MESFET structure is preferable to theJFET structure in order to obtain a lower specific on-resistance whilekeeping approximately the same blocking gain.
  • 189. Metal-Semiconductor Field Effect Transistors 167 Junction Depth = 1 micron Gate Spacing = 0.6 microns Increasing VQS in steps of - 4 volts -30 1 2 Distance (microns) Fig. 7.24 Channel Potential Barrier in a 3 kV 4H-SiC JFET. Mi 3kV 4H-SiCI 20 JFET1 10 MESFETU 0 10 20 30 40 Reverse Gate Bias (Volts) Fig. 7.25 Channel Potential Barrier in 3 kV 4H-SiC JFET and MESFET.
  • 190. 168 SILICON CARBIDE POWER DEVICES Junction Depth = 1 micron Gate Spacing = 0.6 microns 1 2 3 4 Drain Bias (kV) Fig. 7.26 Blocking Characteristics for a 3 kV 4H-SiC JFET. (VGS=0,-4,-8,..,-24 volts)7.4 Planar Metal-Semiconductor Field Effect Transistor StructureAn elegant high voltage silicon carbide MESFET structure that utilizes aplanar gate architecture (in place of the trench gate structure discussed inthe previous section) has also been proposed and demonstrated10. In thisdevice structure, a sub-surface heavily doped P-type region is placedbelow the N+ source region as illustrated in Fig. 7.27. The P+ region actsas a barrier to current flow between the source and drain regionsrestricting the current to gaps between the P+ regions. A gate region isplaced over these gaps and overlapping the P+ region to enable controlover the transport of current between the drain and source regions. Ingeneral, the gate can be constructed as a Metal-Semiconductor contact(to form a MESFET structure), a P-N Junction (to form a JFET structure)or as a Metal-Oxide-Semiconductor sandwich (to form a MOSFETstructure). The MESFET structure will be discussed in detail in thissection. The operation of the JFET structure is similar but requires taking
  • 191. Metal-Semiconductor Field Effect Transistors 169into account the larger built-in potential of the gate P-N junction. TheMOSFET structure is discussed in a subsequent chapter. SOURCE GATE T p+ N-DRIFT REGION N+ SUBSTRATE Y///////////////^^^^^ DRAIN Fig. 7.27 The Planar Gate MESFET Structure. The sub-surface P+ region in the planar gate MESFET structurecan be either connected to the gate or to the source region. If the P+region is electrically connected to the gate electrode, it collaborates withthe metal-semiconductor contact to constrict current flow from thesource to the drain region. However, when the gate is reverse biased, alow gate-source breakdown voltage can occur due to the close verticalproximity of the N+ source region and the sub-surface P+ region. It istherefore preferable to connect the P+ region to the source electrode.During the fabrication of the MESFET structure, this can be achieved byinterruption of the N+ region in the orthogonal direction to the cross-section shown in Fig. 7.27 and placing a P+ contact region from thesurface down to the sub-surface P+ region in these gaps. This approachavoids a potential breakdown problem between the N+ source and P+ sub-surface regions. However, the breakdown voltage between the gate andsource electrodes can now occur due to depletion region reach-throughfrom the gate contact to the underlying P+ region. Fortunately, as shownbelow with numerical simulations, relatively small reverse gate biasvoltages are required in the planar MESFET to achieve high drain
  • 192. 170 SILICON CARBIDE POWER DEVICESblocking voltages. The low gate-source breakdown voltage as a result ofreach-through is therefore not a serious limitation with proper design ofthe structure. The sub-surface P+ region in the planar MESFET structure canbe created by using ion-implantation of boron with the appropriateenergy10. Alternately, the sub-surface P+ region can be formed by growthof an N-type epitaxial layer over a P+ region formed in the drift region bylower energy ion-implantation11. In either case, the thickness of the re-type region between the gate and the sub-surface P+ region must besufficient to prevent complete depletion at zero gate bias. The dopingconcentration of the N-type region located between the gate and the sub-surface P+ region can be increased above that for the N-type drift regionif necessary by ion-implantation or during its epitaxial growth.7.4.1 Planar MESFET Structure: Forward BlockingAs previously described in this chapter, the forward blocking regime ofoperation for the MESFET structure is achieved by creating a potentialbarrier for transport of electrons between the source and drain region bythe application of a reverse gate bias. In the planar MESFET structure,this potential barrier is formed in the channel (at location C shown inFig. 7.27). If the thickness of the channel (shown as tcH in Fig. 7.28) isnarrow, a potential barrier can be formed with relatively low reverse gatebias voltages. In addition, the planar MESFET structure contains asecond JFET region formed between the adjacent P+ regions (at locationD shown in Fig. 7.27). When the drain bias exceeds the pinch-offvoltage for this JFET region, the potential at the surface under the gatebecomes isolated from the potential applied at the drain electrode.Consequently, the channel potential barrier is shielded from the drainvoltage enabling the support of high drain voltages without the on-set ofdrain current flow. These features favor producing a very high blockinggain with low reverse gate bias voltages as shown with two-dimensionalnumerical simulations later in this chapter.7.4.2 Planar MESFET Structure: On-State ResistanceThe planar MESFET can be designed to contain an un-depleted channelregion at zero gate bias. Current can then flow between the source anddrain regions through the channel and the gap between the P+ regions
  • 193. Metal-Semiconductor Field Effect Transistors 171down to the N-type drift region. The resistance of these regions must beincluded in the analysis of the total on-state resistance of the structure. a Lch W J SOURCE GATE t *™m ^ ^ ^ ^ ^ ^ j R__ V.,:,,,,,,,..,,,-. P+ mm aHBRW iH-DRlPTiftEGIQN:: :;wiii:syBCTHJCTE;sSxsss;iB£ DRAIN Fig. 7.28 Resistances in a Planar Gate MESFET Structures. The total specific on-resistance is given by: R R CH + RJFET + R D + R subs [7.12] on.spwhere RCH is the channel resistance, RJFET is the resistance of the JFETregion, RD is the resistance of the drift region after taking into accountcurrent spreading from the JFET region, and Rsubs is the resistance of theN+ substrate. These resistances can be analytically modeled by using thecurrent flow pattern indicated by the shaded regions in Fig. 7.28. In thisfigure, the depletion region boundaries have also been shown usingdashed lines. The drain current flows through a channel region with asmall cross-section before entering the JFET region. The current spreadsinto the drift region from the JFET region at a 45 degree angle and thenbecomes uniform. The dimension a in Fig. 7.28 is decided by alignmenttolerances used during device fabrication. A typical value of 0.5 micronshas been assumed for the analysis in this chapter.
  • 194. 172 SILICON CARBIDE POWER DEVICES The channel resistance is given by: pD(LCH+aWP)p R CH - • [7.13] (*ai-Wo-WF)where tcH and LCH are the channel thickness and length as shown in Fig.7.28. In this equation, a is a factor that accounts for current spreadingfrom the channel into the JFET region at their intersection. WG and WPare the zero-bias depletion widths at the gate contact and P+ regions,respectively. They can be determined using: w = fr,V„ [7.14] gND w = W„ [7.15] qNDwhere the built-in potential VbiG for a metal-semiconductor gate contactis typically 1 volt while the built-in potential Vbjp for the P+ junction istypically 3.3 volts for 4H-SiC. The JFET region resistance is given by: KjFET ~ PD VCH + tp WG ) [7.16] Wj ~WpJwhere p is the cell pitch. The drift region spreading resistance can be obtained by using: 2p 2p RD=Pc In + pD(t-s-WP) [7.17] W -W Wj-Wr) YVj YYpJwhere t is the thickness of the drift region below the P+ region and s isthe width of the P+ region. The contribution to the resistance from the N+ substrate is givenby: subs r^subs isubs subs [7.18]where psubs and tsubs are the resistivity and thickness of the substrate,respectively. A typical value for this contribution is 4 x 10"4 Q-cm2.
  • 195. Metal-Semiconductor Field Effect Transistors 173 12 3kV 4H-S1C 0.751: Planar MESFET 10 tcH=1.0 (tm 2.0I Otm)! 0.2 0.4 0.6 0.8 1.0 Channel Length (microns) Fig. 7.29 Analytically Calculated On-Resistance for a 4H-SiC Planar MESFET. 7 0.75*fe 6u 1.0a3 2.0•55X •aO 3kV 4H-SiC - Oim) uSB8 Planar MESFET tuQ. ^ = 1 . 2 urn 1 0.2 0.4 0.6 0.8 1.0 Channel Length (microns) Fig. 7.30 Analytically Calculated On-Resistance for a 4H-SiC Planar MESFET.
  • 196. 174 SILICON CARBIDE POWER DEVICES Using the analytical expressions, it is possible to model thechange in specific on-resistance with alterations of the cell designparameters. The specific on-resistance is most sensitive to variations ofthe channel length (L C H) and thickness (tCH), as well as the width of theJFET region (Wj). The variation of the specific on-resistance withincreasing channel length is shown in Fig. 7.29 and 7.30 for cases ofchannel thickness of 1 and 1.2 microns, respectively. It can be seen thatopening up the channel thickness reduces the specific on-resistance andits dependence on the channel length. Opening the JFET width beyond 1micron does not improve the on-resistance significantly7.5 Planar MESFET Structure: Numerical SimulationsNumerical simulations of the planar MESFET structure were performedto examine the on-state and blocking characteristics in detail. The impactof changing cell parameters was determined for the case of drift regionwith doping concentration of 1 x 1016 cm"3 and thickness of 20 microns.As in the case of the trench MESFET structure, the development of thepotential barrier is critical to the ability for these devices to support highdrain voltages without current flow. In the planar MESFET, the potentialbarrier is formed at point C in the channel. Its magnitude is determinednot only by the channel dimensions but also the JFET dimensionsbecause this impacts the potential developed under the gate withincreasing drain bias. Since the analytical model indicated that the on-resistance is sensitive to the channel length and thickness, theseparameters were varied to examine their impact on overall deviceperformance. In each case, the on-state resistance was extracted at zerogate bias, and the blocking characteristics were obtained by applicationof various negative gate bias voltages. A gate metal work-function of 5.2eV was used corresponding to a barrier height of 1.5 eV.7.5.1 Planar MESFET Structure: On-State CharacteristicsThe on-state resistance of the planar MESFET structure was determinedwith the sub-surface P+ region connected to the source electrode and thegate held at zero potential. First, consider the case of a planar MESFETwith a JFET region width (Wj) of 1 micron. The width of the N+ sourceregion and its spacing from the gate edge (total dimension a in Fig.7.28) was kept constant for all structures at a value of 0.5 microns. The
  • 197. Metal-Semiconductor Field Effect Transistors 175impact of changing the channel length (Lad was studied by using valuesof 0, 0.25, 0.75, and 1 micron, while keeping channel thickness (tCH) of 1micron between the P+ region and the gate metal. Channel length = 0.75 microns Distance (microns) Channel Length = 0 microns Distance (microns) Fig. 7.31 On-State Current Flow in 4H-SiC Planar MESFETs: The on-state current flow patterns for two of the structures atzero gate bias are shown in Fig. 7.31. It can be seen that the current flowis severely constricted in the channel of the device with channel length of0.75 microns (see upper part of Fig. 7.31) because of the extension ofdepletion regions from both the P+ region and the gate contact.Consequently, the channel contribution becomes significant unless thechannel length is small. Even for the extreme case of a device structurewith zero channel length, shown in the lower part of Fig. 7.31, there is
  • 198. 176 SILICON CARBIDE POWER DEVICESstill some constriction of the current flow in the channel region becauseof the lateral extension of the depletion region from the P+ region. Thecurrent then flows into the JFET region and spreads rapidly (at an angleof 45 degrees) into the drift region eventually becoming uniform at adepth of 4 microns from the top surface. Channel Thickness = 1 micron Fig. 7.32 On-State Current Flow in 4H-SiC Planar MESFETs. Another method to reducing the channel resistance is byincreasing the thickness of the channel. This provides a larger cross-section in the channel for the transport of the current as shown in Fig.7.32. The improved current pattern produces a reduction of the specificon-resistance from 4.25 mii-cm2 to 2.87 miJ-cm . This is in goodagreement with the predictions of the analytical model previously
  • 199. Metal-Semiconductor Field Effect Transistors 177discussed in this chapter. The impact of the change in channel aspectratio on the blocking gain for these structures is discussed in the nextsection. In the simulations, the specific on-resistance for the device with0.25 micron channel length was found to be 4.25 mQ-cm2. This is inreasonable agreement with the value of 4.9 mQ-cm2 obtained using theanalytical model. However, it is about 4 times larger than the idealspecific on-resistance for the drift region for a structure capable ofsupporting 3000 volts. When the channel length was reduced to zero, thespecific on-resistance was found to reduce to 2.93 mQ-cm2. The impactof the channel length reduction on the blocking characteristics isdiscussed in the next section7.5.2 Planar MESFET Structure: Blocking Characteristics Channel Length = 0.75 micron JFET Spacing = 1 micron 0 0.5 1.0 1.5 2.0 Distance (microns) Fig. 7.33 Channel Potential Barrier in a 3 kV 4H-SiC Planar MESFET.In the planar MESFET structure, the ability to block current flow withpositive drain voltage can be achieved by application of a negative gatebias. The gate bias depletes the space between the gate region and the
  • 200. 178 SILICON CARBIDE POWER DEVICESsub-surface P+ region, which produces a potential barrier to the flow ofelectrons from the source to the drain. A larger potential barrier can beformed with larger gate bias voltage as discussed earlier. The behavior ofthe planar MESFET structure is discussed here with the aid of resultsfrom two-dimensional numerical simulations. In the MESFET structure, electron injection can occur over theportion of the channel with the smallest potential barrier leading the on-set of current flow. The smallest potential barrier occurs at the center ofthe channel. For this reason, the potential variation along the center ofthe channel region (i.e. at y = 0.5 microns in Fig. 7.31 and Fig. 7.32) isshown in Fig. 7.33. Since the channel is nearly depleted at zero gate bias,a potential barrier develops in the channel even for a gate bias of -2 volts.The magnitude of the potential barrier increases with gate bias andreaches a value of -3 volts a gate bias of -10 volts. 4.U 2 3kV 4H-SiC Planar MESFET L1.0 ~ &0.75 • 0.50 ^3.0 L 0 ! Channel Poten alBa Hi :> <** i.U 0 0 2 A t S l0 Re verse Gate Bias (Volts) Fig. 7.34 Channel Potential Barriers in 3 kV 4H-SiC Planar MESFETs. The magnitudes of the channel potential barrier for the cases ofchanges in the channel length ranging from 0 to 1 micron are shown inFig. 7.34. Once the potential barrier is formed, a linear increase in thebarrier height is observed for all cases with increasing gate bias. Thepotential barrier height is relatively small (only -3 volts at a reverse gatebias of -10 volts) when compared with the barrier heights observed in the
  • 201. Metal-Semiconductor Field Effect Transistors 179trench MESFET structure. However, this is found to be adequate forproviding a high blocking voltage capability because of shielding of thechannel region by the JFET region in the planar MESFET structure. Themagnitude of the potential barrier height created by the gate bias wasfound to be insensitive to the width of the JFET region. The blocking voltage capability of the MESFET structure isdependent upon its ability to retain a potential barrier to the transport ofelectrons from the source to the drain as the drain bias is increased. Therelatively small change in the barrier height with increasing drain voltageobserved for the device structure with channel length of 0.75 micronsand JFET spacing of 1 micron is shown in Fig. 7.35 when a channelthickness of 1 micron is used. A potential barrier is retained even whenthe drain bias is increased to 3000 volts indicating the ability to supporthigh blocking voltages. A larger reduction of the potential barrier is observed when thechannel length is reduced from 0.75 microns to 0.25 microns as shown inFig. 7.36. In this case, the potential barrier becomes small when the drainbias exceeds 1500 volts indicating problems with supporting high drainbias voltages without electron injection induced current flow. Channel Length = 0.75 micron JFET Spacing = 1 micron 1A 1U V DS VGs = -10V Increasing VDS 3000 V 8 2500 V •rain-•Sourc e Poteiitial (V) y^— 2000 V 6 1500 V 4 1000 V y 2 500 V ^— H 0 ~ V_^#J 100 V 50 V -2 N^g ^B^ 10 V 0V C 0.5 1.0 1.5 2.0 Distan ce (microns) Fig. 7.35 Channel Potential distribution in a 3 kV 4H-SiC Planar MESFET.
  • 202. 180 SILICON CARBIDE POWER DEVICES Channel Length = 0.25 micron JFET Spacing = 1 micron 3000 V VGS = -10V Increasing V D S / ^ ^ 8 ^ 2500 V (A) 2000 V Potential 6 1500 V 4 1000 V 8 Soui 500 V 2 i £ 0 100 V 50 V -2 10 V OV 0 0.5 1.0 1.5 Distance (microns) Fig. 7.36 Channel Potential distribution in a 3 kV 4H-SiC Planar MESFET. Channel Length = 0.25 micron JFET Spacing = 2 micron 3000 V / / / / VDS V = -10 V Increasing / / / / /—s 8 VDSy ////, 100 V > /soov •a •*-! A a 50 V & 4 <u u u S o 2 Ul a 10 V CD b 0 Q -2 0V 0.5 1.0 1.5 2.0 2.5 Distance (microns) Fig. 7.37 Channel Potential distribution in a 3 kV 4H-SiC Planar MESFET.
  • 203. Metal-Semiconductor Field Effect Transistors 181 The reduction of the potential barrier with increasing drain biasis relatively small for the above structures in which the channel is wellshielded by the JFET regions whose width is 1 micron. When the widthof the JFET region is enlarged to 2 microns, the shielding becomes muchless effective as shown in Fig. 7.37. This structure has a much lowerblocking gain than the structure with a JFET width of 1 micron. Asdiscussed later in this section, the gate bias required to support 3000volts for the structure with JFET width of 2 microns approaches the gate-source breakdown voltage. This compromises its ability to provide thefull blocking voltage capability of the drift region The reduction of the potential barrier height with increasingdrain voltage is shown in Fig. 7.38 for the case of planar MESFETs withchannel lengths of 0.25 and 0.75 microns with the same JFET width of 1micron. It can be seen that the barrier height reduces to a greater extentwhen the channel length is smaller. When the JFET width is increased to2 microns with a channel length of 0.25 microns, the potential barrier iscompletely removed at a drain bias of above 1500 volts. Thus, thisstructure cannot support high drain voltages with a gate bias of -10 volts. I I I is 3kV 4H-SiC Planar MESFET (VGS = -10V) > I I I Channel Length - 0.75 Jim JFET Widths 1.0 nm I 20 . / - , Channel Length = 0.25 urn I 10 JFET Width = 2.0 |im Channel Length = 0.25 urn JFET Width = 1.0 urn 1000 2000 3000 Drain Bias (Volts) Fig. 7.38 Channel Potential Barriers in 3 kV 4H-SiC Planar MESFETs. In general, the normally-on MESFET structure can support alarger drain bias voltage without significant drain current flow if the gate
  • 204. 182 SILICON CARBIDE POWER DEVICESvoltage is increased. However, the reverse gate bias cannot be arbitrarilyincreased because of the on-set of gate-source breakdown. Thebreakdown voltage between the gate and source regions is decided thedepletion layer reach-through between the gate and the P+ region. For achannel thickness of 1 micron, the gate breakdown voltage was found tobe -12 volts. When the channel thickness was increased to 1.2 microns,the breakdown voltage improved to -16 volts. When the gate bias is changed, the on-set of drain current up toany given leakage current level occurs at different drain bias voltages.This produces triode-like characteristics between the drain current andvoltage. A typical set of I-V characteristics is shown in Fig. 7.39 for thecase of the structure with channel length of 0.25 microns, channelthickness of 1 micron and JFET width of 1 micron. The structure is ableto support a drain bias of over 3000 volts with a gate bias of only -10volts. Thus, the planar MESFET structure exhibits an extremely highblocking gain even for a short channel length. In fact, the structure withchannel length of 0.75 microns could support a drain bias of over 3000volts with a gate bias of only -4 volts. Channel Length = 0.25 microns JFET Spacing = 1 micron Fig. 7.39 Blocking Characteristics for a 3 kV 4H-SiC Planar MESFET.
  • 205. Metal-Semiconductor Field Effect Transistors 183 Channel Length = 0 microns JFET Spacing = 1 micron Drain Bias (kV) Fig. 7.40 Blocking Characteristics for a 3 kV 4H-SiC Planar MESFET. When the channel length is reduced to zero, the blocking gaindeteriorates as shown in Fig. 7.40 and the structure is unable to support adrain bias of 3000 volts unless the gate voltage is increased beyond -14volts. Under these gate bias conditions, there is substantial gate currentflow due to the on-set of reach-through induced breakdown. Thisdemonstrates the need to retain some overlap between the edge of thesub-surface P+ region and the edge of the gate electrode during thedesign of the planar MESFET structure. The amount of the overlap,which determines the channel length, must be decided by performing atrade-off between minimizing the on-state resistance and maximizing theblocking gain. The drain blocking voltage at a leakage current density of 1mA/cm2 is plotted in Fig. 7.41 for the planar MESFET structure withchannel thickness of 1 micron and JFET spacing of 1 micron as afunction of the magnitude of the reverse gate bias. From this graph, theneed to provide a small (0.25 micron) overlap between the P+ region andthe gate contact is quite clear.
  • 206. 184 SILICON CARBIDE POWER DEVICES 1 1 Channel Length = 0.25 (im rt 3000 _ . Channel Length = 0.S urn 2000 1000 3kV 4H-SiC Planar MESFET 0 Ii i >*--• 1 1 . 0 2 4 6 8 10 12 14 Reverse Gate Bias (Volts) Fig. 7.41 Drain Blocking Voltage for 3 kV 4H-SiC Planar MESFETs. — i i 1 — JFET Spacing = 1 (im 3000 JFET Spacing = 2|im - JFET Spacing = 0.75 |im 2000 1000 3kV AH.Sir PI 1 anar MESFE• T 0 1 _ 4 6 8 10 12 14 Reverse Gate Bias (Volts) Fig. 7.42 Drain Blocking Voltage for 3 kV 4H-SiC Planar MESFETs. Similarly, the impact of changing the JFET spacing is shown inFig. 7.42 for the case of a channel length of 0.25 microns. When theJFET spacing is increased to 2 microns, the drain potential encroaches
  • 207. Metal-Semiconductor Field Effect Transistors 185into the channel and the drain voltage blocking capability deteriorates.The blocking voltage capability of the planar MESFET structuresbecomes limited by the on-set of gate breakdown to about 2500 volts.When the JFET spacing is reduced to 0.75 microns, the channel becomesextremely well shielded and the structure is able to support a drain biasof over 3000 volts with a gate bias of only -6 volts. The voltage blocking behavior of the planar MESFET structurecan be examined by looking at the blocking gain as a function of thechannel length. The DC blocking gain is defined as the ratio of the drainblocking voltage to the corresponding gate bias. This gain varies withdrain and gate bias as observed in the above figures. If the gain is takenby using the gate voltage required to support a drain bias of 3000 volts,then the various structures can be compared in terms of the channellength. This is done in Fig. 7.43 for the planar MESFET structuressimulated with various channel lengths using a channel thickness of 1micron and a JFET spacing of 1 micron. An exponential increase inblocking gain is observed with increasing channel length. Forcompleteness, the changes in the blocking gain with variations in theJFET spacing are included in this figure for the case of a channel lengthof 0.25 microns. 10,000 3kV 4H-SiC Planar MESFET JFET Spacing = 1 jim 1 0 0 »„ ° - JFET Spacing = 0.75 (im en a 2 u • j ^ ^ o JFET Spacing = 2|im 100 0.2 0.4 0.6 0.8 1.0 Channel Length (microns) Fig. 7.43 Blocking Gain for 3 kV 4H-SiC Planar MESFETs.
  • 208. 186 SILICON CARBIDE POWER DEVICES In the previous section, it was demonstrated that the on-resistance for the planar MESFET structure could be significantlyreduced by increasing the channel thickness. The impact of this changeon the blocking characteristics is shown in Fig. 7.44 for the case of achannel thickness of 1.2 microns when the channel length is 0.25microns and the JFET spacing is 1 micron. It can seen that this structurerequires a gate bias of -14 volts to block a drain bias of 3000 volts incontrast with only -8 volts required for the structure with channelthickness of 1 micron (whose characteristics are shown in Fig. 7.39). Theblocking gain is therefore reduced from about 400 to about 200.However, this is a good compromise because the structure has 50%lower specific on-resistance and still needs only 14 volts to block a drainbias of 3000 volts. This gate bias is also compatible with utilization ofthe planar MESFET in the Baliga-Pair circuit configuration with asilicon power MOSFET rated with blocking voltage of 20 to 30 volts. Channel Length = 0.25 microns Channel Thickness = 1.2 microns a S U 2 ex o 1 2 Drain Bias (kV) Fig. 7.44 Blocking Characteristics for a 3 kV 4H-SiC Planar MESFET.
  • 209. Metal-Semiconductor Field Effect Transistors 1877.5.3 Planar MESFET Structure: Output CharacteristicsThe output characteristics of the planar MESFET structure determine thesafe operating area of the device. In a typical pulse width modulatedcontrol scheme, the power transistor undergoes a switching transientfrom either the on-state to off-state or vice versa. The loci for thesetransients must be kept within the bounds of the safe operating area forthe transistor. Channel Length = 0.25 microns JFET Spacing = 1 micron Fig. 7.45 Output Characteristics for a 3 kV 4H-SiC Planar MESFET. As expected from the previous discussion, the channel designhas a strong impact on the output characteristics of the planar MESFETstructure. For the structure with channel length of 0.25 microns, channelthickness of 1 micron, and JFET spacing of 1 micron, the outputcharacteristics exhibit a mixed triode-pentode behavior as shown in Fig.7.45. When the channel length is reduced to zero, the characteristics arebroadened to higher current levels as shown in Fig. 7.46. However, alarger gate bias is needed to traverse the safe-operating-area for thisdevice. A similar outcome is observed when the channel thickness isincreased from 1 micron to 1.2 microns with a channel length of 0.25microns as shown in Fig. 7.47.
  • 210. 188 SILICON CARBIDE POWER DEVICES Channel Length = 0 microns JFET Spacing = 1 micron 1 2 Drain Bias (kV) Fig. 7.46 Output Characteristics for a 3 kV 4H-SiC Planar MESFET. Channel Length = 0.25 microns Channel Thickness = 1.2 microns 1 2 Drain Bias (kV) Fig. 7.47 Output Characteristics for a 3 kV 4H-SiC Planar MESFET.
  • 211. Metal-Semiconductor Field Effect Transistors 1897.5.4 Planar MESFET Structure: Gate Contact ShieldingOne of the key advantages of the planar MESFET structure is the abilityto shield the gate contact from the high electric fields developed withinthe semiconductor when the device is biased close to the breakdownvoltage capability of the drift region. In the planar MESFET structure,the depletion of the JFET region (location D in Fig. 7.27) at a relativelylow drain bias voltage produces a potential barrier. This barrier preventsincrease in the electric field at the semiconductor surface under the gatecontact (location B in Fig. 7.27) with further increase in the drain biasvoltage. Consequently, the maximum electric field in the semiconductoroccurs just below the bottom of the sub-surface P+ region. JFET Spacing = 1 micron Fig. 7.48 Electric Field within a 3 kV 4H-SiC Planar MESFET. A three-dimensional view of the electric field is shown in Fig.7.48 for a structure with JFET spacing of 1 micron at a drain bias of 3000volts and a gate bias of -10 volts. The highest electric field is observed atthe bottom of the sub-surface P+ region with some enhancement at itscorner as indicated in the figure. The electric field at the semiconductor
  • 212. 190 SILICON CARBIDE POWER DEVICESsurface is low under the entire gate contact interface due to the shieldingprovided by the junction. The development of the electric field at thegate contact interface can be best observed at the right hand edge of thecell structure shown in Fig. 7.27 where it has the highest value. Thechange in the electric field at various drain bias voltages is shown in Fig.7.49 for the case of a JFET spacing of 1 micron. As expected, this fielddistribution was found to be independent of the channel length andthickness as long as the JFET spacing is kept at 1 micron. It can beclearly seen that that the largest electric field at the gate contact interface(EM(Surface)) is much smaller than the maximum electric field(EM(Bulk)) in the bulk of the semiconductor. The electric field at thegate contact interface remains below 4 x 103 V/cm even for a drain biasof 3000 volts while the electric field in the bulk approaches thebreakdown strength of 3 x 106 V/cm. The low electric field at the gatecontact prevents high leakage currents associated with Schottky barrierlowering and tunneling phenomena. These results demonstrate the abilityto fully utilize the breakdown strength of the semiconductor materialwithout encountering a gate contact breakdown and leakage problem. JFET Spacing = 1 micron 3.0 EM(Bulk) Increasing Drain Bias in steps of 500V EM(Surface) 5 10 15 20 Distance (microns) Fig. 7.49 Electric Field within a 3 kV 4H-SiC Planar MESFET.
  • 213. Metal-Semiconductor Field Effect Transistors 191 The suppression of the electric field at the gate contact interfaceis strongly dependent upon the JFET spacing because this determines thedrain bias at which a potential barrier is created in region D of the planarMESFET structure. The impact of changes to the JFET spacing on theelectric field within the planar MESFET structure is shown in Fig. 7.50.For all the structures, the electric field at the gate contact interface issmaller than the maximum electric field developed in the bulk just belowthe bottom of the P+ region. Considerable reduction of the gate contactfield is observed when the JFET spacing is reduced from 2 to 1 micron.The improvement obtained with reducing the JFET spacing to 0.75microns is not substantial. This indicates that a JFET spacing of 1 micronis optimal for this structure to suppress the electric field in the gatecontact while simultaneously obtaining a low specific on-resistance inthe on-state. 0 1000 2000 3000 Reverse Bias (Volts) Fig. 7.50 Electric Field within 3 kV 4H-SiC Planar MESFETs.7.6 Experimental Results: Trench Gate StructuresSeveral approaches can be taken to construct a vertical FET structure thatutilizes a potential barrier along the vertical path induced by a gate bias.The gate region in the device can be formed by using ion implantation ofP-type dopants to form a JFET structure or by placing a metal contact
  • 214. 192 SILICON CARBIDE POWER DEVICESwithin a trench etched between the source regions to form a MESFETstructure or by forming a hetero-j unction gate region within the trench toform a HJFET structure. Prior to the development of a process forformation of heavily doped P-type regions in silicon carbide, it was morepractical to construct the hetero-junction gate FET structure. The formation of a hetero-junction between P-type polysiliconand N-type silicon carbide was first demonstrated at PSRC in 199612.The band structure for the interface between P + Polysilicon and N-type6H-SiC is shown in Fig. 7.51. Good rectification was experimentallyconfirmed at this hetero-junction13 allowing consideration of thisjunction for the gate region in a HJFET structure, shown in Fig. 7.52.The fabrication process for this structure is simple because thepolysilicon gate material can be deposited into the trenches andplanarized due to the good selectivity between it and SiC during reactive-ion-etching. The HJFET structure was analyzed in detail in 199614followed by experimental demonstration15 of a structure with the P+polysilicon located within trenches etched between the source regions.Although some gate control was observed, the performance of thestructure was poor due to the bad quality of the surface within thetrenches after etching. P+ Polysilicon N- 6H-SiC a 1.25 eV Ec 2.7 eV Fig. 7.51 P+ Polysilicon/N- 6H-SiC Hetero-Junction Band Structure.
  • 215. Metal-Semiconductor Field Effect Transistors 193 A trench JFET structure that contains a MOS sidewall (alsoillustrated in Fig. 7.52) has been proposed and demonstrated16. Thisstructure requires ion implantation of the P+ region at the bottom of thetrenches after they have been etched. Since the authors masked the P+implant, the process is difficult to implement due to the poor topologyfor patterning photoresist in the presence of 1 micron deep trenches. Inaddition, it is not clear that the P-type implant will not occur on thetrench sidewalls, an effect disregarded by the authors. The authorsdeposited an oxide after the P+ implant and then refilled the trench withpolysilicon to create an MOS-structure on the trench sidewalls. Theprocess described by the authors precludes making contact to the P+ gateregions along the trenches. Since the contact to the P+ gate regions mustbe located at the periphery of the device, the structure would have poorswitching characteristics due to the very high resistance of the P+ fingersorthogonal to the cross-section. The authors report obtaining a specificon-resistance of 5 mii-cm2 for a device that is able to block 600 voltsusing a reverse gate bias of -30 volts. A similar structure with contactmade to the P+ region by the P+ polysilicon has been proposed17 but theauthors failed to describe how such a contact can be fabricated with lowcontact resistance. HETERO-JUNCTION BURIED-JUNCTION GATE FET GATE FET SOURCE GATE SOURCE vm> sm iU-i-iiiii- HI p+ Polysilicon $££$$£ -Oxide P+ Gate | N-DRIFT REGION N-DRIFT REGION N+ SUBSTRATE N+ SUBSTRATE Y/////////////A DRAIN V////////////A DRAIN Fig. 7.52 Novel Vertical Trench Gate SiC FET Structures.
  • 216. 194 SILICON CARBIDE POWER DEVICES The vertical JFET structure can also be fabricated using ionimplantation to form the P+ gate region. In order to obtain a good channelaspect ratio, it is necessary to resort to very high energy (1.3 MeV)aluminum implants to form the P+ gate regions18. The authors obtained ablocking voltage of 2000 volts with a reverse gate bias of -50 volts(blocking gain of 40). However, the on-resistance for the devices wasvery high unless a positive gate bias of 2.5 volts was applied. With thepositive gate bias, the gate depletion region was reduced allowing draincurrent flow through the channel with a specific on-resistance of 70 m£2-cm2. These values indicate poor optimization of the structure which had avery large cell pitch of 32 microns.7.7 Experimental Results: Planar Gate StructuresThe planar gate FET structure was originally proposed and patented in1996 with either a metal-semiconductor, or a junction, or an MOS gateregion9. It was proposed that the sub-surface P+ region be formed byusing ion-implantation with appropriate energy to locate the junctionbelow the surface so as to create an un-depleted N-type channel region.An obvious alternative approach is to grow an N-type epitaxial layerover the P+ regions implanted into a substrate to create the N-typechannel region. Experimental results on the lateral channel, vertical(planar) MESFET/JFET structures are discussed here. The MOS gatestructures are discussed in subsequent chapters. The first planar MESFET structures were successfully fabricatedat PSRC in 1996-97 by performing 380 keV boron ion-implants to formthe sub-surface P+ region19. Devices were fabricated from both 6H-SiCand 4H-SiC as the starting material with doping concentration of about 2x 1016 cm3. The energy for the boron implants was chosen to locate thecenter of the P+ region at about 0.5 microns below the surface20. Anadditional N-type nitrogen implant was used in the channel region toenhance its doping to produce normally-on devices. Contact to the sub-surface P+ region was made by additional boron implants at lower energyin selective regions within the cell structure. The devices were found toexhibit a low specific on-resistance of about 12 mQ-cm2 but had poorgate-drain breakdown voltage of about 50 volts. The planar JFET structures that were also fabricated at PSRC in1996-97 using the same process conditions described above had muchbetter blocking capability21. In these devices, the P+ gate region was
  • 217. Metal-Semiconductor Field Effect Transistors 195formed by using a shallow 10 keV boron implant. The 4H-SiC planarJFETs fabricated using a N-type channel implant with a dose of 1-2 x1013 cm2 exhibited a specific on-resistance of only 11-14 mQ-cm2. Thedevices were able to block a drain bias of 1100 volts with a negative gatebias of 40 volts. Excellent gate controlled pentode-like characteristicswith drain current saturation was observed in the devices upto thebreakdown voltage with a drain current density of 250 A/cm2. Lateral channel, vertical JFET structures, fabricated by epitaxialgrowth of an N-type layer over a P+ region implanted into the driftregion, have also been reported by several groups. The first such deviceswere reported11 in 1999 by using epitaxial layers capable of supporting600 V and 1200 V. By growing a epitaxial layer with dopingconcentration of about 2 x 1016 cm"3 with a thickness of 2.5 microns overthe sub-surface P+ region, the devices were able to support a gate bias ofmore than 10 volts above a channel pinch-off voltage of 40 volts. Thiswas sufficient to allow blocking a drain bias of 1200 volts. The specificon-resistance for the devices was 18, 25, and 40 mQ-cm2 for devicescapable of supporting 550, 800, and 950 volts, respectively. Theperformance of these structures was subsequently improved22 to ablocking voltage of 1800 volts with a specific on-resistance of 24.5 mQ-cm2.7.8 SummaryThe physics of operation of the normally-on vertical JFET/MESFETstructure has been described in this chapter. It is demonstrated that apotential barrier forms in the channel under reverse gate bias whichprevents the flow of drain current. The devices exhibit mixed triode-pentode like characteristics. The channel for these devices can beoriented along the vertical drain current flow path by using a trench gatearchitecture. Alternately, a lateral channel can be formed by introducinga sub-surface P+ region below a planar gate design. The planar deviceshave been successfully made using either a deep P+ ion implantation stepinto the N-drift region or by growth of an N-type epitaxial layer above apreviously implanted P+ region in the N-type drift region. Both methodshave resulted in devices with low specific on-resistance and good gatecontrolled current saturation capability with relatively low reverse gatebias voltages. These devices are suitable for utilization in the Baliga-Pairconfiguration discussed in the next chapter.
  • 218. 196 SILICON CARBIDE POWER DEVICESReferences1 J. Nishizawa, T. Terasaki, and J. Shibata, "Field Effect Transistorversus Analog Transistor (Static Induction Transistor)", IEEETransactions on Electron Devices, Vol. ED22, pp. 185-197, 1975.2 B. J. Baliga, "Modern Power Devices", John Wiley and Sons, 1987.3 B. J. Baliga, "Evolution of MOS-Bipolar Power SemiconductorTechnology", Proceedings of the IEEE, Vol. 74, pp. 409-418, 1988.4 B. J. Baliga, "Silicon Carbide Switching Device with RectifyingGate", U. S. Patent 5,396,085, Issued March 7, 1995.5 B. J. Baliga, "Power Semiconductor Devices", PWS PublishingCompany, 1996.6 P. Plotka and B. Wilamowski, "Interpretation of Exponential typeDrain Characteristics of the Static Induction Transistor", Solid StateElectronics, Vol. 23, pp. 693-694, 1980.7 B.J. Baliga, "A Power Junction Gate Field Effect Transistor Structurewith High Blocking Gain", IEEE Transactions on Electron Devices, Vol.27, pp. 368-373, 1980.8 X. C. Kun, "Calculation of Amplification Factor of Static InductionTransistors", DEE Proceedings, Vol. 131, pp. 87-93, 1984.9 B. J. Baliga, "High Voltage Junction Gate Field Effect Transistor withRecessed Gates", IEEE Transactions on Electron Devices, Vol. 29, pp.1560-1570, 1982.10 B. J. Baliga, "Silicon Carbide Semiconductor Devices having BuriedSilicon Carbide Conduction Barrier Layers Therein", U. S. Patent5,543,637, Issued August 6, 1996.1 H. Mitlehner, et al, "Dynamic Characteristics of High Voltage 4H-SiC Vertical JFETs", IEEE International Symposium on PowerSemiconductor Devices and ICs, Abstract 11.1, pp. 339-342, 1999.12 P. M. Shenoy and B. J. Baliga, "High Voltage P+ Polysilicon/N- 6H-SiC Heteroj unction Diodes", PSRC Technical Report TR-96-050, 1996.13 P. M. Shenoy and B. J. Baliga, "High Voltage P+ Polysilicon/N- 6H-SiC Heteroj unction Diodes", Electronics Letters, Vol. 33, pp. 1086-1087,1997.14 B. Vijay, K. Makeshwar, P. M. Shenoy, and B. J. Baliga, "Analysis ofa High Voltage Heteroj unction Gate SiC Field Effect Transistor", PSRCTechnical Report TR-96-049, 1996.15 P. M. Shenoy, V. Bantval, M. Kothandaraman, and B. J. Baliga, "ANovel P+ Polysilicon/N- SiC Heterojunction Trench Gate Vertical FET",
  • 219. Metal-Semiconductor Field Effect Transistors 197IEEE International Symposium on Power Semiconductor Devices andICs, pp. 365-368, 1997.16 R. N. Gupta, H.R. Chang, E. Hanna, and C. Bui, "A 600 V SiCTrench JFET". Silicon Carbide and Related Materials - 2001, MaterialScience Forum, Vol. 389-393, pp. 1219-1222, 2002.17 L. Zhu and T. P. Chow, "Design and Processing of High Voltage 4H-SiC Trench Junction Field Effect Transistor", Silicon Carbide andRelated Materials - 2001, Material Science Forum, Vol. 389-393, pp.1231-1234,2002.18 H. Onose, et al, "2 kV 4H-SiC Junction FETs", Silicon Carbide andRelated Materials - 2001, Material Science Forum, Vol. 389-393, pp.1227-1230, 2002.19 P. Shenoy and B. J. Baliga, The Planar Lateral Channel SiCMESFET", PSRC Technical Report TR-97-038, 1997.20 M. S. Janson, et al, "Range distributions of Implanted Ions in SiliconCarbide", Silicon Carbide and Related Materials - 2001, MaterialScience Forum, Vol. 389-393, pp. 779-782, 2002.21 P. Shenoy and B. J. Baliga, "A Planar Lateral Channel SiC VerticalHigh Power JFET", PSRC Technical Report TR-97-036, 1997.22 P. Friedrichs, et al, "Static and Dynamic Characteristics of 4H-SiCJFETs Designed for Different Blocking Categories", Silicon Carbide andRelated Materials - 1999, Material Science Forum, Vol. 338-342, pp.1243-1246, 2000.
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  • 221. Chapter 8 The Baliga-Pair ConfigurationThe advent of semiconductor based power electronics began with theavailability of silicon bipolar devices in the 1950s. The development ofbipolar power junction transistors for medium power applications andsilicon gate turn-off thyristors for high power applications enabledsignificant enhancement in system performance by replacement ofvacuum tubes. However, the low current gain (< 10) for structuresdesigned to support high voltages resulted in large, expensive controlcircuits. The concurrent development of CMOS technology in the 1960senabled the power semiconductor industry to introduce power MOSFETsin the 1970s. These devices rapidly captured the market for low power (<100 watts) systems where the operating voltages are relatively low (<100 volts). The metal-oxide-semiconductor (MOS) gate structure in thesedevices could be driven using small pulses of current with essentiallynegligible steady state currents. The low input power requirementsenabled the subsequent integration of the control circuit resulting in ahuge improvement in the size and cost of the system. The relatively high on-resistance of silicon MOSFETs was asignificant drawback for application in higher power systems thatworked with high operating voltages (>200 volts). However, in the1980s, a conceptual break-through enabled combining the physics of theMOS and Bipolar structures to create a new class of devices1. Thecommercial introduction of the Insulated Gate Bipolar Transistor (IGBT)with its high input impedance MOS-gate structure and high output powerhandling capability revolutionized medium and high power systemdesign. As in the case of the power MOSFET, the IGBT could becontrolled by using a small integrated drive circuit resulting in compact,low cost solutions for consumer, industrial, medical, and automotiveapplications. This has set the bench-mark that any new proposedtechnology must be able to surmount in order to be considered anattractive replacement for the existing silicon MOS-gated devices. 199
  • 222. 200 SILICON CARBIDE POWER DEVICES As had occurred during the evolution of silicon technology, theability to produce a high quality interface between silicon carbide and asuitable gate dielectric material has been a significant challenge2. Inaddition to a larger density of charge in the oxide and at the interface thatcauses threshold voltage shift, the inversion layer mobility was found tobe very low when compared with silicon. To compound the problem, theconventional silicon power MOSFET structure could not provide the fullbenefits of the high breakdown field strength of the silicon carbidematerial because of reliability and rupture problems associated with theenhanced electric field in the gate oxide. In order to overcome these problems, it was proposed3 that anormally-on silicon carbide high voltage JFET/MESFET be usedtogether with a low voltage silicon MOSFET to create a compoundswitch with the desired features for a high quality power switch. In ananalogy to the Darlington-Pair configuration commonly used for powercontrol applications, it was suggested5 that the proposed combination ofdevices be named the Baliga-Pair configuration. The same circuitconfiguration has also been subsequently called the Cascode circuit6 withthe acknowledgement that it was first disclosed in a textbook in 19967.The idea was also presented in 1996 at the Conference on SiliconCarbide and Related Devices8 held in Kyoto, Japan. This chapter discusses the operating principles of the Baliga-Pairconfiguration. It is demonstrated that a silicon power MOSFET with lowbreakdown voltage rating (and hence low specific on-resistance) can beused to control a high voltage, normally-on silicon carbideJFET/MESFET structure. This enables supporting large voltages withinthe silicon carbide FET while allowing control of the composite switchwith signals applied to the MOS gate electrode of the silicon MOSFET.The same type of simple, low cost, integrated control circuits used forsilicon power MOSFETs and IGBTs can therefore be utilized for theBaliga-Pair configuration. Since both devices in the configuration areunipolar devices, the Baliga-Pair has very fast switching speed andexcellent safe-operating-area. In concert with the low on-resistance forboth the FETs, the fast switching speed results in very low overall powerdissipation in applications9. In addition, this configuration contains anexcellent fly-back diode allowing replacement of not only the IGBT butalso the fly-back rectifier that is usually connected across it in H-bridgepower circuits. From this stand-point, it is preferable to use the siliconcarbide MESFET structure due to lower on state voltage drop of theSchottky diode.
  • 223. The Baliga-Pair Configuration 2018.1 The Baliga-Pair Configuration sB sB Si L O W s„ VOLTAGE G*B MOSFET GB —. D.. SOURCE 7////////A IM* SIC SiC H I G H A VOLTAGE MESFET N-DRIFT REGION D SIC N* SUBSTRATE V//////////////////A DRAIN ( DB i • OB Fig. 8.1 The Baliga-Pair Power Switch Configuration. The Baliga-Pair configuration consists of a low breakdownvoltage silicon MOSFET and a normally-on, high voltage silicon carbideJFET/MESFET connected together as shown in Fig. 8.1. Any of thetrench gate or planar gate JFET/MESFET structures discussed in theprevious chapter can be used to provide the high blocking voltagecapability. It is important that the silicon carbide FET structure bedesigned for normally-on operation with a low specific on-resistance. Itis also necessary for the silicon carbide FET to be able to block the drainbias voltage with a gate bias less than the breakdown voltage of thesilicon power MOSFET. The silicon power MOSFET can be either a planar DMOSstructure or a trench-gate UMOS structure to provide low specific on-resistance. The source of the silicon carbide FET is connected to thedrain of the silicon power MOSFET. Note that the gate of the siliconcarbide FET is connected directly to the reference or ground terminal.The path formed between the drain and the gate contact of the silicon
  • 224. 202 SILICON CARBIDE POWER DEVICEScarbide FET creates the fly-back diode. The composite switch iscontrolled by the signal applied to the gate of the silicon powerMOSFET.8.1.1 Baliga-Pair Configuration: Voltage Blocking ModeThe composite switch can block current flow when the gate of the siliconpower MOSFET is shorted to ground by the external drive circuit. Withzero gate bias, the silicon power MOSFET supports any bias applied toits drain terminal (DM) unless the voltage exceeds its breakdown voltage.Consequently, at lower voltages applied to the drain terminal (DB) of thecomposite switch, the voltage is supported across the silicon powerMOSFET because the silicon carbide JFET is operating in its normally-on mode. However, as the voltage at the drain (DM) of the siliconMOSFET increases, an equal positive voltage develops at the source(SSiC) of the silicon carbide FET. Since the gate (GSic) of the siliconcarbide FET is connected to the ground terminal, this produces a reversebias across the gate-source junction of the silicon carbide FET.Consequently, a depletion layer extends from the gate contact/junctioninto the channel of the silicon carbide FET. When the depletion regionpinches off the channel at location A, further increase in the bias appliedto the drain (DB) of the composite switch is supported across the siliconcarbide FET. Since the potential at the source of the silicon carbide FETis then isolated from the drain bias applied to the silicon carbide FET, thevoltage across the silicon power MOSFET is also clamped to a valueclose to the pinch-off voltage of the silicon carbide FET. This featureenables utilization of a silicon power MOSFET with a low breakdownvoltage. Such silicon power MOSFETs have very low specific on-resistance with a mature technology available for their production. Fromthis point of view, it is desirable to utilize silicon power MOSFETs withbreakdown voltages of below 50 volts. If the Baliga-Pair is designed to support a drain bias of 3000volts, the ability to utilize a silicon power MOSFET with a breakdownvoltage of 30 volts requires designing the silicon carbide FET so that thechannel is pinched-off at a gate bias of below 20 volts. Thus, theblocking gain of the silicon carbide FET should be in excess of 150. Thisis feasible for both the trench-gate and planar gate architectures forsilicon carbide FETs discussed in the previous chapter. As pointed out inthat chapter, much larger blocking gains could be achieved with the
  • 225. The Baliga-Pair Configuration 203planar MESFET structure making it an attractive choice for use in theBaliga-Pair configuration.8.1.2 Baliga-Pair Configuration: Forward Conduction ModeThe composite switch shown in Fig. 8.1 can be turned-on by applicationof a positive gate bias to the gate (GB). If the gate bias is well above thethreshold voltage of the silicon power MOSFET, it operates with a lowon-resistance. Under these conditions, any voltage applied to the drainterminal (DB) produces current flow through the normally-on siliconcarbide FET and the silicon MOSFET. Due to the low specific on-resistance of both structures, the total on-resistance of the Baliga-Pairconfiguration is also very small: Ron (Baliga - Pair) = Ron (SiliconMOSFET) + Ron (SiCFET) [ 8.1]Depending up on the size of the two devices, an on-resistance of lessthan 10 milli-Ohms is feasible even when the switch is designed tosupport 3000 volts. This indicates that the Baliga-Pair configuration willhave an on-state voltage drop of about 1 volt with a nominal on-statecurrent density of 100 A/cm2 flowing through the devices. This is wellbelow typical values of around 4 volts for an IGBT designed to supportsuch high voltages.8.1.3 Baliga-Pair Configuration: Current Saturation ModeOne of the reasons for the success of the silicon power MOSFET andIGBT in power electronics applications is the gate controlled currentsaturation capability of these devices. This feature enables controllingthe rate of rise of current is power circuits by tailoring the input gatevoltage waveform rather than by utilizing snubbers that are required fordevices like gate turn-off thyristors. In addition, current saturation isessential for survival of short-circuit conditions where the device mustlimit the current. The current saturation capability is inherent in the Baliga-Pairconfiguration. If the gate voltage applied to the Baliga-Pair configurationis close to the threshold voltage of the silicon MOSFET, it will enter itscurrent saturation mode when the drain bias increases. This produces aconstant current through both the silicon MOSFET and the siliconcarbide FET while the drain bias applied to the composite switchincreases. At lower drain bias voltages applied to the drain terminal (DB),
  • 226. 204 SILICON CARBIDE POWER DEVICESthe voltage is supported across the silicon power MOSFET. As thisvoltage increases, the channel in the silicon carbide FET gets pinched-offand further voltage is then supported by the silicon carbide FET. Underthese bias conditions, both the devices sustain current flow whilesupporting voltage. The level of the current flowing through the devicesis controlled by the applied gate bias. In this sense, the Baliga-Pairbehaves like a silicon power MOSFET from the point of view of theexternal circuit on both the input and output side. This feature makes theconfiguration attractive for use in power electronic systems because theexisting circuit topologies can be used. The safe-operating-area of thecomposite switch is mainly determined by the silicon carbide FETbecause it supports a majority of the applied drain voltage. The excellentbreakdown strength, thermal conductivity, and wide band gap of siliconcarbide ensure good safe-operating-area for the FET structures.8.1.4 Baliga-Pair Configuration: Switching CharacteristicsThe transition between the on and off modes for the Baliga-Pairconfiguration is controlled by the applied gate bias. During turn-on andturn-off, the gate bias must charge and discharge the capacitance of thesilicon power MOSFET. Since silicon power MOSFETs are extensivelyused for high frequency power conversion, their input capacitance andgate charge have been optimized by the industry10. The switching speedof the Baliga-Pair is consequently very high because of the availability ofsilicon power MOSFETs designed for high frequency applications. Themain limitations to the switching speed of the Baliga-Pair will be relatedto parasitic inductances in the package that could produce high voltagespikes.8.1.5 Baliga-Pair Configuration: Fly-Back DiodeThe Baliga-Pair contains an inherent high quality fly-back rectifier.When the drain bias is reversed to a negative value, the gate-draincontact/junction of the silicon carbide FET becomes forward biased.Since the gate of the silicon carbide FET is directly connected to theground terminal, current can flow through this path when the drainvoltage is negative in polarity. From this stand-point, it is preferable touse a metal-semiconductor contact for the gate rather than a P-Njunction. The Schottky gate contact provides for a lower on-state voltagedrop by proper choice of the work-function for the gate contact. In
  • 227. The Baliga-Pair Configuration 205addition, the Schottky contact has no significant reverse recoverycurrent. This greatly reduces switching losses in both the rectifier and theFETs . Thus, the Baliga-Pair configuration replaces not just the powerswitch (such as the IGBT or GTO) in applications but also the powerrectifier that is normally used across the switch.8.2 Baliga-Pair: Simulation Results SOURCE M s, y///M O,E XD |i>V •"•-•- •- fv«v GATE p Si LOW VOLTAGE MOSFET N-DRIFT F, E G I 0 N N + SUBSTRATE ///////ssssssssssssssJ E4 WMZ N* 1 A a ! i ILSJI G SiC SiC HIGH VOLTAGE MESFET N-DRIFT F1EGI0N N* SUBSTRATE E2 y///////////////////A DRAIN D B Fig. 8.2 Concatenated Silicon MOSFET and 4H-SiC MESFET Model.In order to demonstrate the operation of the Baliga-Pair configuration,two-dimensional numerical simulations were performed byconcatenating a silicon power MOSFET with a silicon carbide MESFETas illustrated in Fig. 8.2. This allowed observation of the potential andcurrent distribution within both devices during all modes of operation.The silicon carbide MESFET had a drift region with doping
  • 228. 206 SILICON CARBIDE POWER DEVICESconcentration of 1 xlO16 cm3 and thickness of 20 microns designed tosupport 3000 volts. A trench gate region with a depth of 1 micron waschosen based upon the simulation results in the previous chapter. Thespacing between the gate regions (dimension a in the figure) waschosen as 0.6 microns because this provided a good trade-off betweennormally-on operation with low specific on-resistance and a goodblocking gain. A work function of 4.5 eV was used for the gate contactcorresponding to a barrier height of 0.8 eV. The silicon power MOSFET had a trench gate design to reduceits on-resistance and make the structure compatible with the trench gatesilicon carbide FET for simulations. The gate oxide for the MOSFETwas chosen as 500 angstroms with a peak P-base doping concentration of3 x 1017 cm"3. This resulted in a threshold voltage of 4.5 volts for theMOSFET which is acceptable for high voltage power switches that canbe driven using 10 volt gate signals. The drift region for the siliconpower MOSFET had a doping concentration of 1.5 xlO16 cm"3 andthickness of 2.5 microns designed to support 30 volts. The gate electrode (E5) for the silicon carbide MESFET wasconnected to the source electrode (E0 of the silicon power MOSFETduring all the simulations. The electrode (E4) served as both the sourcecontact to the silicon carbide MESFET and the drain contact for thesilicon power MOSFET. This electrode was treated as a floatingelectrode (zero current boundary conditions) whose potential wasmonitored to provide insight into the voltage sharing between the twodevices. The high voltage DC bias was applied to the drain (E2) of thesilicon carbide MESFET while the input control signal was applied to thegate electrode (E3) of the silicon power MOSFET.8.2.1 Baliga-Pair Simulations: Voltage Blocking ModeTo operate the Baliga-Pair configuration in the voltage blocking mode,the gate electrode was held at zero bias and a drain bias was applied tothe drain (E2) of the silicon carbide MESFET structure. The compositeswitch was able to support 3000 volts with the potential on the drainelectrode (E4) of the silicon MOSFET remaining below 30 volts. Thepotential distribution can be observed in Fig. 8.3 within both thetransistors. The potential contours in the figure are mapped using aninterval of 50 volts. It can be seen that most of the applied drain voltageis supported by the silicon carbide MESFET structure. The channelregion adjacent to the Schottky gate contact of the silicon carbide
  • 229. The Baliga-Pair Configuration 207MESFET has a low potential because the channel is depleted at drainbias of only 5 volts. No potential contours are visible within the siliconMOSFET because it is supporting less than 50 volts. Cell Pitch = 1.1 microns Source Gate Silicon Floating 2s MOSFET Electrode 4H-SiC MESFET 0.4 0.6 0.8 Distance (microns) Fig. 8.3 Potential distribution within the Baliga-Pair Configuration: (VGS = 0V;V DS = 3000V). The voltage developed across the silicon power MOSFET can bemonitored by examining the potential at the floating electrode (E4). Asthe applied drain voltage increases, the potential at this electrode alsoincreases as shown in Fig. 8.4. The voltage at the floating electrodeincreases to 26.5 volts when the applied voltage to the drain of thecomposite switch reaches 3000 volts. Consequently, the maximum drainvoltage experienced by the silicon power MOSFET is maintained below30 volts for a composite switch capable of supporting 3000 volts. This isan important feature of the Baliga-Pair configuration because it allowsthe use of silicon power MOSFETs with relatively low breakdown
  • 230. 208 SILICON CARBIDE POWER DEVICESvoltages (< 50 volts). Such silicon power MOSFETs are commerciallyavailable with very low on-resistance. 1000 2000 3000 Drain Bias (Volts) Fig. 8.4 Voltage at the Drain of the Silicon MOSFET in the Baliga-Pair Configuration in the Blocking Mode.8.2.2 Baliga-Pair Simulations: Forward Conduction ModeCurrent flow through the Baliga-Pair configuration is obtained byapplication of a positive gate bias to the silicon power MOSFET. Whenthe gate bias is well above the threshold voltage of the silicon powerMOSFET, it can carry a high current density with very low on-statevoltage drop due to its low specific on-resistance. Under theseconditions, the voltage difference between the source and gate of thesilicon carbide MESFET becomes very small. Consequently, the channelof the silicon carbide MESFET remains un-depleted allowing currentflow with low on-resistance.
  • 231. The Baliga-Pair Configuration 209 The current distribution within the Baliga-Pair configuration isshown in Fig. 8.5 for the case of a gate bias of 10 volts and a drain biasof 1 volt. Only the upper portion of the silicon carbide MESFET isdisplayed in this figure because the current is uniformly distributedthrough the lower portion of the device. It can be seen that the currentflows via the channel of the silicon power MOSFET and becomesuniformly distributed in its drift region. The current is then constrictedthrough the channel of the silicon carbide MESFET before becominguniformly distributed within its drift region. Cell Pitch = 1.1 microas Source Gate • 0.2 n.-l 0.6 0.8 1.0 Distance (microns) Fig. 8.5 On-State Current Distribution within the Baliga-Pair Configuration. The transfer characteristic for the Baliga-Pair configuration wasobtained by increasing the gate bias applied to the silicon powerMOSFET while maintaining a bias of 1 volt at the drain of the siliconcarbide MESFET. From the transfer curve shown in Fig. 8.6, it can beseen that a gate bias of 10 volts is sufficient to operate the Baliga-Pairwith a low net on-resistance. At this gate bias, the current densityflowing through the structures was 570 A/cm2 corresponding to aspecific on-resistance of 1.9 mQ-cm2 The silicon carbide MESFET
  • 232. 210 SILICON CARBIDE POWER DEVICEScontributes about 90 percent of this on-resistance with the balancecontributed by the silicon power MOSFET. Baliga-Pair Configuration 6 • ^i- S 1 JJ / 1 5 ^ " «s J , o lH i * " ] K a 0> 1 Q 3 • •M a <u u S 2 • U i -o u > « 1 l , I © 1 n ) ! 5 10 15 20 Gate Bias (Volts) Fie. 8.6 Transfer Characteristics for the Baliea-Pair Confieuration.8.2.3 Baliga-Pair Simulations: Current Saturation ModeAs discussed earlier, the ability to limit the current flow by currentsaturation within a power switch is an attractive attribute from anapplications stand-point. The extension of current saturation to highvoltages is very desirable because this provides a broad safe-operating-area for the switching loci during circuit operation. These features wereanalyzed for the Baliga-Pair configuration by application of various gatebias voltages and examining the resulting output characteristics as shownin Fig. 8.7. It can be seen that the composite switch exhibits an excellentcurrent saturation capability to very high drain bias voltages with veryhigh output resistance until the gate bias voltage exceeds 9 volts. Beyond
  • 233. The Baliga-Pair Configuration 211this gate bias voltage, current compression is observed - a phenomenoncommonly observed in transistors at very high current densities". Notethat the current density has reached a magnitude of 2 x 104 A/cm2 at agate bias of 9 volts. Although such high current density can be a problemfrom a power dissipation point of view, these results demonstrate that theBaliga-Pair has a very broad safe-operating-area within which inductiveload switching can be performed. Baliga-Pair Configuration 3 €~ For ward urrent Density (104A/cn Gate Bias 15, 20 V ^ - ^ ^ C - - 2 ^^^^^^ 9V fi^ 8V 1 7V >w< 6V 5V oJ 0.5 1.0 1.5 2.0 2.5 0 Drain Bias (kV) Fig. 8.7 Output Characteristics for the Baliga-Pair Configuration.8.2.4 Baliga-Pair Simulations: Switching CharacteristicsThe switching performance of the Baliga-Pair configuration wasexamined under inductive load conditions. The composite switch wasfirst biased into its blocking state with a drain bias of 2000 volts bykeeping the gate bias of the silicon MOSFET at zero. The gate was thenbiased using a constant input current to charge the gate capacitance. Thismethod is commonly used for characterization of power MOSFETs12.
  • 234. 212 SILICON CARBIDE POWER DEVICESThe gate voltage at the silicon power MOSFET increases in response tothe stimulus, as shown in Fig. 8.8. When the gate voltage exceeds thethreshold voltage at time ti, the drain current begins to rise. Thesimulations were designed to maintain the drain current density at aconstant value once it reached a magnitude of 200 A/cm2. At this time t2,the drain voltage falls rapidly until time t3 resulting in a high dV/dt at theoutput terminals of the FETs. The plateau in the gate voltage until time t4is associated with the charging of the Miller capacitance of the siliconMOSFET. tlMJ 10V v wo 3 I -7 • VT = 4 V C3 o " VD = 2000 V • I > J F = 200 A/cm 2 V 3 u j I .... I 0.5 1.0 1.5 Time (Ms) Fig. 8.8 Switching Performance of the Baliga-Pair Configuration.
  • 235. The Baliga-Pair Configuration 213 During the switching event for turning on the Baliga-Pair, highpower dissipation occurs during the transition time (t2 - ti) for the draincurrent and the transition time (t3 - t2) for the drain voltage. Theswitching energy associated with these events is given by: £tf=0.5*Vo*/D*(f3-f1) [8.2]For the simulated case with VD = 2000 volts and JD = 200 A/cm2, thecalculated switching energy is 30 mJ/cm2. This would produce a powerdissipation of 30 W/cm2 at a typical operating frequency of 1 kHz. Incomparison, the on-state power dissipation is given by: P0n=RDSonsP*J2D [8-31For the simulated Baliga-Pair configuration with specific on-resistance of2 m£2-cm2, the conduction power loss is found to be 80 W/cm2. If theturn-off switching losses are assumed to be comparable to the turn-onpower loss computed above, the total power loss is 140 W/cm2, which isacceptable from the point of view of cooling the devices with availableheat sink technology. This demonstrates that the Baliga-Pair is capable ofproviding excellent switching performance for high voltage powersystems. It is also interesting to observe the behavior of the drain potentialof the silicon power MOSFET during the switching transient. As can beseen in Fig. 8.9, the drain voltage remains close to its value duringoperation in the blocking mode until time t2 and then reduces to the on-state voltage drop of the silicon power MOSFET. It is worth pointing outthat the drain voltage of the silicon power MOSFET ramps down duringthe entire time interval from t2 to t4 while the drain voltage on the siliconcarbide MESFET ramps down in a much shorter time interval from t2 tot3. Since most of the voltage is supported by the silicon carbideMESFET, this is a favorable outcome that results in smaller turn-offenergy and switching losses. In addition, the current flow through the gate of MESFET isshown in Fig. 8.9 during the switching transient. This current remains atapproximately a constant value during the time interval from t2 to t3when the drain voltage of the MESFET is ramping down. This indicatesthat the Miller and output capacitances of the MESFET are beingcharged through the gate electrode of the MESFET. This is responsiblefor the faster reduction of the drain voltage for the silicon carbideMESFET without being limited by the performance of the silicon
  • 236. 214 SILICON CARBIDE POWER DEVICESMOSFET. These observations indicate that the Baliga-Pair configurationhas an excellent switching behavior for power electronics applications. n *2 *3 *4 10V Ml 3 : ,—i 1 > • VT = 4 V BO • V D = 23.5 V "o !Z2 > os « s <» Q 1 "--4 V C3 1 H -a M a d3 u ^ . ! i v<^ . 1 0.5 1.0 1.5 Time (Ms) Fig. 8.9 Silicon Power MOSFET Drain Potential during Switching of the Baliga-Pair Configuration.8.2.5 Baliga-Pair Simulations: Fly-Back DiodeAs mentioned previously, the Baliga-Pair configuration contains aninherent fly-back rectifier that can be useful in H-bridge and other powerelectronic circuit applications. The performance of this rectifier was
  • 237. The Baliga-Pair Configuration 215examined by doing simulations with a negative bias applied to the drainterminal of the silicon carbide MESFET while connecting the gate of thesilicon power MOSFET to the source terminal. The resulting currentflow path is shown in Fig. 8.10 for the case of a drain bias of -1 volt. Itcan be seen that the current flows between the drain of the silicon carbideMESFET and its gate electrode. No current is observed through the bodydiode of the silicon power MOSFET. This is favorable from the point ofview of avoiding the reverse recovery of the silicon MOSFETs bodydiode13. The observed current path through the Schottky gate contact ofthe silicon carbide MESFET ensures that the fly-back rectifier in theBaliga-Pair operates in the unipolar mode. Cell Pitch =1.1 microns Source Gate Silicon Floating | MOSFET Electrode 4H-SiC MESFET Distance (microns) Fig. 8.10 Current Distribution within the Baliga-Pair Configuration with Negative Bias applied to the Drain Terminal. The current conduction characteristics of the fly-back diode areof interest because they dictate the power losses when the rectifier iscarrying the load current in an H-bridge circuit. The current conductioncapability of the inherent fly-back rectifier in the Baliga-Pair
  • 238. 216 SILICON CARBIDE POWER DEVICESconfiguration was determined by performing simulations with a negativevoltage applied to the drain of the silicon carbide MESFET. The gate ofthe silicon MOSFET was held at zero volts during these simulations. Theresulting characteristic is shown in Fig. 8.11 at room temperature.Excellent characteristics are observed with an on-state voltage drop ofonly 0.7 volts. This indicates that a larger work-function could be usedfor the gate of the silicon carbide MESFET to reduce its leakage currentif necessary. Baliga-Pair Configuration ~———-— /-* -6 < -7 -w JF = 100 A/cm2 e -X v u u 3 -t U & -10 ] « l* Q -11 DC -12 O J -13 Cell Pitch = 1.1 microns -14 Work Function = 4.5 eV -15 -2.5 -2.0 -1.5 -1.0 -0.5 Drain Bias (Volts) Fig. 8.11 Forward Characteristics of the Fly-Back Diode in the Baliga-Pair Configuration. The simulations discussed above indicate that the Baliga-Pairconfiguration provides an excellent power switch for high voltage powersystem applications. In terms of packaging, the two transistors within theBaliga-Pair configuration replace the IGBT and the fly-back rectifierresulting in a similar level of complexity and cost.
  • 239. The Baliga-Pair Configuration 2178.3 Baliga-Pair Configuration: Experimental ResultsThe attractive features of the Baliga-Pair configuration have beenacknowledged by several research groups. The same configuration wasreferred to as the Cascode arrangement in 19996 with theacknowledgement that it was originally proposed and published in 19967.The switching behavior of the Cascode arrangement was reported14 byusing a planar silicon carbide JFET structure with a 50 volt silicon powerMOSFET. The authors compared the performance of silicon carbideJFETs with the gate formed using the buried sub-surface P+ region with aJFET fabricated using a gate formed on the upper surface (similar to thestructure discussed in the previous chapter). It was found that the buriedgate device had inferior switching performance due to the high resistancein the buried P+ regions. The turn-off time was limited by the R-Ccharging time-constant for the buried P+ regions. In addition, the slowresponse of this JFET structure resulted in the silicon power MOSFETbeing driven into avalanche breakdown. These problems were notobserved for the surface gate device. In a subsequent paper15, the authorsstated "SiCED favors a combination of a silicon switch and a vertical,normally-on SiC junction field effect transistor". Their analysisconcluded that the Baliga-Pair configuration is useful upto at least the 4.5kV range. The excellent performance of the Baliga-Pair circuit has alsobeen confirmed by using numerical simulations and compared with theperformance of a silicon carbide MOSFET structure16. The authors, whocalled this a Cascade Configuration, found that the turn-off time for theBaliga-pair configuration was half that for the silicon carbide MOSFETdue to the smaller Miller capacitance.8.4 SummaryIt has been demonstrated that the Baliga-pair configuration provides anideal power switch for high voltage power system applications. It can beused in the same manner as IGBTs packaged with anti-parallel rectifierswithout alterations of the gate control techniques. The packaging of thiscombination of two FETs is similar to that for the two chips currentlyused because the Baliga-Pair contains an inherent fly-back rectifier. Untilthe development of reliable silicon carbide power MOSFETs with lowspecific on-resistance, the Baliga-Pair offers a commercially viable nearterm option for high power electronic systems.
  • 240. 218 SILICON CARBIDE POWER DEVICESReferences1 B.J. Baliga, The Evolution of MOS-Bipolar Power Semiconductor Technology", Proceedings of the IEEE, Vol. 74, pp. 409-418, 1988. 2 B. J. Baliga, "Critical Nature of Oxide/Interface Quality for SiC PowerDevices", Microelectronics Engineering, Vol. 28, pp. 177-184, 1995.3 B. J. Baliga, "Silicon Carbide Switching Device with RectifyingGate", U. S. Patent 5,396,085, Issued March 7, 1995.4 S. Darlington, "Semiconductor Signal Translating Device", U. S.Patent 2,663,806, Issued December 22, 1953.5 P. M. McLarty, Private Communication, 1995.6 P. Friedrichs, et al, "Static and Dynamic Characteristics of 4H-SiCJFETs Designed for Different Blocking Categories", Silicon Carbide andRelated Materials - 1999, Material Science Forum, Vol. 338-342, pp. 1243-1246, 2000.7 B. J. Baliga, "Power Semiconductor Devices", pp. 418-420, PWSPublishing Company, 1996.8 B. J. Baliga, "Prospects for Development of SiC Power Devices",Silicon Carbide and Related Materials - 1995, Institute of PhysicsConference Series, Vol. 142, pp. 1-6, 1996.9 B. J. Baliga, "Power Semiconductor Devices for Variable-FrequencyDrives", Proceeding of the IEEE, Vol. 82, pp. 1112-1122, 1994.10 B. J. Baliga and D. Alok, "Paradigm Shift in Planar Power MOSFETTechnology", Power Electronics Technology Magazine, pg. 24-32,November 2003.11 B. J. Baliga, "Silicon RF Power MOSFETs", World ScientificPublishers, 2005.12 B. J. Baliga, "Power Semiconductor Devices", pp. 387-391, PWSPublishing Company, 1996.13 B. J. Baliga and J. P. Walden, "Improving the Reverse Recovery ofPower MOSFET Integral Diodes by Electron Irradiation", Solid StateElectronics, Vol. 26, pp. 1133-1141, 1983.14 H. Mitlehner, et al, "Dynamic Characteristics of High Voltage 4H-SiC Vertical JFETs", IEEE International Symposium on PowerSemiconductor Devices and ICs, Abstract 11.1, pp. 339-342, 1999.15 P. Friedrichs, et al, "Application-Oriented Unipolar Switching SiCDevices", Silicon Carbide and Related Materials - 2001, MaterialScience Forum, Vol. 389-393, pp. 1185-1190, 2002.16 A. Mihaila, et al, "Static and Dynamic Behavior of SiC JFET/SiMOSFET Cascade Configuration for High-Performance Power
  • 241. The Baliga-Pair Configuration 219Switches", Silicon Carbide and Related Materials - 2001, MaterialScience Forum, Vol. 389-393, pp. 1239-1242, 2002.
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  • 243. Chapter 9 Planar Power MOSFETsThe planar power MOSFET was the first commercially successfulunipolar switch developed using silicon technology1 once the issuesrelated to the metal-oxide-semiconductor interface had been resolved forCMOS technology. In order to reduce cost, the channel in these deviceswas created by the double diffusion (or D-MOS) process. In the DMOSprocess, the P-base and N+ source regions are formed by ionimplantations masked by a common edge defined by a refractorypolysilicon gate electrode. A drive-in cycle is used after each ionimplantation step to move the P-N junction in the lateral direction underthe gate electrode. The separation between the N+/P-base junction andthe P-base/N-drift junction under the gate electrode defines the channel.Consequently, the channel length can be reduced to sub-microndimensions without the need for high resolution lithography. Thisapproach served the industry quite well from the 1970s into the 1990swith planar power MOSFETs still available for power electronicapplications. In the 1990s, the industry borrowed the trench technologyoriginally developed for DRAMs to introduce the UMOSFET structurefor commercial applications2. This was important for the reduction of thechannel and JFET components in the planar MOSFET structure designedfor lower (< 30 volts) voltage applications. This UMOSFET structure hasalso been explored in silicon carbide as described in a subsequentchapter. In silicon power MOSFETs, the on-resistance becomesdominated by the resistance of the drift region when the breakdownvoltage exceeds 200 volts. At high breakdown voltages, the specific on-resistance for these devices becomes greater than 10"2 Ohm-cm2, asshown in Fig. 3.6, leading to an on-state voltage drop of more than 1 voltat a typical on-state current density of 100 A/cm2. For this reason, theInsulated Gate Bipolar Transistor (IGBT) was developed in the 1980s toserve medium and high power systems2. The superior performance of the 221
  • 244. 222 SILICON CARBIDE POWER DEVICESIGBT in high voltage applications relegated the silicon MOSFETs toapplications with operating voltages below 100 volts. Novel siliconstructures that utilize the charge-coupling concept have allowedextending the breakdown voltage of power MOSFETs to the 600 voltrange3. However, their specific on-resistance is still quite large limitingtheir use to high operating frequencies where switching losses dominate. In principle, the much lower resistance of the drift region insilicon carbide should enable development of power MOSFETs withvery high breakdown voltages. These devices offer not only fastswitching speed but also superior safe operating area when compared tohigh voltage silicon IGBTs. This allows reduction of both the switchingloss and conduction loss components in power circuits4. Unfortunately,the power MOSFET structures developed in silicon cannot be directlyutilized to form high performance silicon carbide devices. Firstly, thelack of significant diffusion of dopants in silicon carbide prevents the useof the silicon DMOS process. Secondly, a high electric field occurs in thegate oxide of the silicon carbide MOSFET exceeding its rupture strengthleading to catastrophic failure of devices in the blocking mode at highvoltages. Thirdly, when compared with silicon, the smaller band offsetbetween the conduction band of silicon carbide and silicon dioxide canproduce injection of hot carriers into the oxide leading to instabilityduring operation. In addition, the quality of the oxide-semiconductorinterface for silicon carbide must be improved to allow good control overthe threshold voltage and the channel mobility. This chapter begins with a review of the basic principles ofoperation of the planar MOSFET structure. A planar MOSFET structureformed by staggering the ion implantation of the P-base and N+ sourceregions to create the channel is then described. Next, the problem ofexacerbation of reach-through breakdown in silicon carbide isconsidered. Based upon fundamental considerations, the differencebetween the threshold voltage for silicon and silicon carbide structures isanalyzed. The relatively high doping concentrations and large channellengths required to prevent reach-through are shown to be seriouslimitations to obtaining low specific on-resistance in these devices. Inaddition, the much larger electric field in silicon carbide is shown to leadto a high electric field in the gate oxide. Structures designed to reduce theelectric field at the gate oxide by using a shielding region are thereforeessential to realization of practical silicon carbide MOSFETs even afterthe MOS interface quality is improved. These structures are describedand analyzed in the next chapter. The results of the analysis of the planar
  • 245. Planar Power MOSFETs 223silicon carbide MOSFET structures by using two-dimensional numericalsimulations are described in this chapter followed by the description ofexperimental results on relevant structures to define the state of thedevelopment effort on these devices.9.1 Planar Power MOSFET Structure N+ Source Implant Edge P-Base Implant Edge P-BASE N-DRIFT REGION N* SUBSTRATE W7//////////////////////A DRAIN Fig. 9.1 The Planar Power MOSFET Structure.The basic structure of the planar power MOSFET is shown in Fig. 9.1together with the location of the ion implantation edges. In recognition ofthe low diffusion coefficients for dopants in silicon carbide, it wasproposed5 that the P-base and N+ source ion implantations be staggeredby using photoresist masks rather that be defined by the gate edge. It wasalso suggested that the P-base region be first amorphized to obtain amore uniform dopant distribution to suppress reach-through. Thisapproach with staggered P-base and N+ source implants wassubsequently taken by several groups to fabricate high voltage devices .These devices have been called DIMOSFETs because of the Double-Implant process used for their fabrication. The measured performance ofthese structures is discussed at the end of the chapter.
  • 246. 224 SILICON CARBIDE POWER DEVICES9.1.1 Planar Power MOSFET Structure: Blocking CharacteristicsIn the forward blocking mode of the planar power MOSFET, the voltageis supported by a depletion region formed on both sides of the P-base/N-drift junction. The maximum blocking voltage can be determined by theelectric field at this junction becoming equal to the critical electric fieldfor breakdown if the parasitic N+/P/N bipolar transistor is completelysuppressed. This suppression is accomplished by short-circuiting the N*source and P-base regions using the source metal as shown on the upperleft hand side of the cross-section. However, a large leakage current canoccur when the depletion region in the P-base region reaches-through tothe N+ source region. The doping concentration and thickness of the P-base region must be designed to prevent the reach-through phenomenonfrom limiting the breakdown voltage. N+ P-Base N-Drift N+ Fig. 9.2 Reach-Through in a Power MOSFET Structure. The applied drain voltage is supported by the N-drift region andthe P-base region with a triangular electric field distribution as shown inFig. 9.2 if the doping is uniform on both sides. The maximum electricfield occurs at the P-base/N-drift junction. The depletion width on the P-base side is related to the maximum electric field by:
  • 247. Planar Power MOSFETs 225 e,E [9.1] s WB =• " & Awhere NA is the doping concentration in the P-base region. The minimumP-base thickness required to prevent reach-though limited breakdown canbe obtained by assuming that the maximum electric field at the P-base/N-drift junction reaches the critical electric field for breakdown when the P-base region is completely depleted: £ t _ s^c [9.2]where Ec is the critical electric field for breakdown in the semiconductor. 1U 1 4H-SIC 1 I a. I Si icon 0.1 10" 10" 1018 P-Base Doping Concentration ( c m 3 ) Fig. 9.3 Comparison of Minimum P-Base Thickness to prevent Reach-Through Breakdown in 4H-SiC and Silicon. The calculated minimum P-base thickness for 4H-SiC powerMOSFETs is compared with that for silicon in Fig. 9.3. At any given P-base doping concentration, the thickness for 4H-SiC is about six timeslarger than for silicon. This implies that the minimum channel lengthrequired for silicon carbide devices is much larger than for silicondevices resulting in a big increase in the on-resistance. The enhancement
  • 248. 226 SILICON CARBIDE POWER DEVICESof the on-resistance is compounded by the lower channel inversion layermobility observed for silicon carbide. The minimum thickness of the P-base region required to preventreach-through breakdown decreases with increasing dopingconcentration as shown in Fig. 9.3. The typical P-base dopingconcentration for silicon power MOSFETs is 1 x 1017 cm"3 to obtain athreshold voltage between 1 and 2 volts for a gate oxide thickness of 500to 1000 angstroms. At this doping level, the P-base thickness can bereduced to 0.5 microns without reach-through limiting the breakdownvoltage. In contrast, for 4H-SiC, it is necessary to increase the P-basedoping concentration to above 4 x 1017 cm"3 to prevent reach-throughwith a 0.5 micron P-base thickness. This higher doping concentrationincreases the threshold voltage as discussed in the next section. The maximum blocking voltage capability of the powerMOSFET structure is determined by the drift region dopingconcentration and thickness as already discussed in chapter 3. However,in the power MOSFET structure, a high electric field also develops in thegate oxide under forward blocking conditions. The electric fielddeveloped in the oxide is related to the electric field in the underlyingsemiconductor by Gausses Law: c Semi ^ Oxide •ESemi [9.3] V £Oxide Jwhere eSemi and e0xide are the dielectric constants of the semiconductorand the oxide and ESemi is the electric field in the semiconductor. In thecase of both silicon and silicon carbide, the electric field in the oxide isabout 3 times larger than in the semiconductor. Since the maximumelectric field in the silicon drift region remains below 3 x 105 V/cm, theelectric field in the oxide does not exceed its reliability limit of about 3 x106 V/cm. However, for 4H-SiC, the electric field in the oxide reaches avalue of 9 x 106 V/cm when the field in the semiconductor reaches itsbreakdown strength. This value not only exceeds the reliability limit butcan cause rupture of the oxide leading to catastrophic breakdown. It istherefore important to monitor the electric field in the gate oxide whendesigning and modeling the silicon carbide MOSFET structures. Novelstructures7 that shield the gate oxide from high electric field have alsobeen proposed and demonstrated to resolve this problem. Thesestructures will be discussed in the next chapter.
  • 249. Planar Power MOSFETs 2279.1.2 Planar Power MOSFET Structure: Forward Conduction w, SOURCE GATE . g?ggl I E V////////////////M^ & 1 R, P-BASE REGION fc •-flUST R» N-DffffT REGION N* SUBSTRATE ^Sli v;;/////////////^^^^^ DRAIN Fig. 9.4 Current Flow Path in the Planar 4H-SiC Power MOSFET.Current flow between the drain and source can be induced by creating aninversion layer channel on the surface of the P-base region. The currentpath is illustrated in Fig. 9.4 by the dotted area. The current flowsthrough the inversion layer channel formed due to the applied gate biasinto the JFET region via the accumulation layer formed above it underthe gate oxide. It then spreads into the N-drift region at a 45 degree angleand becomes uniform through the rest of the structure. The total on-resistance for the planar power MOSFET structure is determined by theresistance of these components in the current path: Ron.v=RcH+RA+RjFEr+RD+R! ubs [9.4]where RCH is the channel resistance, RA is the accumulation regionresistance, RJFET is the resistance of the JFET region, RD is the resistanceof the drift region after taking into account current spreading from theJFET region, and Rsubs is the resistance of the N+ substrate. Theseresistances can be analytically modeled by using the current flow pattern
  • 250. 228 SILICON CARBIDE POWER DEVICESindicated by the shaded regions in Fig. 9.4. In this figure, the depletionregion boundaries have also been shown using dashed lines. The specific channel resistance is given by: R —(w)— [95] Minvcox(vG-vT)where LCH is the channel length as shown in Fig. 9.4, fxinv is the mobilityfor electrons in the inversion layer channel, Cox is the specificcapacitance of the gate oxide, VG is the applied gate bias, and VT is thethreshold voltage. The specific capacitance can be obtained using: C„=7=- [9.6]where eox is the dielectric constant for the gate oxide and tox is itsthickness. The specific resistance of the accumulation region is given by: R K(W,-WP)p — w pjr_ [97] MaC„(Vo-VT)where (ia is the mobility for electrons in the accumulation layer, Cox is thespecific capacitance of the gate oxide, VG is the applied gate bias, and VTis the threshold voltage. The factor K is used to account for two-dimensional current spreading from the channel into the JFET regionwith a typical value of 0.6 for silicon devices. In this equation, WP is thezero-bias depletion width at the P-base/N-drift junction. It can bedetermined using: w ^SVML [9S]where the built-in potential VbiP for the P-N junction is typically 3.3 voltsfor 4H-SiC. The specific JFET region resistance is given by: ( « ^ KJFET ~ PD •*/> [9.9] Wj-WP)where tp is the depth of the P-base region.
  • 251. Planar Power MOSFETs 229 The drift region spreading resistance can be obtained by using: RD=PD.p.n + pD.{t-s-WP) [9.10] W -Wwhere t is the thickness of the drift region below the P-base region and sis the width of the P-base region. The contribution to the resistance from the N+ substrate is givenby: subs rsubs subs [9.11]where psut,s and tsubs are the resistivity and thickness of the substrate,respectively. A typical value for this contribution is 4 x 10" Q-cm 4.0 4H-SiC Planar MOSFET v Channel Mobility = 100 cm2/V.s 3.0 _ _ ^ - ^ ~ ^ 2.0 a * H Drift O w Channel 1.0 B-J JFET -•—I Substrate Accumulation 1.0 2.0 Channel Length (microns) Fig. 9.5 On-Resistance Components for a 4H-SiC Planar MOSFET. The specific on-resistances of 4H-SiC planar MOSFETs with adrift region doping concentration of 1 x 1016 cm"3 and thickness of 20microns were modeled using the above analytical expressions. In all thedevices, a gate oxide thickness of 0.1 microns was used. The dimensiona in the structure shown in Fig. 9.4 was kept at 1 micron. This valuecan be achieved using 0.5 micron design rules. The accumulationmobility was assumed to be twice the inversion layer mobility and a K-factor of 0.1 was used to provide correlation with the simulations. The P-
  • 252. 230 SILICON CARBIDE POWER DEVICESbase was assumed to have a depth of 1 micron and the effective gatedrive voltage (VG - VT) was assumed to be 20 volts. The variouscomponents of the on-resistance are shown in Fig. 9.5 when a channelinversion layer mobility of 100 cm2/Vs was used. This magnitude ofinversion layer mobility has been experimentally observed8. It can beseen that the drift region resistance is dominant under these conditionseven for channel lengths of 2 microns. At a channel length of 1 micron, atotal specific on-resistance of 2.7 miJ-cm2 is obtained, which is aboutthree times the ideal specific on-resistance. Although this is a good valuefor a device with the drift regions parameters used for the modeling, thebreakdown voltage of the structure was determined to be well below itsideal parallel-plane case (3000 volts), as shown later under devicesimulations, due to the reach-through problem. 8.0 1 1 I 1 4H-SiC Planar MOSFET /*—N 7.0 s u 1 Channel Mobility = 100 cm2/V.s 1 6.0 £, V V 5.0 U B sta 4.0 •J7S LCH = 2 nm V fie n-R 3.0 ^ ^ ^ - • ^ • • • • f » • » " ~4 • »-< »-» • •- O 2.0 .OH - , L • H m u V 1.0 £ 0.6 0.8 1.0 1.2 1.4 1.6