Introduction to VHDL

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A quick and high-level overview of VHDL design. Simple and full examples are included for the concepts that are addressed. Prepared and presented to the UWASIC Design Team in Fall of '08.

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Introduction to VHDL

  1. 1. Introduction to VHDL Fall 2008 Jason Lor jlor@engmail.uwaterloo.ca
  2. 2. Outline • Brief Overview of VHDL • Structural Elements of VHDL • Entity • Architecture • Signals • Data Types & Operators in VHDL • Assignment Execution • Concurrent • Sequential (Process)
  3. 3. Brief Overview of VHDL • VHDL ... stands for Very High Speed Integrated Circuit Hardware Description Language ... can be translated into an actual hardware implementation ... allows complex digital circuits to be easily created In VHDL, strong understanding of your code is more important than syntax & style.
  4. 4. Structural Elements • Entity • Interface • Example: Ports, I/O • Architecture • Implementation • Behaviour • Function
  5. 5. Entity • Describes the interactions of a module entity GarageDoorOpener is entity BlockName is port( port( i_button : in std_logic; clock_gen : in std_logic; i_sensor : in std_logic; input1 : inout boolean; i_stop : in std_logic; input2 : in std_integer; o_active : out std_logic; output : out string; o_direction : out std_logic output1 : buffer character ); ); end entity; end entity; • Port is a keyword that describes the data flow • PortName : Mode DataType • ‘;’ is used to separate elements, not for terminating the statement
  6. 6. Entity • Clock Generator 1 Periodic Function 0 Rising Edge Falling Edge
  7. 7. Architecture • Specifies the implementation of the module • One entity can have several architectures architecture ArchitectureName of EntityName is begin a AND b => c; end ArchitectureName; • Entity ports are available as signals within the architecture
  8. 8. Signals • are intermediary ‘ports’ within the architecture • represents wires and storage elements • statements are concurrent architecture rtl of GarageDoorOpener is signal stop_door : std_logic; signal SignalName : datatype begin <architecture code here> end rtl;
  9. 9. Data Types • similar to programming, all signals and ports should have a data type • all signals and port must have a data type Data Types Boolean Integer std_logic_vector Bit Real std_logic Character type
  10. 10. Data Types std_logic_vector is an array of std_logic variables std_logic U : uninitialized X : unknown 0 : logic 0 1 : logic 1 Z : high impedance W : weak signal (either 1 or 0) L : weak signal (leaning 0) H : weak signal (leaning 1) - : don’t care
  11. 11. Data Types • ‘type’ enumerable type • ... is an array of data types and values similar to std_logic_vector & std_logic • ... can be defined by you type TrafficLightState is (INIT, RED, REDYELLOW,YELLOW, GREEN); type LightSwitchState is (‘0’, ‘1’); type TypeName is (datatype, variablename);
  12. 12. Typical Operators Logical Operators Relational Operators AND NOR NOT = Equal /= Not Equal OR NAND < Less than XOR XNOR > Greater than Mathematical Operators + Addition - Subtraction * Multiplication / Division
  13. 13. Assignment Execution • Concurrent/Continously or Combinational Logic • To give a signal a concurrent assignment SignalName <= expression; • Once your VHDL files compile, the compiler will assign your specifications to hardware components which operate in parallel with one another • Sequential Logic • Sequential logic is like programming in that your code executes in sequence • You can use conditional assignments like ‘if’, ‘case’ etc.
  14. 14. Assignment Execution • In order to utilize sequential logic you have to use process statements • There are two types of process statements, inside processes and outside processes • ‘Process’ Statements • ... specifies a block of sequentially executed statements • ... run concurrently with each other • ... allows the use of if, else if, case, when, with, select statements
  15. 15. Assignment Execution library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; Entity Architecture continued, Processes, Cases and If/elses entity TrafficLight is port( process(i_clock) i_clock : in std_logic; begin i_pedestrian : out std_logic; if rising_edge(traffic_clock) then if i_pedestrian = ‘1’ then o_red : out std_logic; current_state = YELLOW; o_yellow : out std_logic; else o_green : out std_logic; case current_state is ); when RED => end entity; current_state <= GREEN; Architecture, Signal, Type when GREEN => architecture RTL of TrafficLight is current_state <= RED; type state_t is (RED, YELLOW, GREEN); when YELLOW => current_state <= RED; signal current_state : state_t; end case; end if; begin end if; o_red <= ‘1’ when (current_state = RED) else ‘0’; end process; o_yellow <= ‘1’ when (current_state = YELLOW) else ‘0’; end rtl; o_green <= ‘1’ when (current_state = GREEN) else ‘0’;

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