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Dmap Announces Development Of Do 254 Dal A Complex Semiconductor Ip, Fully Verified With Mentor Graphics Questa® Functional Verification Platform
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Dmap Announces Development Of Do 254 Dal A Complex Semiconductor Ip, Fully Verified With Mentor Graphics Questa® Functional Verification Platform

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DMAP Announces Development of DO-254 DAL A Complex Semiconductor IP, Fully Verified with Mentor Graphics Questa® Functional Verification Platform

DMAP Announces Development of DO-254 DAL A Complex Semiconductor IP, Fully Verified with Mentor Graphics Questa® Functional Verification Platform

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  • 1. DMAP Announces Development of DO-254 DAL A Complex Semiconductor IP, Fully Verified with Mentor Graphics Questa® Functional Verification PlatformToulouse – France, November 28th, 2011 –DMAP, a company focused on high reliability semiconductor applications and producing DO-254 compliant IP, has made availableto the market PCI Express and Ethernet (Gigabit, 10G) IP for DO-254 applications that has been verified using SystemVerilog andAssertion Based Verification (ABV) in an OVM environment. Adherence to DO-254 compliance during development, and verifiedusing advanced verification methods supported by Mentor Graphics industry-leading Questa® functional verification platform,ensures thorough testing of these complex IP devices.DO-254 explicitly requires functional coverage, a verification approach that ensures all requirements have been covered in thedesigned hardware. The DO-254 standard states the following: “Evidence is provided that the hardware implementation meets therequirements” [DO-254 6.2.1-1]. Regardless of the level of design (LRU, board, device, IP) and design assurance level (DAL) of theitem, functional coverage is the fundamental metric of every ‘safe’ design flow.Supplementing a requirements-driven approach to verification and functional coverage, HDL code coverage is also commonly usedin DO-254 programs. While not explicitly mentioned in DO-254, code coverage is often used in support of elemental analysis, anadvanced verification method described in DO-254 Appendix B to ensure that all the design elements have been exercised duringverification. Newer regulatory policy has mandated the use of code coverage for DAL A and B digital hardware projects.Specifically, the recent EASA CEH memo states”…an HDL code coverage measurement is an acceptable means to assess theway the HDL code has been exercised during device functional verification by simulation.” [EASA CM-SWCEH-001 8.4.2.1].With the Questa functional verification platform from Mentor Graphics, DMAP’s verification team has been able to reach 100%coverage on both hardware requirements (i.e., functional coverage) and HDL code (i.e., code coverage) in an automated way.Quite straightforward, both functional and code goals are extracted from the document which describes the verificationprocedures (HVCP) or verification‘s code (SV) then Questa® simulator is able to automatically answer the question: Arewe done?“DMAP’s team is pioneering advanced verification techniques on DO-254 compliant IP” stated Michelle Lange, DO-254 ProgramManager at Mentor Graphics. “It’s good to see these methods – which are used extensively in every other industry because theyoffer more efficient and higher quality results – being used now in an industry where verification effectiveness is so crucial. DMAP,with their use of Questa and advanced methods, is demonstrating their leadership and understanding of the value of these methodsin support of safety-critical design.”“By using more modern verification techniques such as SystemVerilog, formal methods, ABV, and Bus Functional Models (BFMs),we are now able to reach all DO-254 goals on very high complex IP or FPGA designs in a short amount time and for a competitivecost.” said James Bezamat, CEO and DO-254 evangelist at DMAP.Already available for DO-254 DAL A designs, our Generation One PCI Express Endpoint and 10/100/100 Ethernet MACsemiconductor IP products can be customized on request to match your needs. The DMAP’s product list also includes ARINC429and CAN bus interface.Contact DMAP at contact@dmap.fr to get your evaluation copy.About DMAPDMAP is a company focused on high reliability semiconductor application domains. DMAP was founded in 2009 by two highlyskilled engineers in the semiconductor area. With more than 40 years of experience, we are able to combine IP and SoCdevelopment for ASIC and FPGA target with high reliability methods provided by the DO-254 guidance. High reliable domains suchas aeronautic, medical, defense and space, like other mass markets are sensitive to time-to-market constraints and growing systemcomplexity. Thats why we offer IP vendors the opportunity to address new markets and the high reliability sub-contractorcommunity the opportunity to buy DO-254 ready IP to speed up their development process. For more information, please email:contact@dmap.fr or visit the company’s website at www.dmap.fr.About Mentor GraphicsMentor Graphics Corporation is a world leader in electronic hardware and software design solutions, providing products, consultingservices and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Establishedin 1981, the company reported revenues in the last fiscal year of about $915 million. Corporate headquarters are located at 8005S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. World Wide Web site: http://www.mentor.com.

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