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Lect8 dram sram
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Lect8 dram sram

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Lect8 dram sram Lect8 dram sram Presentation Transcript

  • Internal memory in computer
  • Internal memory of computer•Physical structure of internal memory located on main boardDRAMModulesOnDIMMslotsMother board4 - 8GBNorth breadgeDRAMcontrollerCAS,RASControlsignals forsinchranousCAS-colum access strobe,RAS- row access strobeDRAMinterfaseDouble Memorycannels64bits DBCPU corechipL1Cach32-64KBL2Cach256KBL3cach1-8MBCPU coreL1Cach32-64KBCPU corechipProcessorchipL2Cach256KBCPU core
  • DRAM and SRAM memory types•Internal memory of computer consist of RAM (random access memory) andCache memory•RAM is the array of multiply cells each saved 8 bits information•Each bit of information is saved in one memory elements•Depending on realisation scheme there are two types of of memory elements :statical RAM(SRAM) and dynamic RAM(DRAM)•Usually DRAM and SRAM elements can be used in following modes: writenew state(“1”or “0”),read current state and save of the last state•In DRAM schemes logic “1” or “0” are saved as charged or discharged statesof capacity integrated in this scheme•SRAM scheme saves logic “1” and “0” by trigger (flip-flop) that has twostatical states(”1” or “0”)•Current state of SRAM didn‟t changed after read operation and this state willbe saved in a large time when SRAM works in saving mode•after reading “1” state of DRAM is changed to “0” and “1” state did not besaved for large time duration because value of charge in capacity willdecreased by existing internal currents
  • Scheme of DRAM memory element• Commom scheme of 1bit DRAM element (a) and changing of charged state inDRAM by write /read operations (b)b)WR”1”Chargingof C“1”RD”1”Dischargingof C“0”Vct+-CcondensatorAddress linedata lineTransistorJFTsrcdstgateRDWRa)Not connected
  • Scheme of SRAM memory element• 1 bit SRAM schemeAddress lineFead backT1T2T3 T4T5T6data lines for read /writeGates of triggerWr”1”Wr”0”invers out /in of triggerWrie /read „0“Direct out /in of triggerWrie /read „1“
  • Internal structure of DRAM chipsRow/Columnaddress code n bitsMemoryarray..Data busWrite buffer andamplifierColumn selectsignalECC blockRAS (Row Access Strobe)Row selectsignalRead buffer andamplifierControl circuits,timersRow and columnaddressBuffers and decodersRefreshcircuits,counterCAS(Column AccessStrobe)Memorymatrixm-1Memorymatrix0
  • The memory array structure• memory array consist of some matrixes each saved onlysame bits of all memory cells• Number of matrixes(0-(m-1)) is defined by number ofbits in one memory cell for a given structure• Internal structure of each matrix consist of some rowsand columns• Full row readed from memory is saved in data buffer thatcan be realised using SRAM elements• Content of needed cell can be out from this data buffer• For restoring (refreshing) of DRAM cells full row savedin data buffer can be writed to memory at given address
  • Regeneration of information ,error checking andcorrection in DRAM chips• For restoring of „‟1‟‟- s that could be saved in DRAM at large of timeis used special circuits that named as regeneration(refresh) blocks• regeneration of DRAM memory is implemented at special refrreshcycles• At one refresh cycle may be implemented regeneration of few 1000memory rowes• The number of memory rowes (1K/2K/4K) refreshed in each cycle isdefined by special counter that included in refresh block• For checking of information write and read correction in DRAM isused ECC (ECC- Error Checking and Correction) block thatprovides to detect some of errors and their correction• The ECC technology replaces the parity control early used inDRAM memory
  • memory address signals• for memory access operation used memory address code that consist of two parts:row address and column address• By row and column addresses can be separatly selected corresponding row andcolumn in memory matrixes for accessing to corresponding memory cell• In memory accessing process at first must be selected row then correspondingcolumn in this row• Incerting the row and column addresses are accompanied by special control signalsthat transfered from DRAM controller and named as RAS (Row Access Strobe) andCAS (Column Access Strobe).These signals enable to transfer row and columnaddresses into memory• At first must be transferred RAS signal and following row address. After can betransferred CAS signal and column addresses to memory modules.• Time duration betweeen two nealy (sequentially) RAS signals defines the DRAMaccess time• For transfering row and column address codes with n bits from DRAM controller toDRAM chips is used memory address bus• Received row and column address codes are saved in own address buffers and lateris transferred from this buffers to corresponding address decoders existing in DRAMchips• The row and column address decoders convert these address codes to certinecontrol signals that select corresponding row and column in all memory matrises inparallel.
  • The internal structure of memory array• Selected on all matrixes rows and columns with samenumber define needably memory cell in DRAM chip• For this row and columns of all matrixes are connectedto corresponding outs of row and column addressdecoders• The number of rowes and columnes in each memorymatrixes are defined as number of outputs of eachdecoders and equals to 2n• The size of each matrix defined as 2n x 2n =22n• Space of memory is defined as 22n x m bits, where m=1/4/8 is the number of bits in each memory cell ornumber of matrix in used structure of memory array
  • Data and address buffer blocks in DRAM chip• The data codes that read or write to DRAM must be passed fromspecial read/write amplifies.• These amplifies are used for electrical (power) and logicalformation of bits in data codes .• For temporary saving read /write codes are used special databuffers that provide to decrease DRAM access time because nextaccess operation may be begined befor termination previous one• Similary, address buffers existing in DRAM chips provide toincrease frequance of RAS and CAS signals