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  • 1. www.fairchildsemi.comLM555/NE555/SA555Single TimerFeatures Description• High Current Drive Capability (200mA) The LM555/NE555/SA555 is a highly stable controller• Adjustable Duty Cycle capable of producing accurate timing pulses. With a• Temperature Stability of 0.005%/°C monostable operation, the time delay is controlled by one• Timing From µSec to Hours external resistor and one capacitor. With an astable• Turn off Time Less Than 2µSec operation, the frequency and duty cycle are accurately controlled by two external resistors and one capacitor.Applications 8-DIP• Precision Timing• Pulse Generation• Time Delay Generation 1• Sequential Timing 8-SOP 1Internal Block Diagram R R R GND 1 8 Vcc Comp. Discharging Tr. Trigger 2 7 Discharge OutPut Output 3 Stage F/F 6 Threshold Comp. Control Reset 4 5 Vref Voltage Rev. 1.0.3©2002 Fairchild Semiconductor Corporation
  • 2. LM555/NE555/SA555Absolute Maximum Ratings (TA = 25°C) 25° Parameter Symbol Value Unit Supply Voltage VCC 16 V Lead Temperature (Soldering 10sec) TLEAD 300 °C Power Dissipation PD 600 mW Operating Temperature Range LM555/NE555 TOPR 0 ~ +70 °C SA555 -40 ~ +85 Storage Temperature Range TSTG -65 ~ +150 °C2
  • 3. LM555/NE555/SA555Electrical Characteristics(TA = 25°C, VCC = 5 ~ 15V, unless otherwise specified) Parameter Symbol Conditions Min. Typ. Max. Unit Supply Voltage VCC - 4.5 - 16 V VCC = 5V, RL = ∞ - 3 6 mA Supply Current (Low Stable) (Note1) ICC VCC = 15V, RL = ∞ - 7.5 15 mA Timing Error (Monostable) Initial Accuracy (Note2) ACCUR - 1.0 3.0 % Drift with Temperature (Note4) RA = 1kΩ to100kΩ ∆t/∆T 50 ppm/°C Drift with Supply Voltage (Note4) C = 0.1µF ∆t/∆VCC 0.1 0.5 %/V Timing Error (Astable) - Intial Accuracy (Note2) ACCUR RA = 1kΩ to 100kΩ 2.25 - % Drift with Temperature (Note4) ∆t/∆T C = 0.1µF 150 ppm/°C Drift with Supply Voltage (Note4) ∆t/∆VCC 0.3 %/V VCC = 15V 9.0 10.0 11.0 V Control Voltage VC VCC = 5V 2.6 3.33 4.0 V VCC = 15V - 10.0 - V Threshold Voltage VTH VCC = 5V - 3.33 - V Threshold Current (Note3) ITH - - 0.1 0.25 µA VCC = 5V 1.1 1.67 2.2 V Trigger Voltage VTR VCC = 15V 4.5 5 5.6 V Trigger Current ITR VTR = 0V 0.01 2.0 µA Reset Voltage VRST - 0.4 0.7 1.0 V Reset Current IRST - 0.1 0.4 mA VCC = 15V ISINK = 10mA - 0.06 0.25 V Low Output Voltage VOL ISINK = 50mA 0.3 0.75 V VCC = 5V - 0.05 0.35 V ISINK = 5mA VCC = 15V ISOURCE = 200mA 12.5 - V High Output Voltage VOH ISOURCE = 100mA 12.75 13.3 V VCC = 5V 2.75 3.3 - V ISOURCE = 100mA Rise Time of Output (Note4) tR - - 100 - ns Fall Time of Output (Note4) tF - - 100 - ns Discharge Leakage Current ILKG - - 20 100 nANotes:1. When the output is high, the supply current is typically 1mA less than at VCC = 5V.2. Tested at VCC = 5.0V and VCC = 15V.3. This will determine the maximum value of RA + RB for 15V operation, the max. total R = 20MΩ, and for 5V operation, the max. total R = 6.7MΩ.4. These parameters, although guaranteed, are not 100% tested in production. 3
  • 4. LM555/NE555/SA555Application InformationTable 1 below is the basic operating table of 555 timer: Table 1. Basic Operating Table Threshold Voltage Trigger Voltage Discharging Tr. Reset(PIN 4) Output(PIN 3) (Vth)(PIN 6) (Vtr)(PIN 2) (PIN 7) Dont care Dont care Low Low ON Vth > 2Vcc / 3 Vth > 2Vcc / 3 High Low ON Vcc / 3 < Vth < 2 Vcc / 3 Vcc / 3 < Vth < 2 Vcc / 3 High - - Vth < Vcc / 3 Vth < Vcc / 3 High High OFFWhen the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage orthe trigger voltage. Only when the high signal is applied to the reset terminal, the timers output changes according tothreshold voltage and trigger voltage.When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timers internal discharge Tr.turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintainedlow. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timers internaldischarge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.1. Monostable Operation +Vcc 2 10 4 8 RA RESET Vcc 10 1 kΩ Ω Trigger Ω kΩ DISCH 7 Ω =1 M 0k 10 1M 10 10 A A R 2 Capacitance(uF) TRIG 10 0 THRES 6 -1 10 3 OUT C1 CONT 5 -2 10 GND RL 1 C2 -3 10 -5 -4 -3 -2 -1 0 1 2 10 10 10 10 10 10 10 10 Time Delay(s) Figure 1. Monoatable Circuit Figure 2. Resistance and Capacitance vs. Time delay(td) Figure 3. Waveforms of Monostable Operation4
  • 5. LM555/NE555/SA555Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage fallsbelow Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timersinternal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1and setting the flip-flop output at the same time.The voltage across the external capacitor C1, VC1 increases exponentially with the time constant t=RA*C and reaches 2Vcc/3at td=1.1RA*C. Hence, capacitor C1 is charged through resistor RA. The greater the time constant RAC, the longer it takesfor the VC1 to reach 2Vcc/3. In other words, the time constant RAC controls the output pulse width.When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationshipbased on RA and C. Figure 3 shows the general waveforms during the monostable operation.It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timeroutput turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output ishigh, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulseremains at below Vcc/3. Figure 4 shows such a timer output abnormality.Figure 4. Waveforms of Monostable Operation (abnormal)2. Astable Operation +Vcc 100 RA (R A+2R B) 4 8 10 1k 1 Ω RESET Vcc 10 7 Capacitance(uF) kΩ DISCH 1 10 2 TRIG 00 0 0 kΩ RB 1M 1 Ω Ω Ω THRES 6 Ω 0.1 10 0M Ω Ω Ω Ω 3 OUT C1 0.01 CONT 5 GND RL 1 C2 1E-3 100m 1 10 100 1k 10k 100k Fr equency(Hz) Figure 5. Astable Circuit Figure 6. Capacitance and Resistance vs. Frequency 5
  • 6. LM555/NE555/SA555 Figure 7. Waveforms of Astable OperationAn astable timer operation is achieved by adding resistor RB to Figure 1 and configuring as shown on Figure 5. In the astableoperation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multivibrator. When the timer output is high, its internal discharging Tr. turns off and the VC1 increases by exponentialfunction with the time constant (RA+RB)*C.When the VC1, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 dischargesthrough the discharging channel formed by RB and the discharging Tr. When the VC1 falls below Vcc/3, the comparatoroutput on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and theVC1 rises again.In the above process, the section where the timer output is high is the time it takes for the VC1 to rise from Vcc/3 to 2Vcc/3,and the section where the timer output is low is the time it takes for the VC1 to drop from 2Vcc/3 to Vcc/3. When timer outputis high, the equivalent circuit for charging capacitor C1 is as follows: RA RB Vcc C1 Vc1(0-)=Vcc/3 dv c1 V cc – V ( 0- ) C ------------ = ------------------------------ - - (1) 1 dt RA + RB V ( 0+ ) = V ⁄3 (2) C1 CC  t   -  – ------------------------------------  ( R + R )C1  2  A B  V C1 ( t ) = V CC  1 – -- e -  (3)  3   Since the duration of the timer output high state(tH) is the amount of time it takes for the VC1(t) to reach 2Vcc/3,6
  • 7. LM555/NE555/SA555  t   -  – ------------------------------------  H 2  2  ( R A + R B )C1  V ( t ) = -- V - =V  1 – -- e -  (4) C1 3 CC CC  3    t = C ( R + R )In2 = 0.693 ( R + R )C (5) H 1 A B A B 1The equivalent circuit for discharging capacitor C1, when timer output is low is, as follows: RB C1 VC1(0-)=2Vcc/3 RD dv 1 C1 C 1 -------------- + ---------------------- V C1 = 0 - (6) dt R +R A B t - ------------------------------------ - 2 ( R A + R D )C1 V C1 ( t ) = -- V - (7) 3 CC eSince the duration of the timer output low state(tL) is the amount of time it takes for the VC1(t) to reach Vcc/3, tL - ------------------------------------ ( R A + R D )C1 - 1 2 -- V - = -- V - (8) 3 CC 3 CC e t = C ( R + R )In2 = 0.693 ( R + R )C (9) L 1 B D B D 1Since RD is normally RB>>RD although related to the size of discharging Tr.,tL=0.693RBC1 (10)Consequently, if the timer operates in astable, the period is the same withT=tH+tL=0.693(RA+RB)C1+0.693RBC1=0.693(RA+2RB)C1 because the period is the sum of the charge time and dischargetime. And since frequency is the reciprocal of the period, the following applies. 1 1.44 frequency, f = -- = --------------------------------------- - - ( 11 ) T ( R + 2R )C A B 13. Frequency dividerBy adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle. 7
  • 8. LM555/NE555/SA555 Figure 8. Waveforms of Frequency Divider Operation4. Pulse Width ModulationThe timer output waveform may be changed by modulating the control voltage applied to the timers pin 5 and changing thereference of the timers internal comparators. Figure 9 illustrates the pulse width modulation circuit.When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according tothe signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the controlterminal. Figure 10 shows the example of pulse width modulation waveform. +Vcc RA 4 8 RESET Vcc 7 Trigger DISCH 2 TRIG 6 THRES Output 3 OUT Input GND CONT 5 C 1 Figure 9. Circuit for Pulse Width Modulation Figure 10. Waveforms of Pulse Width Modulation5. Pulse Position ModulationIf the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11,the timer becomes a pulse position modulator.In the pulse position modulator, the reference of the timers internal comparators is modulated which in turn modulates thetimer output according to the modulation signal applied to the control terminal.Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any waveshape could be used.8
  • 9. LM555/NE555/SA555 +Vcc RA 4 8 RESET Vcc 7 DISCH 2 TRIG RB 6 THRES Output 3 OUT Modulation GND CONT 5 C 1 Figure 11. Circuit for Pulse Position Modulation Figure 12. Waveforms of pulse position modulation6. Linear RampWhen the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the VC1increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates thegenerated linear ramp waveforms. +Vcc RE R1 4 8 RESET Vcc DISCH 7 2 TRIG Q1 THRES 6 R2 Output 3 OUT C1 CONT 5 GND 1 C2 Figure 13. Circuit for Linear Ramp Figure 14. Waveforms of Linear RampIn Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and RE. V –V I CC E = -------------------------- - ( 12 ) C R E Here, V E is R2 V = V + --------------------- V - ( 13 ) E BE R 1 + R 2 CCFor example, if Vcc=15V, RE=20kΩ, R1=5kW, R2=10kΩ, and VBE=0.7V,VE=0.7V+10V=10.7VIc=(15-10.7)/20k=0.215mA 9
  • 10. LM555/NE555/SA555When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes aconstant current generated by PNP transistor and resistors.Hence, the VC is a linear ramp function as shown in Figure 14. The gradient S of the linear ramp function is defined asfollows: Vp – p S = ---------------- ( 14 ) THere the Vp-p is the peak-to-peak voltage.If the electric charge amount accumulated in the capacitor is divided by the capacitance, the VC comes out as follows:V=Q/C (15)The above equation divided on both sides by T gives us V Q⁄T --- = ----------- - - ( 16 ) T Cand may be simplified into the following equation.S=I/C (17)In other words, the gradient of the linear ramp function appearing across the capacitor can be obtained by using the constantcurrent flowing through the capacitor.If the constant current flow through the capacitor is 0.215mA and the capacitance is 0.02µF, the gradient of the ramp functionat both ends of the capacitor is S = 0.215m/0.022µ = 9.77V/ms.10
  • 11. LM555/NE555/SA555Mechanical DimensionsPackage Dimensions in millimeters 8-DIP ) 6.40 ±0.20 0.031 0.79 0.252 ±0.008 1.524 ±0.10 0.060 ±0.004 0.018 ±0.004 0.46 ±0.10 ( #1 #8 0.362 ±0.008 MAX 9.20 ±0.20 0.378 9.60 #4 #5 0.100 2.54 5.08 3.30 ±0.30 MAX 0.130 ±0.012 0.200 7.62 0.300 3.40 ±0.20 0.33 0.134 ±0.008 0.013 MIN +0.10 0.25 –0.05 +0.004 0.010 –0.002 0~15° 11
  • 12. LM555/NE555/SA555Mechanical Dimensions (Continued)Package Dimensions in millimeters 8-SOP 0.1~0.25 MIN 0.004~0.001 1.55 ±0.20 0.061 ±0.008 ) 0.022 0.56 ( #1 #8 0.194 ±0.008 MAX 4.92 ±0.20 0.202 5.13 0.016 ±0.004 0.41 ±0.10 #4 #5 0.050 1.27 6.00 ±0.30 1.80 0.236 ±0.012 MAX 0.071 0.006 -0.002 0.15 -0.05 MAX0.004 MAX0.10 3.95 ±0.20 +0.004 +0.10 0.156 ±0.008 8° 5.72 0~ 0.225 0.50 ±0.20 0.020 ±0.00812
  • 13. LM555/NE555/SA555Ordering Information Product Number Package Operating Temperature LM555CN 8-DIP 0 ~ +70°C LM555CM 8-SOP Product Number Package Operating Temperature NE555N 8-DIP 0 ~ +70°C NE555D 8-SOP Product Number Package Operating Temperature SA555 8-DIP -40 ~ +85°C SA555D 8-SOP 13
  • 14. LM555/NE555/SA555DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANYPRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHERDOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICESOR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTORCORPORATION. As used herein:1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.www.fairchildsemi.com 11/29/02 0.0m 001 Stock#DSxxxxxxxx  2002 Fairchild Semiconductor Corporation