Your SlideShare is downloading. ×
0
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Micro operation control of processor
Upcoming SlideShare
Loading in...5
×

Thanks for flagging this SlideShare!

Oops! An error has occurred.

×
Saving this for later? Get the SlideShare app to save on your phone or tablet. Read anywhere, anytime – even offline.
Text the download link to your phone
Standard text messaging rates apply

Micro operation control of processor

1,507

Published on

0 Comments
0 Likes
Statistics
Notes
  • Be the first to comment

  • Be the first to like this

No Downloads
Views
Total Views
1,507
On Slideshare
0
From Embeds
0
Number of Embeds
1
Actions
Shares
0
Downloads
38
Comments
0
Likes
0
Embeds 0
No embeds

Report content
Flagged as inappropriate Flag as inappropriate
Flag as inappropriate

Select your reason for flagging this presentation as inappropriate.

Cancel
No notes for slide

Transcript

  • 1. •Instruction cycle has a number of smaller units 1.Fetch 2. Indirect 3. Execute 4.Interrupt • Micro-operations Each part of the cycle has a number of smaller steps called micro-operations • Micro-operations are Fundamental atomic operations of the processor
  • 2. It includes four Registers. • Memory Address Register (MAR) — Connected to address bus — Specifies address for read or write op • Memory Buffer Register (MBR) — Connected to data bus — Holds data to write or last data read • Program Counter (PC) — Holds address of next instruction to be fetched • Instruction Register (IR) — Holds last instruction fetched
  • 3. Clock • Repetitive sequence of pulses • Useful for measuring duration of micro-ops • Different control signals at different times within instruction cycle • Need a counter with different control signals for t1, t2 etc. The notation represents successive time units. • First time unit: Move contents of PC to MAR. • Second time unit: Move contents of memory location from MAR to MBR. Increment by I the contents of the PC. • Third time unit: Move contents of MBR to IR.
  • 4. • The fetch cycle actually consists of 3 steps & 4 micro ops • Each micro-op consists of moving data in or out of a Register AS • Address of next instruction is in PC t1: MAR <- (PC) • Data from data bus copied into MBR • PC incremented t2: MBR <- (memory) PC <- (PC) +I • Data (instruction) moved from MBR to IR t3: IR <- (MBR)
  • 5. • Proper sequence must be followed i. MAR <- (PC) must precede MBR <-(memory) cycle ii. Conflicts must be avoided iii. Must not read & write same register in same iv. MBR <- (memory) & IR <- (MBR) must not be in same cycle v. Also PC <- (PC) +1 involves addition • Might need to Use ALU • May need additional micro operations.
  • 6. • If an instruction specifies an indirect addressing • Then indirect cycles precedes the execution cycle. i-Instruction fetched ii-Fetch source operands • It includes the following micro-operations: i. The address field of the instruction is transferred to the MAR t1: MAR <- (IR address) - address field of IR ii. This is then used to fetch the address of the operand. t2: MBR <- (memory) iii. The address field of the IR is updated from the MBR, so that it now contains a direct rather than an indirect address. t3: IR address <- (MBR address) • Now MBR contains direct address of operand IR is updated with direct address of operand IR is now in same state as if direct addressing .
  • 7. • Fetch, Indirect and Interrupt cycles are simple and predictable • Execute cycle is different for each instruction • There are A number of different sequences of microoperations •Example: ADD R1,X IR contains the ADD instruction i. The address portion of the IR is loaded into the MAR t1: MAR <- (IR address) ii. The referenced memory location is read t2: MBR <- (memory) iii. Finally, the contents of R1 and MBR are added by ALU. t3: R1 <- R1 + (MBR)
  • 8. • Additional micro-operations may be required i. To extract the register reference from the IR ii. To stage the ALU inputs or outputs in some intermediate registers. • More complex example: ISZ X (increment and skip if zero): The content of location X is incremented by 1.If the result is 0,the next instruction is skipped . A possible sequence of micro-operations is t1: MAR ← (IR(address)) t2: MBR ← Memory t3: MBR ← (MBR) + 1 t4: Memory ← (MBR) • This test and action can be implemented as one micro-operation: Conditional action is “the PC is incremented if MBR=0” If ((MBR) = 0) then (PC ← (PC) + I) • Also that this micro-operation can be performed during the same time unit during which the updated value in MBR is stored back to memory
  • 9. • At end of execute cycle, processor tests interrupt signal. i. If set, an interrupt cycle occurs ii. Varies greatly from one machine to another • How It Performs: i. The contents of the PC are transferred to the MBR , so that they can be saved for return from the interrupt t1: MBR <-(PC) saved ii. MAR is loaded with the address At which the contents of the PC are to be t2: MAR <- save-address PC is loaded with the address of the start of the interrupt-processing routine. PC <- routine-address iii. Store the MBR, which contains the old value of the PC into memory. t3: memory <- (MBR) • This is a minimum level of Complexity. • Most processors may provide multiple types of address i. So there may be additional micro-ops to get addresses ii. Note that saving context is done by interrupt handler routine, not micro-ops.
  • 10. • Each phase is decomposed into a sequence of micro operations i. Fetch, indirect, interrupt and Execute cycles ii. • Tie these above sequences together into the instruction cycle • Assume new 2-bit register: The instruction cycle code (ICC) designates which part of cycle is in processor • 00: Fetch • 01: Indirect • 10: Execute • 11: Interrupt
  • 11. • Decomposing Functioning : It decomposes functioning of the processor into elementary operations, called micro-operations. • Exactly what it is that the control unit doing? • Functional Requirements: i. Define the basic elements of the processor ii. Describe the micro-operations that the processor performs iii. Determine the functions control unit must perform in order to execute the micro-ops
  • 12. • Basic Elements of processor i.Registers ii.Internal data pahs iii.External data paths iv.ALU v.Control Unit • Types of Micro-operation i. Transfer data between registers ii. Transfer data from register to external interface iii. Transfer data from external interface to register iv. Perform arithmetic or logical operations using registers
  • 13. • Control Unit performs two basic tasks i. Sequencing Causing the CPU to step through a series of micro operations ii. Execution Causing the performance of each micro operations. • How it Performs? Ans: • Key to operation is the use of control signals
  • 14. Signal: A pulse or frequency of electricity or light that represents a control command • External specifications of the control unit: i. Inputs : allow it to determine the state of the system ii. Outputs : allow it to control the behavior of the system. • Internally it requires logic to perform its sequencing and execution functions.
  • 15. • Clock i. This is how the control unit “keeps time.” ii. The control unit causes one micro-operation or more to be performed for each clock pulse. iii. processor cycle time, or the clock cycle time. • Instruction register: i. The op code and addressing mode of the current instruction are used to determine which micro-operations to perform during the execute cycle. • Flags: i. To determine the status of the processor ii. To see the outcome of previous ALU operations. For example The increment-and-skip-if-zero (ISZ) instruction, the control unit will increment the PC if the zero flag is set. • Control signals from control bus: The control bus portion of the system bus provides signals to the control unit.
  • 16. • Control signals within the processor: These are two types: i. That cause data to be moved from one register to another ii. To activate specific ALU functions. • Control signals to control bus: These are also of two types : i. Control signals to memory, ii. Control signals to the I/O modules. • Three types of control signals are used: i. those that activate an ALU function, ii. those that activate a data path iii. those that are signals on the external system bus

×