IEEE SWTW 2012 Road to 450 mm Semiconductor Wafers - Ira Feldman li2
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IEEE SWTW 2012 Road to 450 mm Semiconductor Wafers - Ira Feldman li2

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Ira Feldman's presentation about the wafer probe impact of the transition to 450 mm semiconductor wafers from IEEE Semiconductor Wafer Test Workshop (SWTW) 2012.

Ira Feldman's presentation about the wafer probe impact of the transition to 450 mm semiconductor wafers from IEEE Semiconductor Wafer Test Workshop (SWTW) 2012.

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IEEE SWTW 2012 Road to 450 mm Semiconductor Wafers - Ira Feldman li2 IEEE SWTW 2012 Road to 450 mm Semiconductor Wafers - Ira Feldman li2 Presentation Transcript

  • The  Road  to  450  mm  Semiconductor  Wafers   Ira  Feldman   Feldman  Engineering  Corp.  
  • Overview  •  Why  450  mm  Wafers?  •  Technical  Challenges  •  Economic  Challenges  •  SoluBons  •  Summary   2
  • …  the  number  of  transistors  on  a  chip  will  double   approximately   every  year  two   years  …   Gordon Moore 1962 credit: Fairchild Camera & Instrument Corporation. 3
  • Electronics, Volume 38, Number 8, April 19, 1965The experts look aheadCramming more componentsonto integrated circuitsWith unit cost falling as the number of components percircuit rises, by 1975 economics may dictate squeezing asmany as 65,000 components on a single silicon chipBy Gordon E. MooreDirector, Research and Development Laboratories, Fairchild Semiconductordivision of Fairchild Camera and Instrument Corp.The complexity for minimum component costs has increased at a rate of roughly a factor of twoper year (see graph on next page). Certainly over the short term this rate can be expected tocontinue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain,although there is no reason to believe it will not remain nearly constant for at least 10 years.That means by 1975, the number of components per integrated circuit for minimum cost will be65,000. 4
  • Economics again! r If the total A= πr2 incremental cost of manufacturing ar’ = 1.5r wafer 1.5 times the previous size is heldA’ = 2.25A to 12.5%, the cost per area for the largerIf cost’ = 1.125 cost wafer is half.cost’/A’ ≈ 1 process node = 0.5cost/A Intel 200 à 300 mm > 30% per die cost reduction 5
  • u  2006 estimate ç 2009 update ✪  current estimate ✔ complete ✔ ✪Dean Freeman, “The Shift to Mobility”, SEMI SV Lunch Forum, April 19, 2012 6
  • TECHNICAL  CHALLENGES   7
  • Prober  -­‐  Direct  Scale  Up?     1.5x   AccretechDimensions   1450  w  x  1775  d  x  1420  h  mm   Dimensions   2175  w  x  2663  d  x  1420  h  mm  ?  Weight   1500  kg   Weight   3375  kg  ?   8
  • TestWIP  /  Cycle  Time  Impact   time per wafer 300 mm examples (hr) “Half Boat” Candidates 9
  • TestWIP  /  Cycle  Time  Impact   time per wafer (hr) 450 mm – examples – 300 mm “Half Boat” Candidates 10
  • Very  Large  Printed  Circuit  Boards  (PCB)   300 450 450 mm mm mm 440 mm 590 mm 660 mm [17.3 in] [23.2 in] [26.0 in]Current DRAM tester Same connector Connector area increased area width by 2.25x for additional signals 11
  • Probe  Force   FormFactor  Total  Probe  Force  (kgF)   1.6gF/mil  @  4mil   FormFactor   1gF/mil  @  3mil   Touchdown,  Microfabrica   &  others  ~2  gF   Current  High  Force  Probers   Cascade  Microtech   ~1  gF   Number  of  Probes  (K)   Marinissen – IMEC / Cascade Microtech 2011; Losey – Touchdown Technologies 2010; Huebner – FormFactor 2009; Folk – Microfabrica 2008 12
  • Operational probe movement Probe card operating range Change in Position, µm Change in Temperature (ΔT), °C Please see notes on next page 13
  • •  AssumpBons  &  notes   –  Wafer  chuck  &  wafer  are  at  desired  temperature     •  Stable  due  to  acYve  thermal  management  of  chuck.   •  Wafer  heats  up  “instantly”  due  to  low  relaYve  thermal  mass  and  pre-­‐heaYng.   –  CalculaYons  are  worst  case  at  wafer  edge  r=225  mm   –  Probe  movement  is  predominantly  thermal  movement  of  probe  card   •  Probe  card  heats  and  cools  as  heat  source  (chuck)  moves  away  to  perform  operaYons  unless  acYve  thermal  management  is   implemented.   •  Different  sYffener  /  structural  materials  are  listed.   •  Actual  coefficient  of  thermal  expansion  (CTE)  of  probe  card  typically  higher  due  to  high  CTE  of  PCB  and  other  materials.   –  First  order  calculaYons  of  thermal  posiYoning  effects  in  plane  (X  &  Y)  only,  there  are  significant  other   factors  including  movement  of  probe  card  in  Z,  warping,  and  thermal  stress  that  need  to  be  considered.  •  CalculaBons   –  First  order  thermal  movement  of  probe  at  edge  of  probe  card  (worst  case):   •  Delta  Probe  PosiYon  =  r  *  delta  Temperature  *  CTE   –  OperaYng  range:   •  Delta  Temperature  =  (maximum  hot  temperature  –  maximum  cold  temperature)  /  2   •  Example:  hot  =  100  C,  cold  =  -­‐20  C  è  delta  T  =  60  C,  card  designed  scaled  for  nominal  40  C.  •  Recent  papers  addressing  thermal  movement  include   –  Daniels  –  Texas  Instruments  SWTW  2011   –  Lee  –  GigaLane  SWTW  2011   –  Breinlinger  –  FormFactor  SWTW  2009   –  Boehm  –  Feinmetall  SWTW  2009   –  Harker  –  FormFactor  SWTW  2009     14
  • ECONOMIC  CHALLENGES   15
  • Can Stock Photo Inc. / alekseykh 16
  • Only Serial Fab Processes: •  Photolithography reticle stepping •  Ion Implantation •  Metrology & inspection •  Non-full wafer testCan Stock Photo Inc. / stillfx 17
  • Larger  Probe  Cards  =   •  Higher  Material  &   Processing  Costs   •  New  NREs   •  New  Equipment     Yield  –  larger  area   requires  lower  defect   density  or  cost   effecYve  rework.    Feldman SWTW 2011 18
  • Intelmade it simple last time:Relative Capital Cost <= 1.3Relative Footprint <= 1.0Seligson 19
  • Mike Splinter, SEMI ISS, January 17, 2012 20
  • SOLUTIONS   21
  • For  extreme   diseases,   extreme   methods  of  cure,   as  to  restricYon,   are  most   suitable.   Hippocrates ca. 460 – 370 BCEEngraving by Rubens 22
  • Possible  SoluBons  LocaBon   Type   Research  &   Short  Term   Long  Term   Development   (delayed   investment)  In  Fab   In  Process  /  Parametric   Semi-­‐automaYc   Flying  probe   Super-­‐sized   probe  staYon   wafer  prober   Single  to  medium   Super-­‐sized   mulYsite   wafer  prober     Test  in  Tray   Quartered   ReconsYtuted      Post  Fab   Full  wafer  contact   wafers   wafers     (1-­‐10?  TDs)   Simplified   prober  /   restricted   movement   23
  • Flying  Probe  for  In  Process  SPEA 24
  • Possible  SoluBons  LocaBon   Type   Research  &   Short  Term   Long  Term   Development   (delayed   investment)  In  Fab   In  Process  /  Parametric   Semi-­‐automaYc   Flying  probe   Super-­‐sized   probe  staYon   wafer  prober   Single  to  medium   Super-­‐sized   mulYsite   wafer  prober     Test  in  Tray   Quartered   ReconsYtuted      Post  Fab   Full  wafer  contact   wafers   wafers     (1-­‐10?  TDs)   Simplified   prober  /   restricted   movement   25
  • Quarter  the  Wafer?   D=450  mm   26
  • Issues:•  Equipment (prober) compatibility•  Lost die X  •  Inefficient Lost Die utilization•  Four different step / probe patterns for high parallelism probing D=300  mm   27
  • Reconstituted partial “wafer” Dice arrayed in efficient probing shape on 300 mm film frameIntel Ivy Bridge “mash up” 28
  • Possible  SoluBons  LocaBon   Type   Research  &   Short  Term   Long  Term   Development   (delayed   investment)  In  Fab   In  Process  /  Parametric   Semi-­‐automaYc   Flying  probe   Super-­‐sized   probe  staYon   wafer  prober   Single  to  medium   Super-­‐sized   mulYsite   wafer  prober     Test  in  Tray   Quartered   ReconsYtuted      Post  Fab   Full  wafer  contact   wafers   wafers     (1-­‐10?  TDs)   Simplified   prober  /   restricted   movement   29
  • Test-in-Tray Centipede Systems’ FlexFrameReusable trayExample devices: 64 die per tray 7.2 mm x 8.3 mm 50 µm Al padsCentipede SystemsSee also: Test in Tray: Thomas Di Stefano - BiTS 2012 30
  • Possible  SoluBons  LocaBon   Type   Research  &   Short  Term   Long  Term   Development   (delayed   investment)  In  Fab   In  Process  /  Parametric   Semi-­‐automaYc   Flying  probe   Super-­‐sized   probe  staYon   wafer  prober   Single  to  medium   Super-­‐sized   mulYsite   wafer  prober     Test  in  Tray   Quartered   ReconsYtuted      Post  Fab   Full  wafer  contact   wafers   wafers     (1-­‐10?  TDs)   Simplified   prober  /   restricted   movement   31
  • Chuck  Area  Minimum chuck area is Wafer chuck &approximately: D ¼ wafer sub-chuckD = 300 mm à 636 mm sq. 0.5DD = 450 mm à 955 mm sq. camerato reach center of headplate opening with all die,sub-chuck, & camera. Head plate opening ~ 3D/(√2) 32
  • Full  Wafer  Contactor  Prober?   Head plate Prober designed for use opening with full wafer contactors Wafer chuck (FWC) such as 1 TD or “rainbow” probe cards. ~ D + 2*50 mm D Restricted movement to +/- 50 mm Y, +/- 10 mm X?FormFactor SmartMatrix ~ D + 2*10 mm 33
  • Micronics Japan Co. 34
  • Future Test Cell? 35
  • Summary  •  Some  challenges  are  1.5x  others  are  2.25x  •  MulBple  soluBons  to  technical  challenges  for   R&D,  short  term,  and  long  term   –  Need  to  plan  accordingly  •  Largest  challenge  is  financial   –  Need  right  soluYon  for  each  problem  with  proper   return  on  investment  (ROI)     –  Don’t  want  to  over  invest  or  “miss  the  boat”  •  InflecBon  point  enables  innovaBon   36
  • 450  mm   300  mm  Can Stock Photo Inc. / andrewro 37
  • Acknowledgments  •  Accretech  •  Applied  Materials  •  Cascade  Microtech  •  CenBpede  Systems  •  FormFactor  •  Micronics  Japan  Co.  (MJC)  •  MulBtest  •  SPEA  •  Tokyo  Electron   38
  • Thank  You!     Ira  Feldman  ira@feldmanengineering.com     Visit  my  blog   www.hightechbizdev.com   for  my  summary  of  SWTW     39
  • References  •  “Cramming  more  components  onto  integrated  circuits”,  Gordon   E.  Moore,  Electronics,  Volume  38,  Number  8,  April  19,  1965.   hip://j.mp/ICfrn9  •  “Planning  for  the  300mm  TransiBon”,  Daniel  Seligson,  Intel   Technology  Journal  Q4  ’98.  hip://j.mp/JMZ3Vx    •  “PosiBon  Paper  for  450mm  Development”,  InternaBonal   Technology  Roadmap  for  Semiconductors  (ITRS)  StarBng   Materials  Sub-­‐TWG,  June  2005.  hip://j.mp/J02AP2     40