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  • 1. MARTE based model driven designmethodology for targeting dynamically reconfigurable FPGA based SoCs Imran Rafiq Q UADRI PhD Defense 20th April, 2010(Imran Rafiq QUADRI - PhD Defense) 20th April 2010 1 / 41
  • 2. Outline DIP Control aspects applications MDE SoC Co-Design (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 2 / 41
  • 3. Outline DIP Control aspects applications MDE SoC Co-Design (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 2 / 41
  • 4. Outline : Systems-on-Chips
  • 5. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 3 / 41
  • 6. Systems-on-Chips Important characteristics
  • 7. Omnipresent in our daily lives
  • 8. Targeted application domains Conception : !
  • 9. # Modeling, Simulation, $%% Synthesis .. Reconfigurability (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 3 / 41
  • 10. Systems-on-Chips Important characteristics Omnipresent in our daily lives Targeted application domains Conception : Modeling, Simulation, Synthesis .. Reconfigurability (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 3 / 41
  • 11. Systems-on-Chips Important characteristics Omnipresent in our daily lives Targeted application domains Conception : Modeling, Simulation, Synthesis .. Reconfigurability (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 3 / 41
  • 12. Reconfigurable Systems Reconfigurable Computing Possible implementation of paradigms such as : Sequential execution : on processors Data Parallel execution : on hardware accelerators Different terminologies : ConfigWare, Morphware, Flowware. . . Classification Granularity, coupling, interconnections, reconfiguration type, etc Towards Reconfigurable Systems-on-Chips Field Programmable Gate Arrays (FPGAs) (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 4 / 41
  • 13. Types of Reconfiguration Where ? Exo / Endo reconfiguration When ? Static / Dynamic How ? Full / Partial Presence of a controller component (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 5 / 41
  • 14. Partial Dynamic Reconfiguration (PDR) : Self internal reconfiguration possible One Partial Reconfigurable Region (PRR) can have multiple Partial Reconfigurable Modules (PRMs) (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 6 / 41
  • 15. SoC design challenges Productivity / Complexity Productivity gap Reliability / Verification Loss of human lives, system loss Reconfigurability How to express control ? (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 7 / 41
  • 16. SoC design challenges Productivity / Complexity Productivity gap Reliability / Verification Loss of human lives, system loss Reconfigurability How to express control ? Some solutions : Component based approach, elevation of design abstraction levels, SoC Co-Design, IP-Reuse, etc (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 7 / 41
  • 17. Component Based Software Engineering (CBSE)CBSE and Reconfigurability Component Models and Component Frameworks Homogeneous / Heterogeneous Static / Dynamic Adaptivity in CBSE Present at different granularities Techniques : AOP, Wrappers, Reflection etc Controller component manages Configurations (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 8 / 41
  • 18. Outline : Model-Driven Engineering
  • 19. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 9 / 41
  • 20. Model-Driven Engineering Models Metamodels Model Transformations UML profiles (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 9 / 41
  • 21. Model-Driven Engineering Models Metamodels Model Transformations UML profiles (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 9 / 41
  • 22. Model-Driven Engineering Models Metamodels Model Transformations UML profiles
  • 23. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 9 / 41
  • 24. MARTEModeling and Analysis of Real-Time and Embedded Systems For Real-Time and Embedded Systems Additional advantages such as : Non Functional Properties Timing aspects First version available since 2007 http ://www.omgmarte.org/ Support of current UML modeling tools Papyrus, Rhapsody, MagicDraw, Modelio etc (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 10 / 41
  • 25. MARTEModeling and Analysis of Real-Time and Embedded Systems MARTE compliant modeling tools Need of an underlying framework Aspects of (re)configurability Absent until version 1.0 released in early 2010 A large community still prefers HLS / RTL tools (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 11 / 41
  • 26. MARTEModeling and Analysis of Real-Time and Embedded Systems MARTE compliant modeling tools Need of an underlying framework Aspects of (re)configurability Absent until version 1.0 released in early 2010 A large community still prefers HLS / RTL tools Modeling of Reconfigurable Systems via MARTE .. I.Quadri et al. A Model Driven design flow for FPGAs supporting Partial Reconfiguration. International Journal of Reconfigurable Computing, Hindawi, 2009 I.Quadri et al. MARTE based modeling approach for partial dynamic reconfigurable fpgas. ESTIMedia, ESWEEK. USA. 2008 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 11 / 41
  • 27. Gaspard2 : SoC Co-Design framework $
  • 28. #
  • 29. $
  • 30. #
  • 31. $ $
  • 32. #
  • 33. !
  • 34. !
  • 35. !
  • 36. $
  • 37. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 38. Gaspard2 : SoC Co-Design frameworkA matrix-multiplication application and a QuadriPro architecture : Task Parallelism
  • 39. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 40. Gaspard2 : SoC Co-Design frameworkA matrix-multiplication application and a QuadriPro architecture : Data Parallelism MatrixMultiplication matrixIN1: Real(8) [{4,4}] «tiler» «shaped» origin = {0,0}, dp: dotProduct [{4,4}] paving = {{1,0},{0,0}}
  • 41. fitting = {{0,1}} matrixOUT: Real(8) [{4,4}]
  • 42. row: Real(8) [{4}] dot: Real(8) [{}] origin = {0,0}, «tiler» paving = {{0,0},{0,1}} column: Real(8) [{4}] origin = {0,0},
  • 43. fitting = {{1,0}} paving = {{1,0},{0,1}} fitting = {{}} «tiler» matrixIN2: Real(8) [{4,4}] «hwComputingResource» RepProcessingUnit ibus [{4}]] «tiler» «hwProcessor, shaped» origin = {0}, ibus [{}] paving = {{1}} 4u: ProcessingUnit [{4}] fitting = {{0}} origin = {0}, paving = {{1}} dbus [{}] fitting = {{0}} «tiler» dbus [{4}]] (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 44. Gaspard2 : SoC Co-Design frameworkA matrix-multiplication application and a QuadriPro architecture : Allocation MatrixMultiplication matrixIN1: Real(8) [{4,4}] «tiler» «shaped» origin = {0,0}, dp: dotProduct [{4,4}]
  • 45. paving = {{1,0},{0,0}} matrixOUT: Real(8) [{4,4}]
  • 46. fitting = {{0,1}} row: Real(8) [{4}] dot: Real(8) [{}] origin = {0,0}, «tiler» paving = {{0,0},{0,1}} column: Real(8) [{4}]
  • 47. fitting = {{1,0}} origin = {0,0}, paving = {{1,0},{0,1}} fitting = {{}} «tiler» matrixIN2: Real(8) [{4,4}] repetitionSpace = {4,4}, «Abstraction» patternShape = {1}, «Distribute» fromTiler = {origin = {0,0}, paving = {{1,0},{0,1}}, fitting = {{0,0}}} toTiler = {origin = {0}, paving = {{1},{0}}, fitting = {{0}}} «hwComputingResource» RepProcessingUnit ibus [{4}]] «tiler» «hwProcessor, shaped» origin = {0}, ibus [{}] paving = {{1}} 4u: ProcessingUnit [{4}] fitting = {{0}} origin = {0}, paving = {{1}} dbus [{}] fitting = {{0}} «tiler» dbus [{4}]] (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 48. Gaspard2 : SoC Co-Design frameworkA matrix-multiplication application and a QuadriPro architecture : Deployment dotProduct row: Real(8) [{4}] dot: Real(8) [{4}] column: Real(8) [{4}]
  • 49. «implements»
  • 50. «implements» «implements» «implements» «virtualIP» VirtualdotProduct «implements» vrow: Real(8) Linking an IP to an vdot: Real(8) Elementary component vcolumn: Real(8) «implements» «implements» «implements» «implements» «softwareIP» «softwareIP» dotProductimpHDL dotProductimpC «implements» «implements» «implements» IPHDLrow: Real(8) IPCrow: Real(8) IPHDLcolumn: Real(8) IPHDLdot: Real(8) IPCcolumn: Real(8) IPCdot: Real(8) «implements» «SoftwareIP» «SoftwareIP» language = VHDL language = C entryName = dotproduct parameters = [IPin1, IPin2, IPout] (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 51. Gaspard2 : SoC Co-Design frameworkA matrix-multiplication application and a QuadriPro architecture : Deployment
  • 52. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 12 / 41
  • 53. Positioning of the thesis SoC Co-Design Increasing complexity Component based approach No common standard High abstraction levels : MARTE No clear semantics or guidelines Gaspard2 SoC Co-Design framework No concrete realization of reconfigurability High level component based design methodology for reconfigurable SoCs in Gaspard2 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 13 / 41
  • 54. Contributions in Gaspard2 Two key concepts Dynamically reconfigurable hardware accelerator Reconfiguration controller $
  • 55. #
  • 56. $
  • 57. #
  • 58. $ $
  • 59. #
  • 60. !
  • 61. !
  • 62. !
  • 63. $
  • 64. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 14 / 41
  • 65. Design flowOverview of the compilation chain (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 15 / 41
  • 66. Outline : Control Semantics
  • 67. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 16 / 41
  • 68. Expressing Control semantics ? How to express control at high abstraction levels ? Should integrate seamlessly at all SoC design levels Application, Architecture, Allocation, IP-deployment What control semantics to use StateCharts, Petri nets, Mode Automata ? Initial contributions O. Labbani. Modélisation à haut niveau du contrôle dans des applications de traitement systématique à parallélisme massif . USTL. 2006 Notion of Degree of granularity, no hierarchical / parallel compositions H. Yu. A MARTE-Based Reactive Model for Data-Parallel Intensive Processing : Transformation Toward the Synchronous Model. USTL. 2008 Hierarchical / parallel compositions possible, but only hypothesis (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 16 / 41
  • 69. Modes and State Graphs Mode Switch Component (MSC) Gaspard State Graph Represents a collection of Component (GSGC) modes Acts as controller component Switch functionality : for Mode Switch execution of Component one exclusive mode State Graphs : similar to Harel StateCharts The modes M1 , ..., Mn ; are identified by the mode Graphical representation of transition functions values : m1 , ..., mn All modes : same interface
  • 70. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 17 / 41
  • 71. Macro Componentcomposition of the two concepts Macro Component : represents a complete control structure One possible combination shown Gaspard State Graph Component produces mode value(s) and the Mode Switch Component switches the modes accordingly represents one transition from a source to target state (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 18 / 41
  • 72. Constructing Mode Automata Using additional MARTE concepts : Interrepetition dependency DefaultLink Tiler The Interrepetition dependency allows to represent continuous transitions C. Glitia. Optimisation des applications de traitement systématique intensives sur system-on-chip. USTL. 2009 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 19 / 41
  • 73. Control at which SoC design level ? Application level Different versions of an algorithm Yielding different degress of precision Example : DCT in H.264 codec
  • 74. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 20 / 41
  • 75. Control at which SoC design level ? Architecture level Adaptivity similar to application level Change in system structure or behavior Replacing a processor by a hardware accelerator Dynamic Frequency / Voltage Scaling
  • 76. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 20 / 41
  • 77. Control at which SoC design level ? Allocation level For increasing system performance Decreasing power consumption levels Spatial / Temporal allocation Design Space Exploration strategy
  • 78. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 20 / 41
  • 79. Control at which SoC design level ? Comparison of control at the three levels I. Quadri et al. High-level modeling of dynamically reconfigurable heterogeneous systems. Book Chapter in Heterogeneous Embedded Systems - Design Theory and Practice. Springer. 2010 I.Quadri et al. Integrating Mode Automata Control Models in SoC Co-Design for Dynamically Reconfigurable FPGAs. DASIP. France. 2009 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 21 / 41
  • 80. Control at which SoC design level ? Integration at another SoC design level IP-Deployment level (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 21 / 41
  • 81. Control at which SoC design level ? IP-Deployment level An ementary component can be related to an IP In SoC : application functionality can be either optimized for processor / hardware accelerator QoS criteria related to IPs : consumed resources, latency etc.
  • 82. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 22 / 41
  • 83. Extending current notion of ControlBasic conditions Addition of implementations in Array-OL Control scope levels Task level all repetitions changed Repetition level subset of repetitions changed Same Task-Multiple implementations level different repetition subsets related to different implementations Hybrid level all repetitions related to one implementation Limitations : Synchronization of control / data flow Data management (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 23 / 41
  • 84. Control at Deployment level Switching between global system implementations Application, Architecture and Allocation models can be reused Gaspard State graph component ⇒ controller Mode switch component ⇒ switch for implementations Modes have same interface a.k.a PRMs of a PRR (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 24 / 41
  • 85. MARTE metamodel and profile extension Behavioral concepts in MARTE are not detailed enough No notion of implementations for elementary components Use of Merge mechanism developed in DaRT
  • 86. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 25 / 41
  • 87. MARTE extension : State Graph concepts Integrating behavior with MARTE StructuredComponent MARTE compatible concepts StateGraphs, Transitions, Triggers, Events, Collaborations, etc 30+ Metaclasses, 40+ Metarelations (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 26 / 41
  • 88. MARTE extension : State Graph concepts Overview Property BehavioredClassifier (from Foundations) (from CommonBehavior) aggregation : AggregationKind 0..* collaborationRole mainBehavior ownedBehavior parts 0..1 0..* InteractionPort StructuredComponent AssemblyPart OpaqueBehavior Behavior ownedPorts 0..* doActivity body : EString 0..* language : EString 0..1 Action action ownedConnectors 0..* FlowPort 0..* isConjugated : EBoolean AssemblyConnector CompositeBehavior isAtomic : EBoolean direction : DirectionKind enumeration enumeration DirectionKind PseudostateKind _in initial _out submachine StateGraph deepHistory _inout shallowHistory 0..1 Collaboration NameSpace regions 1..* container Region name : EString 1..1 0..1 container event region Event 1..1 Trigger 0..* trigger 0..* transition subvertex transition 0..1 0..* target 0..* incoming 1..1 0..* MessageEvent ChangeEvent LiteralString Vertex Transition ModelElement (from Foundations) value : String unique_name : EString source name : EString transit outgoing name : String 0..1 changeExpression 0..* 1..1 1..1 AnyReceiveEvent connectionPoint 0..* ValueSpecification Pseudostate State (from vsl) LiteralSpecification kind : PseudostateKind state (from vsl) 0..1 submachineState 0..* (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 26 / 41
  • 89. MARTE extension : State Graph concepts Behavior, Collaborations ... Property BehavioredClassifier (from Foundations) (from CommonBehavior) aggregation : AggregationKind 0..* collaborationRole parts InteractionPort StructuredComponent AssemblyPart ownedPorts 0..* 0..* mainBehavior ownedBehavior 0..1 0..* ownedConnectors Behavior FlowPort 0..* isConjugated : EBoolean AssemblyConnector isAtomic : EBoolean direction : DirectionKind OpaqueBehavior body : EString enumeration language : EString DirectionKind _in _out _inout Collaboration (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 26 / 41
  • 90. MARTE extension : State Graph concepts State Graph, States ... OpaqueBehavior Behavior doActivity body : EString language : EString 0..1 Action action 0..* enumeration CompositeBehavior PseudostateKind initial submachine StateGraph deepHistory shallowHistory 0..1 NameSpace regions 1..* container Region name : EString 1..1 0..1 container region 0..* subvertex transition 0..* target 0..* incoming 1..1 0..* Vertex Transition unique_name : EString source name : EString transit outgoing 0..1 0..* 1..1 connectionPoint 0..* Pseudostate State kind : PseudostateKind state 0..1 submachineState 0..* (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 26 / 41
  • 91. MARTE extension : State Graph concepts Transitions, Triggers, Events ... event Event 1..1 Trigger trigger 0..* transition 0..1 0..* Transition MessageEvent ChangeEvent ModelElement LiteralString (from Foundations) value : String name : EString name : String changeExpression 0..* 1..1 AnyReceiveEvent ValueSpecification (from vsl) LiteralSpecification (from vsl) (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 26 / 41
  • 92. MARTE extension : IP-Deployment Initial concepts of IP-Deployment : E. Piel. Ordonnancement de systèmes parallèles temps-réel, de la modélisation à la mise en œuvre par l’ingénierie dirigée par les modèles. USTL. 2007 Notion of Configurations related to QoS (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 27 / 41
  • 93. MARTE extension : IP-Deployment Initial concepts of IP-Deployment : E. Piel. Ordonnancement de systèmes parallèles temps-réel, de la modélisation à la mise en œuvre par l’ingénierie dirigée par les modèles. USTL. 2007 Notion of Configurations related to QoS IP ClassifierTypeExtension language : EString (from extensions) entryName : EString logicalElements : EInt DynamicPower : EFloat Configuration name : String ConfigurationID : String InitialConfiguration : Boolean configuration 0..* SoftwareIP ipName : EString softwareIP 1..* (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 27 / 41
  • 94. Configurations A Global implementation of application, architecture or mapping of both Control at deployment : several configurations possible A configuration : collection of different IPs An elementary component can be associated with same IP in different configurations For n configurations : each having m elementary components, each elementary components must have at least one IP EC X EC Y EC Z IPY1 IPY2 IPZ1 IPX1 IPX2 Configuration C1 Configuration C2 ConfigurationID = Mode1 ConfigurationID = Mode2 InitialState = true InitialState = false ip = [IPX1, IPY1, IPZ1] ip = [IPX1, IPY2, IPZ1] (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 28 / 41
  • 95. Examples : Modeling of an application TimeRepeatedMultiplicationAddition origin = {0}, «tiler» paving = {{1}}, inDataTRM: [{*}] fitting = {{1}} «shaped» rm: RepeatedMultAdder [{*}] outDataTRM: [{64,*}] InDataM: [{128}] «tiler» origin = {0,0}, outM: [{64}] «tiler» paving = {{0,1}}, origin = {0,0}, fitting = {{1,0}} paving = {{0,1}}, InCoeffM: [{128}] fitting = {{1,0}} inCoeffTRM: [{128,*}] RepeatedMultAdder inDataM: [{128}] origin = {0}, «tiler» paving = {{2}}, fitting = {{0}} «shaped» ma: MultiplicationAddition [{64}] «tiler» outM: [{64}] origin = {1}, inData1: [{}] «tiler» paving = {{2}}, outM: [{}] fitting = {{0}} origin = {0}, inData2: [{}] paving = {{1}}, fitting = {{0}} «tiler» origin = {0}, inCoeff1: [{}] paving = {{2}}, fitting = {{0}} inCoeff2: [{}] origin = {1}, «tiler» paving = {{2}}, nCoeffM: [{128}] fitting = {{0}} MultiplicationAddition inData1: [{}] inData2: [{}] outM: [{}] inCoeff1: [{}] inCoeff2: [{}] (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 29 / 41
  • 96. Examples : Deploying the modeled application MultiplicationAddition InData1: [{}] outM: [{}] «Configuration» ConfigurationID = DSPMode «implements» «implements» «implements» InitialState = true ip = [DSPCase] «virtualIP» «configuration» «implements» VirtualMultAdder «implements» DSPConfiguration VIPinData1 VIPoutM «configuration» IfelseConfiguration «implements» «implements» «implements» «implements» «softwareIP» «softwareIP» IfThenElse DSPCase «implements» «implements» IPinData1 IPoutM IPinData1 IPoutM «Configuration» ConfigurationID = IfelseMode InitialState = false «SoftwareIP» ip = [IfThenElse] «SoftwareIP» language = VHDL language = VHDL logicalUnits = 0.03% logicalUnits = 0.026% (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 29 / 41
  • 97. Examples : Modeling of control concepts State Graph, Mode Switch Component etc ... StateGraph Gaspard State Graph Component when ifelse_event and not dsp_event istate: Statevalues [{}] ostate: Statevalues [{}] dsp_event: Boolean [{}] modevalue: Modes [{}] State_DSP State_Ifelse when dsp_event ifelse_event: Boolean [{}] and not ifelse_event all all Mode Switch Component cf1: DSPConfiguration Mode: Modes [{}] cf2: IfelseConfiguration (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 29 / 41
  • 98. Examples : Modeling of control concepts Macro Component Macro Component i_state: Statevalues [{}] gsgc: Gaspard State GraphComponent ostate: Statevalues [{}] istate: Statevalues [{}] dsp_e: Boolean [{}] o_state: Statevalues [{}] dsp_event: Boolean [{}] modevalue: Modes [{}] ifelse_e: Boolean [{}] ifelse_event: Boolean [{}] msc: Mode Switch Component Mode: Modes [{}] DSPMode IfelseMode : Mode Switch Component : Mode Switch Component : IfelseConfiguration : DSPConfiguration (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 29 / 41
  • 99. Examples : Modeling of control concepts Mode Automata Deployed Automata «interRepetition» repetitionShapeDependence = {-1} «shaped» «defaultLink» mc: Macro Component [{*}] defaultin: Statevalues [{}] origin = {0}, i_state: Statevalues [{}] «tiler» paving = {{1}}, fitting = {{0}} dsp_e: Boolean [{}] o_state: Statevalues [{}] dsp_event: Boolean [{*}] ifelse_e: Boolean [{}] ifelse_event: Boolean [{*}] «tiler» origin = {0}, paving = {{1}}, fitting = {{0}} (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 29 / 41
  • 100. Extension of RTL metamodel in Gaspard2 Before : 35 Metaclasses Now : 65 Metaclasses Before : 85 Metarelations Now : 170 Metarelations Single hardware accelerator Multiple hardware No aspects of control accelerators No dynamic aspects Aspects of control Dynamic aspects S. Le Beux. Un flot de conception pour applications de traitement du signal systématique implémentées sur FPGA à base d’Ingénierie Dirigée par les Modèles.
  • 101. USTL. 2007
  • 102. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 30 / 41
  • 103. Extension of RTL metamodel in Gaspard2 Overview RTL_DataType type RTL_Field atribute model type 0..* RTL_ModelType 1..1 0..* nbbits : EInt 1..1 type 1..1 RTL_PrimitiveType RTL_ComplexType complexType 1..1 RTL_Element RTL_Enumerate owner value RTL_EnumValue 1..1 1..* RTL_NamedElement RTL_IntVector name : EString value : EInt vector 0..* RTL_Matrix model RTL_Configuration RTL_Model InitialConfiguration : EBoolean ConfigurationID : EInt configurations 0..* ownconfiguration configurationOwner 0..* files 1..1 implementations 0..* HW_Implementation 0..* HW_CodeFile ipList language : ImplementationLanguage filePath : EString 1..* implementation implementingFiles 0..* 0..* element type RTL_ConnectableElement 0..1 RTL_PortType 1..* nbbits : EInt type Collaboration 0..1 RTL_Component sourcePort targetPort type clockFrequency : EInt 1..1 0..1 hwcomponent controlcomponent 1..1 1..1 nbLEs : EInt 0..1 nbDSPblocks : EInt DynamicPwr : EInt 0..* 1..1 Control_Node tilerOwner portImplementation RTL_Tiler 1..1 RTL_Port owner implementation HW_PortImplementation 1..* ports 0..* type : EString ref owner 1..1 RTL_Connector owner RTL_Hierarchical 0..1 RTL_Elementary connector connect 0..* 1..1 owner rst RTL_InputTiler RTL_OutputTiler 1..1 RTL_InputPort RTL_OutputPort 1..1 HW_TE clk 1..1 role owncomponent subConnector 0..* 1..1 RTL_SubConnector 0..* HW_RepetitiveComponent HW_CompoundComponent Control_RepetitiveComponent Control_CompoundComponent sublinks 0..* HW_delayedSubConnector delay : EInt refDefaultLink 0..* refTilerInstance refControlComponentInstance refInterrepetition 1..* componentinstance 0..* 1..1 0..* refControlTilerInstance 1..* HW_ComponentInstance Control_ComponentInstance refComponentInstance 1..1 owner master componentinstance port_instance 1..1 1..1 0..* 0..* RTL_PortInstance portsinstance sourceIndex 0..1 targetIndex 0..1 0..* dim 0..1 RTL_RepetitionConnector dim RTL_Shape 0..1 patternShape 0..1 value : EInt dim repetitionSpace 0..1 0..1 dim repetitionDim 0..1 0..1 RTL_Signal dim 0..1 signal points 0..* repetitionSize 0..* 0..1 patternSize RTL_DefaultRepetition 0..1 DepRepOwner 1..1 RTL_DefaultLink RTL_Interrepetition (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 30 / 41
  • 104. Extension of RTL metamodel in Gaspard2 Configurations, Implementations ... (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 30 / 41
  • 105. Extension of RTL metamodel in Gaspard2 Control Node, Collaborations ... (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 30 / 41
  • 106. Extension of RTL metamodel in Gaspard2 Automaton ... (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 30 / 41
  • 107. Model Transformations Model-to-Model Transformations UML2MARTE Extended
  • 108. MARTE2RTL Developed entirely during
  • 109. thesis
  • 110. 4500+ lines of QVTO code
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  • 112. Model-to-Text Transformation
  • 113. RTL2CODE Extended (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 31 / 41
  • 114. Model TransformationsUML2MARTE rules overview Notion of state graphs, collaborations, configurations ... # # # $# # #
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  • 119. Model TransformationsMARTE2RTL rules overview Control aspects, dynamic hardware accelerator concepts ...
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  • 124. Outline : Case Study application
  • 125. (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 32 / 41
  • 126. Case study : Delay Estimation Correlation ModuleOverview MARTE based specification of a dynamically reconfigurable DECM in an anti-collision radar detection system Code generation via Gaspard2 Simulation and Synthesis : Xilinx tools Implemented on a Xilinx Virtex II-Pro XC2VP30 FPGA I. Quadri et al. MARTE based design flow for partially reconfigurable Systems-on-Chips. VLSI-SoC. Brazil. 2009 I. Quadri et al. Model based design flow for implementing an Anti-Collision Radar system. ITS-T. France. 2009 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 32 / 41
  • 127. Case study : Delay Estimation Correlation ModuleModeling using extended MARTE concepts Modeling of the application (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 33 / 41
  • 128. Case study : Delay Estimation Correlation ModuleModeling using extended MARTE concepts Deploying the application MultiplicationAddition CoeffGen inData1: Integer rage -8 to 7 [{}] outData: Integer rage -8 to 7 [{}] outCoeffGen: Integer rage -1 to 1 [{}] inData2: Integer rage -8 to 7 [{}] inCoeff1: Integer rage -1 to 1 [{}] «Configuration» ConfigurationID = DSPMode inCoeff2: Integer rage -1 to 1 [{}] InitialState = true «implements» ip = [MyMultAddDSPVHDL,CoeffGenVHDL, AdditionVDHL,DataGenVHDL] «implements» «implements» «configuration» «implements» «implements» DECM DSPConfiguration «implements» «implements» «implements» «implements» «implements» «virtualIP» VirtualCoeff VIPinData1 «virtualIP» vcoeff: Integer rage -1 to 1 VirtualMultAdder «implements» VIPinData2 «configuration» «implements» VIPoutM DECM IfelseConfiguration VIPinCoeff1 «implements» VIPinCoeff2 «implements» «implements» «implements» «implements» «implements» «implements» «implements» «Configuration» «implements» ConfigurationID = IfelseMode IPinData1 «softwareIP» «softwareIP» InitialState = false IPinData1 MyMultAddIfelse «softwareIP» ip = [MyMultAddIfelseVHDL,CoeffGenVHDL, MyMultAddDSP «implements» «implements» IPinData2 myCoeffGenVHDL AdditionVDHL,DataGenVHDL] IPinData2 IPoutM «implements» IPinCoeff1 IPinCoeff1 IPoutM «implements» IPinCoeff2 IPinCoeff2 IPOutCoeffGen: Integer rage -1 to 1 «SoftwareIP» «SoftwareIP» language = VHDL language = VHDL «SoftwareIP» logicalUnits = 0.03% logicalUnits = 0.026% language = VHDL logicalUnits = 0.010% (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 33 / 41
  • 129. Case study : Delay Estimation Correlation ModuleModeling using extended MARTE concepts Control concepts DECM State Graph Component DECM MSC istate: Statevalues [{}] ostate: Statevalues [{}] cf1: DECM DSPConfiguration Mode: Modes [{}] dsp_event: Boolean [{}] modevalue: Modes [{}] cf2: DECM IfelseConfiguration ifelse_event: Boolean [{}] DSPMode IfelseMode : DECM MSC : DECM MSC : DECM IfelseConfiguration : DECM DSPConfiguration DECM Mode Automata «interRepetition» repetitionShapeDependence = {-1} «shaped» «defaultLink» mc: Macro Component [{*}] defaultin: Statevalues [{}] origin = {0}, i_state: Statevalues [{}] «tiler» paving = {{1}}, fitting = {{0}} dsp_e: Boolean [{}] o_state: Statevalues [{}] dsp_event: Boolean [{*}] ifelse_e: Boolean [{}] ifelse_event: Boolean [{*}] «tiler» origin = {0}, paving = {{1}}, fitting = {{0}} (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 33 / 41
  • 130. Case study : Delay Estimation Correlation ModuleCode generation in Gaspard2 Automatic code generation via model transformations (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 34 / 41
  • 131. Case studySimulation and Synthesis Peaks observed for DSP configuration (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 35 / 41
  • 132. Case studySimulation and Synthesis Peaks observed for If-then-else configuration (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 35 / 41
  • 133. Case study : Delay Estimation Correlation ModuleImplementing Partial Dynamic Reconfiguration Processor submodule created in EDK DECM wrapped and integrated in overall design (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 36 / 41
  • 134. Case study : Delay Estimation Correlation ModuleImplementing Partial Dynamic Reconfiguration Processor submodule created in EDK DECM wrapped and integrated in overall design (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 36 / 41
  • 135. Case study : Delay Estimation Correlation ModuleAfter placement and routing
  • 136. DSP Configuration If-then-else Configuration Slices 1272/13696 (9.287%) 1186/13696 (8.659%) Slice FlipFlops 2084/27392 (7.608%) 1944/27392 (7.096%) LUTs 1584/27392 (5.782%) 1836/27392 (6.702%) Reconfiguration Time (secs) 1.45 1.41 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 37 / 41
  • 137. Case study : Delay Estimation Correlation ModuleDesign Space Exploration : Choosing a softcore processor
  • 138. DSP configuration If-then-else Configuration PowerPC 1.45 1.41 Microblaze 0.85 0.79 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 38 / 41
  • 139. Case study : Delay Estimation Correlation ModuleDesign Space Exploration : Changing layout of reconfigurable region DSP Configuration If-then-else Configuration Slices 1272/13696 (9.287%) 1186/13696 (8.659%) Slice FlipFlops 2084/27392 (7.608%) 1944/27392 (7.096%) LUTs 1584/27392 (5.782%) 1836/27392 (6.702%) Reconfig. Time (secs) 2.87 2.85 (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 39 / 41
  • 140. Conclusion Model-driven design flow for FPGA based reconfigurable SoCs MARTE profile and metamodel Generic control semantics At different SoC design levels Extension of IP deployment level QoS based configurations RTL metamodel with dynamic aspects Model transformation chain from UML diagrams Experimental validation Dynamically reconfigurable DECM (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 40 / 41
  • 141. Perspectives MARTE semantics for (re)configurability Extended profile for reconfigurability I. Quadri et al. Modeling of Configurations for Embedded System Implementations in MARTE. M-BED at DATE. Germany. 2010 Integration with commercial EDA Tools Xilinx ISE .. Spring 2010.. New partial reconfiguration flow ! (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 41 / 41
  • 142. Publications Publication summary Overall 13(+1) publications during thesis 1 (Hindawi) + 1 (InderScience : awaiting final acceptance) 1 in submission (Journal of Systems Architecture) 2 book chapters (Springer, IGI-Global) 4 international conferences VLSI-SoC 09, ITS-T 09 .. 1 in submission (DSD 10) 4 international workshops ESTIMedia 08, M-BED at DATE 2010 .. 2 invited papers 3 invited talks, poster presentations GDR SoC/SIP, FETCH 09 Several INRIA research reports http ://marte-fpga.blogspot.com/ Under development ! (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 41 / 41
  • 143. Questions Questions ? (Imran Rafiq QUADRI - PhD Defense) 20th April 2010 41 / 41

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